1485 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_init()
1488 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_emac_init()
1560 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_umac_enable()
1564 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_umac_enable()
1675 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1679 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1705 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_xmac_init()
1709 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_xmac_init()
1823 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_emac_enable()
2415 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_bmac_enable()
2420 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,  in bnx2x_bmac_enable()
3339 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_serdes_deassert()
3341 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_serdes_deassert()
3375 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);  in bnx2x_xgxs_deassert()
3377 	REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);  in bnx2x_xgxs_deassert()
6601 	REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,  in bnx2x_int_link_reset()
12563 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
12567 			REG_WR(bp, GRCBASE_MISC +  in bnx2x_avoid_link_flap()
12826 		REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,  in bnx2x_link_reset()