Lines Matching refs:bp
224 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_en() argument
226 u32 val = REG_RD(bp, reg); in bnx2x_bits_en()
229 REG_WR(bp, reg, val); in bnx2x_bits_en()
233 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits) in bnx2x_bits_dis() argument
235 u32 val = REG_RD(bp, reg); in bnx2x_bits_dis()
238 REG_WR(bp, reg, val); in bnx2x_bits_dis()
255 struct bnx2x *bp = params->bp; in bnx2x_check_lfa() local
258 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
266 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
273 link_status = REG_RD(bp, params->shmem_base + in bnx2x_check_lfa()
302 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
311 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
320 saved_val = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
330 cur_speed_cap_mask = REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
343 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
353 eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_check_lfa()
372 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en) in bnx2x_get_epio() argument
384 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_get_epio()
385 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
387 *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; in bnx2x_get_epio()
389 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en) in bnx2x_set_epio() argument
401 gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS); in bnx2x_set_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
410 gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE); in bnx2x_set_epio()
411 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
414 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val) in bnx2x_set_cfg_pin() argument
419 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_set_cfg_pin()
423 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port); in bnx2x_set_cfg_pin()
427 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val) in bnx2x_get_cfg_pin() argument
432 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val); in bnx2x_get_cfg_pin()
436 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_get_cfg_pin()
447 struct bnx2x *bp = params->bp; in bnx2x_ets_e2e3a0_disabled() local
458 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
467 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
482 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
483 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
490 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
492 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
493 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
495 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
538 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_nig() local
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
576 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_nig_disabled() local
585 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
586 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
588 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
589 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
594 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
602 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
605 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
618 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
620 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
644 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
645 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
660 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf() local
679 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
692 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_pbf_disabled() local
705 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
708 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
713 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
716 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
722 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
725 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
739 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
751 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_disabled() local
753 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_disabled()
774 struct bnx2x *bp = params->bp; in bnx2x_ets_disabled() local
777 if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp))) in bnx2x_ets_disabled()
779 else if (CHIP_IS_E3B0(bp)) in bnx2x_ets_disabled()
799 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_cli_map() local
806 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
809 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
812 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
816 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
828 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp, in bnx2x_ets_e3b0_set_cos_bw() argument
889 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
891 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
905 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_get_total_bw() local
965 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_pri_to_cos_set() local
1046 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_sp_set_pri_cli_reg() local
1113 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1122 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1127 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1140 struct bnx2x *bp = params->bp; in bnx2x_ets_e3b0_config() local
1153 if (!CHIP_IS_E3B0(bp)) { in bnx2x_ets_e3b0_config()
1191 bp, cos_entry, min_w_val_nig, min_w_val_pbf, in bnx2x_ets_e3b0_config()
1241 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit_common() local
1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1262 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1265 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1276 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1278 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1286 struct bnx2x *bp = params->bp; in bnx2x_ets_bw_limit() local
1307 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1308 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1310 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1311 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1317 struct bnx2x *bp = params->bp; in bnx2x_ets_strict() local
1328 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1332 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1334 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1336 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1339 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1349 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1361 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_xmac() local
1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1400 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1401 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1406 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1411 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1421 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, in bnx2x_set_mdio_clk() argument
1429 cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_set_mdio_clk()
1431 if (USES_WARPCORE(bp)) in bnx2x_set_mdio_clk()
1447 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1451 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp, in bnx2x_set_mdio_emac_per_phy() argument
1458 bnx2x_set_mdio_clk(bp, params->chip_id, in bnx2x_set_mdio_emac_per_phy()
1462 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp) in bnx2x_is_4_port_mode() argument
1466 port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_is_4_port_mode()
1472 return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_is_4_port_mode()
1479 struct bnx2x *bp = params->bp; in bnx2x_emac_init() local
1485 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1493 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1494 EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); in bnx2x_emac_init()
1498 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_init()
1507 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_emac_init()
1511 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val); in bnx2x_emac_init()
1517 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val); in bnx2x_emac_init()
1524 struct bnx2x *bp = params->bp; in bnx2x_set_xumac_nig() local
1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1538 struct bnx2x *bp = params->bp; in bnx2x_set_umac_rxtx() local
1539 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_umac_rxtx()
1542 val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG); in bnx2x_set_umac_rxtx()
1550 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1558 struct bnx2x *bp = params->bp; in bnx2x_umac_enable() local
1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1570 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1603 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1622 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1630 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1639 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1644 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1654 struct bnx2x *bp = params->bp; in bnx2x_xmac_init() local
1655 u32 is_port4mode = bnx2x_is_4_port_mode(bp); in bnx2x_xmac_init()
1663 if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || in bnx2x_xmac_init()
1664 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || in bnx2x_xmac_init()
1665 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) && in bnx2x_xmac_init()
1667 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_xmac_init()
1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1685 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1691 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1696 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1701 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1717 struct bnx2x *bp = params->bp; in bnx2x_set_xmac_rxtx() local
1721 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_xmac_rxtx()
1727 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI); in bnx2x_set_xmac_rxtx()
1728 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1733 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL); in bnx2x_set_xmac_rxtx()
1738 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1746 struct bnx2x *bp = params->bp; in bnx2x_xmac_enable() local
1760 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1766 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1769 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1770 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1775 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1778 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1785 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1786 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1803 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1815 struct bnx2x *bp = params->bp; in bnx2x_emac_enable() local
1823 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1827 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1837 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1839 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1844 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1847 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1849 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1853 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE, in bnx2x_emac_enable()
1856 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1862 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1867 bnx2x_bits_en(bp, emac_base + in bnx2x_emac_enable()
1872 bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE, in bnx2x_emac_enable()
1876 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); in bnx2x_emac_enable()
1886 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); in bnx2x_emac_enable()
1890 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, in bnx2x_emac_enable()
1895 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM, in bnx2x_emac_enable()
1902 EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val); in bnx2x_emac_enable()
1905 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE); in bnx2x_emac_enable()
1910 EMAC_WR(bp, EMAC_REG_EMAC_MODE, val); in bnx2x_emac_enable()
1913 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1916 EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE, in bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1924 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1925 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1926 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1929 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1936 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1937 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1939 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1949 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac1() local
1961 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1971 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac1()
1982 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_bmac2() local
1994 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2005 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2017 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, in bnx2x_update_pfc_bmac2()
2028 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2041 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, in bnx2x_update_pfc_bmac2()
2056 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_update_pfc_bmac2()
2064 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp, in bnx2x_pfc_nig_rx_priority_mask() argument
2103 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2109 struct bnx2x *bp = params->bp; in bnx2x_update_mng() local
2111 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2118 struct bnx2x *bp = params->bp; in bnx2x_update_link_attr() local
2120 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_update_link_attr()
2121 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2133 struct bnx2x *bp = params->bp; in bnx2x_update_pfc_nig() local
2144 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2153 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2174 if (CHIP_IS_E3(bp)) in bnx2x_update_pfc_nig()
2175 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2177 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2181 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2184 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2187 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2190 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2194 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2198 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2206 bnx2x_pfc_nig_rx_priority_mask(bp, i, in bnx2x_update_pfc_nig()
2209 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2213 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2217 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2231 struct bnx2x *bp = params->bp; in bnx2x_update_pfc() local
2249 if (CHIP_IS_E3(bp)) { in bnx2x_update_pfc()
2253 val = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_update_pfc()
2261 if (CHIP_IS_E2(bp)) in bnx2x_update_pfc()
2271 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2280 struct bnx2x *bp = params->bp; in bnx2x_bmac1_enable() local
2292 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac1_enable()
2302 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); in bnx2x_bmac1_enable()
2312 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac1_enable()
2317 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2324 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2329 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac1_enable()
2334 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac1_enable()
2344 struct bnx2x *bp = params->bp; in bnx2x_bmac2_enable() local
2354 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); in bnx2x_bmac2_enable()
2360 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, in bnx2x_bmac2_enable()
2372 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, in bnx2x_bmac2_enable()
2380 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, in bnx2x_bmac2_enable()
2387 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2393 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2398 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); in bnx2x_bmac2_enable()
2411 struct bnx2x *bp = params->bp; in bnx2x_bmac_enable() local
2415 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2424 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2427 if (CHIP_IS_E2(bp)) in bnx2x_bmac_enable()
2431 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2432 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2439 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2440 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2441 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2442 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2443 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2444 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2450 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en) in bnx2x_set_bmac_rx() argument
2455 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4); in bnx2x_set_bmac_rx()
2457 if (CHIP_IS_E2(bp)) in bnx2x_set_bmac_rx()
2462 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_set_bmac_rx()
2466 REG_RD_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2471 REG_WR_DMAE(bp, bmac_addr, wb_data, 2); in bnx2x_set_bmac_rx()
2479 struct bnx2x *bp = params->bp; in bnx2x_pbf_update() local
2485 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2488 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4); in bnx2x_pbf_update()
2489 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2494 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2497 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8); in bnx2x_pbf_update()
2509 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2511 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2518 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2520 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2532 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2537 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2542 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2561 static u32 bnx2x_get_emac_base(struct bnx2x *bp, in bnx2x_get_emac_base() argument
2569 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2575 if (REG_RD(bp, NIG_REG_PORT_SWAP)) in bnx2x_get_emac_base()
2596 static int bnx2x_cl22_write(struct bnx2x *bp, in bnx2x_cl22_write() argument
2604 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_write()
2605 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2612 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2617 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_write()
2627 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2631 static int bnx2x_cl22_read(struct bnx2x *bp, in bnx2x_cl22_read() argument
2640 mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); in bnx2x_cl22_read()
2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2653 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl22_read()
2666 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2673 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read() argument
2681 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_read()
2682 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_read()
2683 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_read()
2687 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2693 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2698 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_read()
2706 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2714 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2719 val = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_read()
2728 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_read()
2738 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2743 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_read()
2748 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_write() argument
2756 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_cl45_write()
2757 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_write()
2758 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl); in bnx2x_cl45_write()
2762 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2769 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2774 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); in bnx2x_cl45_write()
2782 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2789 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2794 tmp = REG_RD(bp, phy->mdio_ctrl + in bnx2x_cl45_write()
2803 netdev_err(bp->dev, "MDC/MDIO access timeout\n"); in bnx2x_cl45_write()
2812 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2816 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, in bnx2x_cl45_write()
2826 struct bnx2x *bp = params->bp; in bnx2x_eee_has_cap() local
2828 if (REG_RD(bp, params->shmem2_base) <= in bnx2x_eee_has_cap()
2878 struct bnx2x *bp = params->bp; in bnx2x_eee_calc_timer() local
2893 eee_mode = ((REG_RD(bp, params->shmem_base + in bnx2x_eee_calc_timer()
2911 struct bnx2x *bp = params->bp; in bnx2x_eee_set_timers() local
2916 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2963 struct bnx2x *bp = params->bp; in bnx2x_eee_disable() local
2966 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2968 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2979 struct bnx2x *bp = params->bp; in bnx2x_eee_advertise() local
2983 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2994 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); in bnx2x_eee_advertise()
3004 struct bnx2x *bp = params->bp; in bnx2x_update_mng_eee() local
3007 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3016 struct bnx2x *bp = params->bp; in bnx2x_eee_an_resolve() local
3021 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); in bnx2x_eee_an_resolve()
3022 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); in bnx2x_eee_an_resolve()
3067 struct bnx2x *bp = params->bp; in bnx2x_bsc_module_sel() local
3070 board_cfg = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3078 sfp_ctrl = REG_RD(bp, params->shmem_base + in bnx2x_bsc_module_sel()
3085 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]); in bnx2x_bsc_module_sel()
3089 struct bnx2x *bp, in bnx2x_bsc_read() argument
3109 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3115 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3122 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3126 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3129 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3146 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3150 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3153 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND); in bnx2x_bsc_read()
3164 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); in bnx2x_bsc_read()
3175 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy, in bnx2x_cl45_read_or_write() argument
3179 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_or_write()
3180 bnx2x_cl45_write(bp, phy, devad, reg, val | or_val); in bnx2x_cl45_read_or_write()
3183 static void bnx2x_cl45_read_and_write(struct bnx2x *bp, in bnx2x_cl45_read_and_write() argument
3188 bnx2x_cl45_read(bp, phy, devad, reg, &val); in bnx2x_cl45_read_and_write()
3189 bnx2x_cl45_write(bp, phy, devad, reg, val & and_val); in bnx2x_cl45_read_and_write()
3201 return bnx2x_cl45_read(params->bp, in bnx2x_phy_read()
3218 return bnx2x_cl45_write(params->bp, in bnx2x_phy_write()
3229 struct bnx2x *bp = params->bp; in bnx2x_get_warpcore_lane() local
3233 path = BP_PATH(bp); in bnx2x_get_warpcore_lane()
3236 if (bnx2x_is_4_port_mode(bp)) { in bnx2x_get_warpcore_lane()
3240 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3244 path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3250 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3254 port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP); in bnx2x_get_warpcore_lane()
3264 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); in bnx2x_get_warpcore_lane()
3269 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP); in bnx2x_get_warpcore_lane()
3284 struct bnx2x *bp = params->bp; in bnx2x_set_aer_mmd() local
3292 if (USES_WARPCORE(bp)) { in bnx2x_set_aer_mmd()
3302 } else if (CHIP_IS_E2(bp)) in bnx2x_set_aer_mmd()
3307 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_aer_mmd()
3316 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port) in bnx2x_set_serdes_access() argument
3321 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3322 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3327 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3330 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port) in bnx2x_serdes_deassert() argument
3339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3343 bnx2x_set_serdes_access(bp, port); in bnx2x_serdes_deassert()
3345 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3353 struct bnx2x *bp = params->bp; in bnx2x_xgxs_specific_func() local
3357 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3358 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3366 struct bnx2x *bp = params->bp; in bnx2x_xgxs_deassert() local
3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
3385 struct bnx2x *bp = params->bp; in bnx2x_calc_ieee_aneg_adv() local
3426 struct bnx2x *bp = params->bp; in set_phy_vars() local
3469 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_set_pause() local
3471 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); in bnx2x_ext_phy_set_pause()
3488 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); in bnx2x_ext_phy_set_pause()
3526 struct bnx2x *bp = params->bp; in bnx2x_ext_phy_update_adv_fc() local
3528 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3529 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3530 } else if (CHIP_IS_E3(bp) && in bnx2x_ext_phy_update_adv_fc()
3534 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3541 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3543 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3546 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3548 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_ext_phy_update_adv_fc()
3558 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3561 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_update_adv_fc()
3617 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR2() local
3640 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR2()
3644 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR2()
3656 struct bnx2x *bp = params->bp; in bnx2x_disable_kr2() local
3679 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_disable_kr2()
3690 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_lpi_passthrough() local
3693 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3695 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_lpi_passthrough()
3703 struct bnx2x *bp = params->bp; in bnx2x_warpcore_restart_AN_KR() local
3705 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_restart_AN_KR()
3707 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_restart_AN_KR()
3719 struct bnx2x *bp = params->bp; in bnx2x_warpcore_enable_AN_KR() local
3733 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_enable_AN_KR()
3736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3740 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3751 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3760 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3763 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3771 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3776 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3779 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3782 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3787 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3791 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3797 if (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3801 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3810 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3814 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3821 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_enable_AN_KR()
3824 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3828 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3835 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3837 wc_lane_config = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_enable_AN_KR()
3840 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3855 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_enable_AN_KR()
3870 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_KR() local
3886 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_warpcore_set_10G_KR()
3891 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_10G_KR()
3894 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3897 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3900 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3903 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3908 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3911 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_10G_KR()
3915 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3919 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3923 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3927 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3929 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_KR()
3938 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_10G_XFI() local
3944 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3948 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3952 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3955 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3959 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3963 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3967 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3972 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3974 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3979 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
3989 cfg_tap_val = REG_RD(bp, params->shmem_base + in bnx2x_warpcore_set_10G_XFI()
4035 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4040 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4043 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4048 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4052 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4058 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4062 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4066 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_10G_XFI()
4074 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_20G_force_KR2() local
4076 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4080 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4085 bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4087 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4090 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4094 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4098 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4101 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4104 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4108 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4110 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4114 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_set_20G_force_KR2()
4117 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_force_KR2()
4123 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, in bnx2x_warpcore_set_20G_DXGXS() argument
4128 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4132 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4135 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4138 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4141 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4144 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4147 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4150 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4153 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4156 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4160 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4164 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4168 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4172 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_20G_DXGXS()
4182 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_sgmii_speed() local
4186 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4193 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4198 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4219 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4224 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4230 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4237 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4242 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4244 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4249 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4254 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_sgmii_speed()
4259 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp, in bnx2x_warpcore_reset_lane() argument
4265 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4271 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4273 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_reset_lane()
4281 struct bnx2x *bp = params->bp; in bnx2x_warpcore_clear_regs() local
4300 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4304 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg, in bnx2x_warpcore_clear_regs()
4308 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_clear_regs()
4313 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp, in bnx2x_get_mod_abs_int_cfg() argument
4321 if (CHIP_IS_E3(bp)) { in bnx2x_get_mod_abs_int_cfg()
4322 cfg_pin = (REG_RD(bp, shmem_base + in bnx2x_get_mod_abs_int_cfg()
4355 struct bnx2x *bp = params->bp; in bnx2x_is_sfp_module_plugged() local
4358 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, in bnx2x_is_sfp_module_plugged()
4362 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_is_sfp_module_plugged()
4374 struct bnx2x *bp = params->bp; in bnx2x_warpcore_get_sigdet() local
4378 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, in bnx2x_warpcore_get_sigdet()
4388 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_runtime() local
4399 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_runtime()
4407 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4417 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_runtime()
4418 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4421 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_config_runtime()
4441 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_sfi() local
4458 struct bnx2x *bp = params->bp; in bnx2x_sfp_e3_set_transmitter() local
4462 cfg_pin = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e3_set_transmitter()
4470 bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4472 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1); in bnx2x_sfp_e3_set_transmitter()
4479 struct bnx2x *bp = params->bp; in bnx2x_warpcore_config_init() local
4483 serdes_net_if = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_config_init()
4491 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_config_init()
4557 bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane); in bnx2x_warpcore_config_init()
4579 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4586 struct bnx2x *bp = params->bp; in bnx2x_warpcore_link_reset() local
4589 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_warpcore_link_reset()
4592 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_link_reset()
4596 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4599 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4603 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_warpcore_link_reset()
4606 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4610 bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4614 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4622 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4631 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_link_reset()
4641 struct bnx2x *bp = params->bp; in bnx2x_set_warpcore_loopback() local
4652 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_set_warpcore_loopback()
4655 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4660 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4665 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4673 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4676 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_set_warpcore_loopback()
4686 struct bnx2x *bp = params->bp; in bnx2x_sync_link() local
4754 USES_WARPCORE(bp) && in bnx2x_sync_link()
4761 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4766 if (USES_WARPCORE(bp)) in bnx2x_sync_link()
4792 struct bnx2x *bp = params->bp; in bnx2x_link_status_update() local
4798 vars->link_status = REG_RD(bp, params->shmem_base + in bnx2x_link_status_update()
4808 vars->eee_status = REG_RD(bp, params->shmem2_base + in bnx2x_link_status_update()
4818 media_types = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4836 vars->aeu_int_mask = REG_RD(bp, sync_offset); in bnx2x_link_status_update()
4846 if (SHMEM2_HAS(bp, link_attr_sync)) in bnx2x_link_status_update()
4847 params->link_attr_sync = SHMEM2_RD(bp, in bnx2x_link_status_update()
4859 struct bnx2x *bp = params->bp; in bnx2x_set_master_ln() local
4866 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4871 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_master_ln()
4881 struct bnx2x *bp = params->bp; in bnx2x_reset_unicore() local
4884 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4889 CL22_WR_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4895 bnx2x_set_serdes_access(bp, params->port); in bnx2x_reset_unicore()
4902 CL22_RD_OVER_CL45(bp, phy, in bnx2x_reset_unicore()
4913 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_reset_unicore()
4924 struct bnx2x *bp = params->bp; in bnx2x_set_swap_lanes() local
4938 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4945 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4951 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4957 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_swap_lanes()
4966 struct bnx2x *bp = params->bp; in bnx2x_set_parallel_detection() local
4968 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4978 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4988 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
4993 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5002 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5008 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_parallel_detection()
5021 struct bnx2x *bp = params->bp; in bnx2x_set_autoneg() local
5025 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5036 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5042 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5053 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5058 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5071 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5078 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5084 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5092 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5103 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5114 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_autoneg()
5124 struct bnx2x *bp = params->bp; in bnx2x_program_serdes() local
5128 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5136 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5143 CL22_RD_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5163 CL22_WR_OVER_CL45(bp, phy, in bnx2x_program_serdes()
5172 struct bnx2x *bp = params->bp; in bnx2x_set_brcm_cl37_advertisement() local
5180 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5184 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_brcm_cl37_advertisement()
5193 struct bnx2x *bp = params->bp; in bnx2x_set_ieee_aneg_advertisement() local
5197 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5200 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_ieee_aneg_advertisement()
5214 struct bnx2x *bp = params->bp; in bnx2x_restart_autoneg() local
5221 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5226 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5234 CL22_RD_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5241 CL22_WR_OVER_CL45(bp, phy, in bnx2x_restart_autoneg()
5254 struct bnx2x *bp = params->bp; in bnx2x_initialize_sgmii_process() local
5259 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5268 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5278 CL22_RD_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5309 CL22_WR_OVER_CL45(bp, phy, in bnx2x_initialize_sgmii_process()
5325 struct bnx2x *bp = params->bp; in bnx2x_direct_parallel_detect_used() local
5329 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5333 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5343 CL22_RD_OVER_CL45(bp, phy, in bnx2x_direct_parallel_detect_used()
5364 struct bnx2x *bp = params->bp; in bnx2x_update_adv_fc() local
5371 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5375 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5385 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5389 CL22_RD_OVER_CL45(bp, phy, in bnx2x_update_adv_fc()
5408 struct bnx2x *bp = params->bp; in bnx2x_flow_ctrl_resolve() local
5434 struct bnx2x *bp = params->bp; in bnx2x_check_fallback_to_cl37() local
5438 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5446 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5453 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5469 CL22_RD_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5490 CL22_WR_OVER_CL45(bp, phy, in bnx2x_check_fallback_to_cl37()
5519 struct bnx2x *bp = params->bp; in bnx2x_get_link_speed_duplex() local
5607 struct bnx2x *bp = params->bp; in bnx2x_link_settings_status() local
5613 CL22_RD_OVER_CL45(bp, phy, in bnx2x_link_settings_status()
5650 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, in bnx2x_link_settings_status()
5661 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, in bnx2x_link_settings_status()
5681 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_status() local
5689 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5691 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5697 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5699 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5707 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5718 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5720 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5728 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5736 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5752 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_warpcore_read_status()
5763 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5777 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5780 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_read_status()
5804 struct bnx2x *bp = params->bp; in bnx2x_set_gmii_tx_driver() local
5811 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5825 CL22_RD_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5834 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_gmii_tx_driver()
5844 struct bnx2x *bp = params->bp; in bnx2x_emac_program() local
5849 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + in bnx2x_emac_program()
5880 bnx2x_bits_en(bp, in bnx2x_emac_program()
5893 struct bnx2x *bp = params->bp; in bnx2x_set_preemphasis() local
5897 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5905 CL22_WR_OVER_CL45(bp, phy, in bnx2x_set_preemphasis()
5916 struct bnx2x *bp = params->bp; in bnx2x_xgxs_config_init() local
6000 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp, in bnx2x_wait_reset_complete() argument
6008 bnx2x_cl22_read(bp, phy, in bnx2x_wait_reset_complete()
6011 bnx2x_cl45_read(bp, phy, in bnx2x_wait_reset_complete()
6020 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_wait_reset_complete()
6031 struct bnx2x *bp = params->bp; in bnx2x_link_int_enable() local
6034 if (CHIP_IS_E3(bp)) { in bnx2x_link_int_enable()
6059 bnx2x_bits_en(bp, in bnx2x_link_int_enable()
6065 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_int_enable()
6067 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_int_enable()
6068 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), in bnx2x_link_int_enable()
6069 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); in bnx2x_link_int_enable()
6071 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_int_enable()
6072 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_int_enable()
6075 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port, in bnx2x_rearm_latch_signal() argument
6085 latch_status = REG_RD(bp, in bnx2x_rearm_latch_signal()
6090 bnx2x_bits_en(bp, in bnx2x_rearm_latch_signal()
6095 bnx2x_bits_dis(bp, in bnx2x_rearm_latch_signal()
6103 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6112 struct bnx2x *bp = params->bp; in bnx2x_link_int_ack() local
6118 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, in bnx2x_link_int_ack()
6123 if (USES_WARPCORE(bp)) in bnx2x_link_int_ack()
6143 bnx2x_bits_en(bp, in bnx2x_link_int_ack()
6198 struct bnx2x *bp; in bnx2x_get_ext_phy_fw_version() local
6205 bp = params->bp; in bnx2x_get_ext_phy_fw_version()
6209 spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr); in bnx2x_get_ext_phy_fw_version()
6219 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr); in bnx2x_get_ext_phy_fw_version()
6239 struct bnx2x *bp = params->bp; in bnx2x_set_xgxs_loopback() local
6246 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6248 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD + in bnx2x_set_xgxs_loopback()
6251 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6255 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6261 bnx2x_cl45_write(bp, phy, in bnx2x_set_xgxs_loopback()
6270 if (!CHIP_IS_E3(bp)) { in bnx2x_set_xgxs_loopback()
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6278 bnx2x_cl45_read(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6282 bnx2x_cl45_write(bp, phy, 5, in bnx2x_set_xgxs_loopback()
6299 struct bnx2x *bp = params->bp; in bnx2x_set_led() local
6314 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6315 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6318 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6327 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp); in bnx2x_set_led()
6341 CHIP_IS_E2(bp) && params->num_phys == 2) { in bnx2x_set_led()
6345 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6346 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6348 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6349 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6363 if ((!CHIP_IS_E3(bp)) || in bnx2x_set_led()
6364 (CHIP_IS_E3(bp) && in bnx2x_set_led()
6366 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6368 if (CHIP_IS_E1x(bp) || in bnx2x_set_led()
6369 CHIP_IS_E2(bp) || in bnx2x_set_led()
6371 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6373 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6378 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6379 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6380 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | in bnx2x_set_led()
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6396 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6398 if (CHIP_IS_E3(bp)) in bnx2x_set_led()
6399 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6402 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6404 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6406 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); in bnx2x_set_led()
6407 EMAC_WR(bp, EMAC_REG_EMAC_LED, in bnx2x_set_led()
6410 if (CHIP_IS_E1(bp) && in bnx2x_set_led()
6416 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6418 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6441 struct bnx2x *bp = params->bp; in bnx2x_test_link() local
6447 if (CHIP_IS_E3(bp)) { in bnx2x_test_link()
6452 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6454 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6460 bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD, in bnx2x_test_link()
6470 CL22_RD_OVER_CL45(bp, int_phy, in bnx2x_test_link()
6523 struct bnx2x *bp = params->bp; in bnx2x_link_initialize() local
6535 if (!USES_WARPCORE(bp)) in bnx2x_link_initialize()
6546 (CHIP_IS_E1x(bp) || in bnx2x_link_initialize()
6547 CHIP_IS_E2(bp))) in bnx2x_link_initialize()
6588 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + in bnx2x_link_initialize()
6601 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6608 struct bnx2x *bp = params->bp; in bnx2x_common_ext_link_reset() local
6611 if (CHIP_IS_E2(bp)) in bnx2x_common_ext_link_reset()
6612 gpio_port = BP_PATH(bp); in bnx2x_common_ext_link_reset()
6615 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_common_ext_link_reset()
6618 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_common_ext_link_reset()
6627 struct bnx2x *bp = params->bp; in bnx2x_update_link_down() local
6642 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6645 if (!CHIP_IS_E3(bp)) in bnx2x_update_link_down()
6646 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6650 if (CHIP_IS_E1x(bp) || in bnx2x_update_link_down()
6651 CHIP_IS_E2(bp)) in bnx2x_update_link_down()
6652 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_update_link_down()
6654 if (CHIP_IS_E3(bp)) { in bnx2x_update_link_down()
6656 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6658 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6675 struct bnx2x *bp = params->bp; in bnx2x_update_link_up() local
6690 if (USES_WARPCORE(bp)) { in bnx2x_update_link_up()
6707 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6709 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6710 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6714 if ((CHIP_IS_E1x(bp) || in bnx2x_update_link_up()
6715 CHIP_IS_E2(bp))) { in bnx2x_update_link_up()
6741 if (CHIP_IS_E1x(bp)) in bnx2x_update_link_up()
6746 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6764 struct bnx2x *bp = params->bp; in bnx2x_chng_link_count() local
6768 if (!(SHMEM2_HAS(bp, link_change_count))) in bnx2x_chng_link_count()
6776 val = REG_RD(bp, addr) + 1; in bnx2x_chng_link_count()
6777 REG_WR(bp, addr, val); in bnx2x_chng_link_count()
6794 struct bnx2x *bp = params->bp; in bnx2x_link_update() local
6819 if (USES_WARPCORE(bp)) in bnx2x_link_update()
6824 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); in bnx2x_link_update()
6826 is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + in bnx2x_link_update()
6829 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), in bnx2x_link_update()
6831 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); in bnx2x_link_update()
6834 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_update()
6835 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_update()
6838 if (!CHIP_IS_E3(bp)) in bnx2x_link_update()
6839 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6957 bnx2x_rearm_latch_signal(bp, port, in bnx2x_link_update()
6980 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
7043 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); in bnx2x_link_update()
7051 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port) in bnx2x_ext_phy_hw_reset() argument
7053 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7056 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_ext_phy_hw_reset()
7060 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port, in bnx2x_save_spirom_version() argument
7067 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
7070 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp, in bnx2x_save_bcm_spirom_ver() argument
7076 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7078 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_save_bcm_spirom_ver()
7080 bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2), in bnx2x_save_bcm_spirom_ver()
7084 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp, in bnx2x_ext_phy_10G_an_resolve() argument
7089 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7092 bnx2x_cl45_read(bp, phy, in bnx2x_ext_phy_10G_an_resolve()
7108 struct bnx2x *bp = params->bp; in bnx2x_8073_resolve_fc() local
7120 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7124 bnx2x_cl45_read(bp, phy, in bnx2x_8073_resolve_fc()
7137 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp, in bnx2x_8073_8727_external_rom_boot() argument
7147 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7153 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7158 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7163 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7169 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7189 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7192 bnx2x_cl45_read(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7202 bnx2x_cl45_write(bp, phy, in bnx2x_8073_8727_external_rom_boot()
7205 bnx2x_save_bcm_spirom_ver(bp, phy, port); in bnx2x_8073_8727_external_rom_boot()
7218 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_is_snr_needed() argument
7224 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7233 bnx2x_cl45_read(bp, phy, in bnx2x_8073_is_snr_needed()
7244 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_8073_xaui_wa() argument
7248 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7263 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7282 bnx2x_cl45_read(bp, phy, in bnx2x_8073_xaui_wa()
7300 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_807x_force_10G() argument
7303 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7305 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7307 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7309 bnx2x_cl45_write(bp, phy, in bnx2x_807x_force_10G()
7318 struct bnx2x *bp = params->bp; in bnx2x_8073_set_pause_cl37() local
7319 bnx2x_cl45_read(bp, phy, in bnx2x_8073_set_pause_cl37()
7343 bnx2x_cl45_write(bp, phy, in bnx2x_8073_set_pause_cl37()
7352 struct bnx2x *bp = params->bp; in bnx2x_8073_specific_func() local
7356 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7358 bnx2x_cl45_write(bp, phy, in bnx2x_8073_specific_func()
7368 struct bnx2x *bp = params->bp; in bnx2x_8073_config_init() local
7373 if (CHIP_IS_E2(bp)) in bnx2x_8073_config_init()
7374 gpio_port = BP_PATH(bp); in bnx2x_8073_config_init()
7378 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_config_init()
7381 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8073_config_init()
7387 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7390 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7400 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7403 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7411 if (REG_RD(bp, params->shmem_base + in bnx2x_8073_config_init()
7416 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7419 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7425 bnx2x_807x_force_10G(bp, phy); in bnx2x_8073_config_init()
7429 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7456 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); in bnx2x_8073_config_init()
7457 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); in bnx2x_8073_config_init()
7464 bnx2x_cl45_read(bp, phy, in bnx2x_8073_config_init()
7477 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); in bnx2x_8073_config_init()
7480 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); in bnx2x_8073_config_init()
7481 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, in bnx2x_8073_config_init()
7486 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7492 if (bnx2x_8073_is_snr_needed(bp, phy)) in bnx2x_8073_config_init()
7493 bnx2x_cl45_write(bp, phy, in bnx2x_8073_config_init()
7498 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); in bnx2x_8073_config_init()
7500 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); in bnx2x_8073_config_init()
7506 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7516 struct bnx2x *bp = params->bp; in bnx2x_8073_read_status() local
7522 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7528 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7530 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7534 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7538 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7544 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7548 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7550 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7557 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7560 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7562 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7566 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7568 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7574 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { in bnx2x_8073_read_status()
7579 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7584 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7588 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7619 bnx2x_cl45_read(bp, phy, in bnx2x_8073_read_status()
7632 bnx2x_cl45_write(bp, phy, in bnx2x_8073_read_status()
7637 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_8073_read_status()
7643 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_8073_read_status()
7660 struct bnx2x *bp = params->bp; in bnx2x_8073_link_reset() local
7662 if (CHIP_IS_E2(bp)) in bnx2x_8073_link_reset()
7663 gpio_port = BP_PATH(bp); in bnx2x_8073_link_reset()
7668 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_link_reset()
7680 struct bnx2x *bp = params->bp; in bnx2x_8705_config_init() local
7683 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8705_config_init()
7686 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8705_config_init()
7687 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7688 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8705_config_init()
7690 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7692 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7694 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7696 bnx2x_cl45_write(bp, phy, in bnx2x_8705_config_init()
7699 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); in bnx2x_8705_config_init()
7709 struct bnx2x *bp = params->bp; in bnx2x_8705_read_status() local
7711 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7715 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7719 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7722 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7724 bnx2x_cl45_read(bp, phy, in bnx2x_8705_read_status()
7743 struct bnx2x *bp = params->bp; in bnx2x_set_disable_pmd_transmit() local
7757 bnx2x_cl45_write(bp, phy, in bnx2x_set_disable_pmd_transmit()
7766 struct bnx2x *bp = params->bp; in bnx2x_get_gpio_port() local
7767 if (CHIP_IS_E2(bp)) in bnx2x_get_gpio_port()
7768 gpio_port = BP_PATH(bp); in bnx2x_get_gpio_port()
7771 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_get_gpio_port()
7772 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_get_gpio_port()
7782 struct bnx2x *bp = params->bp; in bnx2x_sfp_e1e2_set_transmitter() local
7786 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_sfp_e1e2_set_transmitter()
7795 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7805 bnx2x_cl45_write(bp, phy, in bnx2x_sfp_e1e2_set_transmitter()
7824 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_sfp_e1e2_set_transmitter()
7837 struct bnx2x *bp = params->bp; in bnx2x_sfp_set_transmitter() local
7839 if (CHIP_IS_E3(bp)) in bnx2x_sfp_set_transmitter()
7850 struct bnx2x *bp = params->bp; in bnx2x_8726_read_sfp_module_eeprom() local
7859 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7864 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7869 bnx2x_cl45_write(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7875 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7894 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7901 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_sfp_module_eeprom()
7916 struct bnx2x *bp = params->bp; in bnx2x_warpcore_power_module() local
7918 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_warpcore_power_module()
7931 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); in bnx2x_warpcore_power_module()
7943 struct bnx2x *bp = params->bp; in bnx2x_warpcore_read_sfp_module_eeprom() local
7960 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, in bnx2x_warpcore_read_sfp_module_eeprom()
7979 struct bnx2x *bp = params->bp; in bnx2x_8727_read_sfp_module_eeprom() local
7992 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
7998 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8004 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8010 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8015 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8021 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8032 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8051 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8058 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_sfp_module_eeprom()
8074 struct bnx2x *bp = params->bp; in bnx2x_read_sfp_module_eeprom() local
8115 struct bnx2x *bp = params->bp; in bnx2x_get_edc_mode() local
8182 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_edc_mode()
8183 gport = BP_PATH(bp) + in bnx2x_get_edc_mode()
8186 netdev_err(bp->dev, in bnx2x_get_edc_mode()
8217 media_types = REG_RD(bp, sync_offset); in bnx2x_get_edc_mode()
8229 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8256 struct bnx2x *bp = params->bp; in bnx2x_verify_sfp_module() local
8262 val = REG_RD(bp, params->shmem_base + in bnx2x_verify_sfp_module()
8292 fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param); in bnx2x_verify_sfp_module()
8318 netdev_err(bp->dev, "Warning: Unqualified SFP+ module detected," in bnx2x_verify_sfp_module()
8333 struct bnx2x *bp = params->bp; in bnx2x_wait_for_sfp_module_initialized() local
8361 static void bnx2x_8727_power_module(struct bnx2x *bp, in bnx2x_8727_power_module() argument
8387 bnx2x_cl45_write(bp, phy, in bnx2x_8727_power_module()
8393 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp, in bnx2x_8726_set_limiting_mode() argument
8399 bnx2x_cl45_read(bp, phy, in bnx2x_8726_set_limiting_mode()
8408 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8422 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8426 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8430 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8434 bnx2x_cl45_write(bp, phy, in bnx2x_8726_set_limiting_mode()
8442 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp, in bnx2x_8727_set_limiting_mode() argument
8448 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8453 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8458 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_limiting_mode()
8463 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8468 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_limiting_mode()
8480 struct bnx2x *bp = params->bp; in bnx2x_8727_specific_func() local
8491 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8494 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8497 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8500 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_specific_func()
8511 bnx2x_cl45_write(bp, phy, in bnx2x_8727_specific_func()
8525 struct bnx2x *bp = params->bp; in bnx2x_set_e1e2_module_fault_led() local
8527 u32 fault_led_gpio = REG_RD(bp, params->shmem_base + in bnx2x_set_e1e2_module_fault_led()
8545 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port); in bnx2x_set_e1e2_module_fault_led()
8559 struct bnx2x *bp = params->bp; in bnx2x_set_e3_module_fault_led() local
8560 pin_cfg = (REG_RD(bp, params->shmem_base + in bnx2x_set_e3_module_fault_led()
8567 bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode); in bnx2x_set_e3_module_fault_led()
8573 struct bnx2x *bp = params->bp; in bnx2x_set_sfp_module_fault_led() local
8575 if (CHIP_IS_E3(bp)) { in bnx2x_set_sfp_module_fault_led()
8587 struct bnx2x *bp = params->bp; in bnx2x_warpcore_hw_reset() local
8590 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8593 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8594 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8595 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
8602 struct bnx2x *bp = params->bp; in bnx2x_power_sfp_module() local
8608 bnx2x_8727_power_module(params->bp, phy, power); in bnx2x_power_sfp_module()
8623 struct bnx2x *bp = params->bp; in bnx2x_warpcore_set_limiting_mode() local
8627 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8645 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8648 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_warpcore_set_limiting_mode()
8652 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_warpcore_set_limiting_mode()
8653 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8663 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8667 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode); in bnx2x_set_limiting_mode()
8678 struct bnx2x *bp = params->bp; in bnx2x_sfp_module_detection() local
8682 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_sfp_module_detection()
8732 struct bnx2x *bp = params->bp; in bnx2x_handle_module_detect_int() local
8736 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8743 if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base, in bnx2x_handle_module_detect_int()
8754 gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port); in bnx2x_handle_module_detect_int()
8758 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_handle_module_detect_int()
8762 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8767 if (CHIP_IS_E3(bp)) { in bnx2x_handle_module_detect_int()
8773 bnx2x_cl45_read(bp, phy, in bnx2x_handle_module_detect_int()
8780 bnx2x_warpcore_reset_lane(bp, phy, 1); in bnx2x_handle_module_detect_int()
8782 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8789 bnx2x_set_gpio_int(bp, gpio_num, in bnx2x_handle_module_detect_int()
8802 static void bnx2x_sfp_mask_fault(struct bnx2x *bp, in bnx2x_sfp_mask_fault() argument
8808 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8811 bnx2x_cl45_read(bp, phy, in bnx2x_sfp_mask_fault()
8815 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); in bnx2x_sfp_mask_fault()
8820 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); in bnx2x_sfp_mask_fault()
8831 struct bnx2x *bp = params->bp; in bnx2x_8706_8726_read_status() local
8834 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8837 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8706_8726_read_status()
8841 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8843 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8847 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8849 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8851 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8853 bnx2x_cl45_read(bp, phy, in bnx2x_8706_8726_read_status()
8873 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8875 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8706_8726_read_status()
8893 struct bnx2x *bp = params->bp; in bnx2x_8706_config_init() local
8895 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8706_config_init()
8898 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8706_config_init()
8899 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8900 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8706_config_init()
8904 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8919 bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val); in bnx2x_8706_config_init()
8926 bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val); in bnx2x_8706_config_init()
8933 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8936 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8940 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8947 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8951 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8954 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8957 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8961 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8963 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8966 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
8970 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8706_config_init()
8976 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8706_config_init()
8983 bnx2x_cl45_read(bp, phy, in bnx2x_8706_config_init()
8986 bnx2x_cl45_write(bp, phy, in bnx2x_8706_config_init()
9006 struct bnx2x *bp = params->bp; in bnx2x_8726_config_loopback() local
9008 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
9014 struct bnx2x *bp = params->bp; in bnx2x_8726_external_rom_boot() local
9019 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9023 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9028 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9032 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9041 bnx2x_cl45_write(bp, phy, in bnx2x_8726_external_rom_boot()
9046 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); in bnx2x_8726_external_rom_boot()
9053 struct bnx2x *bp = params->bp; in bnx2x_8726_read_status() local
9057 bnx2x_cl45_read(bp, phy, in bnx2x_8726_read_status()
9074 struct bnx2x *bp = params->bp; in bnx2x_8726_config_init() local
9077 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8726_config_init()
9078 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8726_config_init()
9091 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9093 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9095 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9097 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9109 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9111 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9113 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9115 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9117 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9122 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9124 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9129 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9140 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9145 bnx2x_cl45_write(bp, phy, in bnx2x_8726_config_init()
9158 struct bnx2x *bp = params->bp; in bnx2x_8726_link_reset() local
9161 bnx2x_cl45_write(bp, phy, in bnx2x_8726_link_reset()
9173 struct bnx2x *bp = params->bp; in bnx2x_8727_set_link_led() local
9195 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9201 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9205 bnx2x_cl45_read(bp, phy, in bnx2x_8727_set_link_led()
9211 bnx2x_cl45_write(bp, phy, in bnx2x_8727_set_link_led()
9223 struct bnx2x *bp = params->bp; in bnx2x_8727_hw_reset() local
9224 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_hw_reset()
9225 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_hw_reset()
9227 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, in bnx2x_8727_hw_reset()
9234 struct bnx2x *bp = params->bp; in bnx2x_8727_config_speed() local
9240 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9242 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9244 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9251 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_speed()
9255 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9267 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9269 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9275 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9278 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9280 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9282 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_speed()
9294 struct bnx2x *bp = params->bp; in bnx2x_8727_config_init() local
9297 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8727_config_init()
9305 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9314 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9320 bnx2x_8727_power_module(bp, phy, 1); in bnx2x_8727_config_init()
9322 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9325 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9337 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9341 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9349 tx_en_mode = REG_RD(bp, params->shmem_base + in bnx2x_8727_config_init()
9357 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9361 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9363 bnx2x_cl45_read(bp, phy, in bnx2x_8727_config_init()
9366 bnx2x_cl45_write(bp, phy, in bnx2x_8727_config_init()
9377 struct bnx2x *bp = params->bp; in bnx2x_8727_handle_mod_abs() local
9379 u32 val = REG_RD(bp, params->shmem_base + in bnx2x_8727_handle_mod_abs()
9383 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9402 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9409 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9427 bnx2x_cl45_write(bp, phy, in bnx2x_8727_handle_mod_abs()
9436 bnx2x_cl45_read(bp, phy, in bnx2x_8727_handle_mod_abs()
9464 struct bnx2x *bp = params->bp; in bnx2x_8727_read_status() local
9470 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9477 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9483 bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT, in bnx2x_8727_read_status()
9486 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9492 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9500 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9505 if (!CHIP_IS_E1x(bp)) in bnx2x_8727_read_status()
9506 oc_port = BP_PATH(bp) + (params->port << 1); in bnx2x_8727_read_status()
9510 netdev_err(bp->dev, "Error: Power fault on Port %d has " in bnx2x_8727_read_status()
9519 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9523 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9528 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9532 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9535 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9544 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9557 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9582 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9585 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, in bnx2x_8727_read_status()
9601 bnx2x_cl45_read(bp, phy, in bnx2x_8727_read_status()
9611 bnx2x_cl45_write(bp, phy, in bnx2x_8727_read_status()
9621 struct bnx2x *bp = params->bp; in bnx2x_8727_link_reset() local
9629 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9637 struct bnx2x *bp, in bnx2x_save_848xx_spirom_version() argument
9652 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9653 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff, in bnx2x_save_848xx_spirom_version()
9659 bnx2x_cl45_write(bp, phy, reg_set[i].devad, in bnx2x_save_848xx_spirom_version()
9663 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9671 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9678 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9679 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9680 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9682 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9690 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9696 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9698 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9700 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1, in bnx2x_save_848xx_spirom_version()
9705 static void bnx2x_848xx_set_led(struct bnx2x *bp, in bnx2x_848xx_set_led() argument
9719 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_led()
9725 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_led()
9730 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg, in bnx2x_848xx_set_led()
9740 bnx2x_cl45_read_or_write(bp, phy, in bnx2x_848xx_set_led()
9749 struct bnx2x *bp = params->bp; in bnx2x_848xx_specific_func() local
9755 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848xx_specific_func()
9761 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4, in bnx2x_848xx_specific_func()
9764 bnx2x_848xx_set_led(bp, phy); in bnx2x_848xx_specific_func()
9773 struct bnx2x *bp = params->bp; in bnx2x_848xx_cmn_config_init() local
9777 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9781 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9786 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9790 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_cmn_config_init()
9809 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9857 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9869 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9875 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9888 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9900 bp, phy, in bnx2x_848xx_cmn_config_init()
9904 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9908 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_cmn_config_init()
9920 struct bnx2x *bp = params->bp; in bnx2x_8481_config_init() local
9922 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8481_config_init()
9926 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_8481_config_init()
9927 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_8481_config_init()
9929 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); in bnx2x_8481_config_init()
9941 struct bnx2x *bp = params->bp; in bnx2x_84833_cmd_hdlr() local
9943 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9947 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9960 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9964 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9967 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9981 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9985 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_84833_cmd_hdlr()
9998 struct bnx2x *bp = params->bp; in bnx2x_84833_pair_swap_cfg() local
10001 pair_swap = REG_RD(bp, params->shmem_base + in bnx2x_84833_pair_swap_cfg()
10020 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp, in bnx2x_84833_get_reset_gpios() argument
10027 if (CHIP_IS_E3(bp)) { in bnx2x_84833_get_reset_gpios()
10031 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
10044 reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] + in bnx2x_84833_get_reset_gpios()
10061 struct bnx2x *bp = params->bp; in bnx2x_84833_hw_reset_phy() local
10063 u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base + in bnx2x_84833_hw_reset_phy()
10070 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10073 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_84833_hw_reset_phy()
10080 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, in bnx2x_84833_hw_reset_phy()
10083 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_hw_reset_phy()
10096 struct bnx2x *bp = params->bp; in bnx2x_8483x_disable_eee() local
10117 struct bnx2x *bp = params->bp; in bnx2x_8483x_enable_eee() local
10135 struct bnx2x *bp = params->bp; in bnx2x_848x3_config_init() local
10144 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_config_init()
10145 port = BP_PATH(bp); in bnx2x_848x3_config_init()
10150 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_config_init()
10155 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_config_init()
10160 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_848x3_config_init()
10177 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10185 if (CHIP_IS_E3(bp)) { in bnx2x_848x3_config_init()
10216 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10239 bnx2x_save_848xx_spirom_version(phy, bp, params->port); in bnx2x_848x3_config_init()
10242 u32 cms_enable = REG_RD(bp, params->shmem_base + in bnx2x_848x3_config_init()
10247 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10253 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10257 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, in bnx2x_848x3_config_init()
10289 bnx2x_cl45_read_and_write(bp, phy, in bnx2x_848x3_config_init()
10301 struct bnx2x *bp = params->bp; in bnx2x_848xx_read_status() local
10308 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10310 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10320 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_848xx_read_status()
10325 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_read_status()
10330 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10361 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10368 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_read_status()
10383 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10401 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10411 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_848xx_read_status()
10439 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10441 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_8481_hw_reset()
10448 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10450 bnx2x_cl45_write(params->bp, phy, in bnx2x_8481_link_reset()
10457 struct bnx2x *bp = params->bp; in bnx2x_848x3_link_reset() local
10461 if (!(CHIP_IS_E1x(bp))) in bnx2x_848x3_link_reset()
10462 port = BP_PATH(bp); in bnx2x_848x3_link_reset()
10467 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3, in bnx2x_848x3_link_reset()
10471 bnx2x_cl45_read(bp, phy, in bnx2x_848x3_link_reset()
10475 bnx2x_cl45_write(bp, phy, in bnx2x_848x3_link_reset()
10484 struct bnx2x *bp = params->bp; in bnx2x_848xx_set_link_led() local
10488 if (!(CHIP_IS_E1x(bp))) in bnx2x_848xx_set_link_led()
10489 port = BP_PATH(bp); in bnx2x_848xx_set_link_led()
10502 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10507 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10512 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10517 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10523 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10538 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10543 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10548 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10553 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10559 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10568 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10575 bp, in bnx2x_848xx_set_link_led()
10580 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10594 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10601 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10607 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10612 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10617 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10622 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10627 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10636 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_848xx_set_link_led()
10643 bp, in bnx2x_848xx_set_link_led()
10648 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10664 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10673 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10680 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10685 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10690 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10695 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10709 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10715 bnx2x_cl45_read(bp, phy, in bnx2x_848xx_set_link_led()
10721 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10730 bnx2x_cl45_write(bp, phy, in bnx2x_848xx_set_link_led()
10748 if (CHIP_IS_E3(bp)) { in bnx2x_848xx_set_link_led()
10749 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, in bnx2x_848xx_set_link_led()
10761 struct bnx2x *bp = params->bp; in bnx2x_54618se_specific_func() local
10767 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10770 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_specific_func()
10775 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10779 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_specific_func()
10790 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_init() local
10803 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_config_init()
10810 bnx2x_set_cfg_pin(bp, cfg_pin, 1); in bnx2x_54618se_config_init()
10816 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10818 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_54618se_config_init()
10826 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10829 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10833 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10850 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10854 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10858 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10879 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10882 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_config_init()
10918 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10925 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10934 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS, in bnx2x_54618se_config_init()
10937 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); in bnx2x_54618se_config_init()
10939 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); in bnx2x_54618se_config_init()
10974 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, in bnx2x_54618se_config_init()
10979 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10986 bnx2x_cl22_write(bp, phy, in bnx2x_54618se_config_init()
10996 struct bnx2x *bp = params->bp; in bnx2x_5461x_set_link_led() local
10999 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11002 bnx2x_cl22_read(bp, phy, in bnx2x_5461x_set_link_led()
11022 bnx2x_cl22_write(bp, phy, in bnx2x_5461x_set_link_led()
11032 struct bnx2x *bp = params->bp; in bnx2x_54618se_link_reset() local
11039 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
11044 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_54618se_link_reset()
11051 bnx2x_set_cfg_pin(bp, cfg_pin, 0); in bnx2x_54618se_link_reset()
11058 struct bnx2x *bp = params->bp; in bnx2x_54618se_read_status() local
11064 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11070 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11107 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11113 bnx2x_cl22_read(bp, phy, in bnx2x_54618se_read_status()
11127 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11145 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11164 struct bnx2x *bp = params->bp; in bnx2x_54618se_config_loopback() local
11172 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11179 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11182 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11188 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11189 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11190 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11193 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11198 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
11207 struct bnx2x *bp = params->bp; in bnx2x_7101_config_loopback() local
11209 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_loopback()
11218 struct bnx2x *bp = params->bp; in bnx2x_7101_config_init() local
11222 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_config_init()
11225 bnx2x_ext_phy_hw_reset(bp, params->port); in bnx2x_7101_config_init()
11226 bnx2x_wait_reset_complete(bp, phy, params); in bnx2x_7101_config_init()
11228 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11231 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11236 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11239 bnx2x_cl45_write(bp, phy, in bnx2x_7101_config_init()
11243 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11246 bnx2x_cl45_read(bp, phy, in bnx2x_7101_config_init()
11248 bnx2x_save_spirom_version(bp, params->port, in bnx2x_7101_config_init()
11257 struct bnx2x *bp = params->bp; in bnx2x_7101_read_status() local
11260 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11262 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11266 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11268 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11275 bnx2x_cl45_read(bp, phy, in bnx2x_7101_read_status()
11282 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars); in bnx2x_7101_read_status()
11306 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy) in bnx2x_sfx7101_sp_sw_reset() argument
11310 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11317 bnx2x_cl45_write(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11322 bnx2x_cl45_read(bp, phy, in bnx2x_sfx7101_sp_sw_reset()
11334 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2, in bnx2x_7101_hw_reset()
11337 bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1, in bnx2x_7101_hw_reset()
11345 struct bnx2x *bp = params->bp; in bnx2x_7101_set_link_led() local
11358 bnx2x_cl45_write(bp, phy, in bnx2x_7101_set_link_led()
11863 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base, in bnx2x_populate_preemphasis() argument
11875 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11879 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11883 rx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11887 tx = REG_RD(bp, shmem_base + in bnx2x_populate_preemphasis()
11900 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_config() argument
11906 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
11911 ext_phy_config = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_config()
11922 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port, in bnx2x_populate_int_phy() argument
11927 u32 switch_cfg = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
11931 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) | in bnx2x_populate_int_phy()
11932 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_populate_int_phy()
11935 if (USES_WARPCORE(bp)) { in bnx2x_populate_int_phy()
11937 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
11940 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) in bnx2x_populate_int_phy()
11945 serdes_net_if = (REG_RD(bp, shmem_base + in bnx2x_populate_int_phy()
12020 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_populate_int_phy()
12027 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
12033 phy_addr = REG_RD(bp, in bnx2x_populate_int_phy()
12044 phy->mdio_ctrl = bnx2x_get_emac_base(bp, in bnx2x_populate_int_phy()
12047 if (CHIP_IS_E2(bp)) in bnx2x_populate_int_phy()
12055 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY); in bnx2x_populate_int_phy()
12059 static int bnx2x_populate_ext_phy(struct bnx2x *bp, in bnx2x_populate_ext_phy() argument
12068 ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base, in bnx2x_populate_ext_phy()
12132 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); in bnx2x_populate_ext_phy()
12138 config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region, in bnx2x_populate_ext_phy()
12149 u32 size = REG_RD(bp, shmem2_base); in bnx2x_populate_ext_phy()
12164 phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port); in bnx2x_populate_ext_phy()
12172 u32 raw_ver = REG_RD(bp, phy->ver_addr); in bnx2x_populate_ext_phy()
12186 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base, in bnx2x_populate_phy() argument
12192 return bnx2x_populate_int_phy(bp, shmem_base, port, phy); in bnx2x_populate_phy()
12193 status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_populate_phy()
12202 struct bnx2x *bp = params->bp; in bnx2x_phy_def_cfg() local
12206 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12209 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12214 link_config = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12217 phy->speed_cap_mask = REG_RD(bp, params->shmem_base + in bnx2x_phy_def_cfg()
12307 struct bnx2x *bp = params->bp; in bnx2x_phy_probe() local
12327 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base, in bnx2x_phy_probe()
12353 media_types = REG_RD(bp, sync_offset); in bnx2x_phy_probe()
12367 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12380 struct bnx2x *bp = params->bp; in bnx2x_init_bmac_loopback() local
12394 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_bmac_loopback()
12400 struct bnx2x *bp = params->bp; in bnx2x_init_emac_loopback() local
12413 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_emac_loopback()
12419 struct bnx2x *bp = params->bp; in bnx2x_init_xmac_loopback() local
12433 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12439 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12445 struct bnx2x *bp = params->bp; in bnx2x_init_umac_loopback() local
12454 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12460 struct bnx2x *bp = params->bp; in bnx2x_init_xgxs_loopback() local
12473 if (!USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12478 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12485 if (USES_WARPCORE(bp)) in bnx2x_init_xgxs_loopback()
12504 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12511 struct bnx2x *bp = params->bp; in bnx2x_set_rx_filter() local
12515 if (!CHIP_IS_E1x(bp)) in bnx2x_set_rx_filter()
12517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12519 if (!CHIP_IS_E1(bp)) { in bnx2x_set_rx_filter()
12520 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12524 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12532 struct bnx2x *bp = params->bp; in bnx2x_avoid_link_flap() local
12534 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_avoid_link_flap()
12554 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12561 if (CHIP_IS_E3(bp)) { in bnx2x_avoid_link_flap()
12563 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12567 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12591 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12595 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12607 struct bnx2x *bp = params->bp; in bnx2x_cannot_avoid_link_flap() local
12614 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12618 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12622 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12627 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12633 tmp_val = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12638 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12641 lfa_sts = REG_RD(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12657 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12665 struct bnx2x *bp = params->bp; in bnx2x_phy_init() local
12698 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_phy_init()
12734 if (!CHIP_IS_E3(bp)) { in bnx2x_phy_init()
12738 bnx2x_serdes_deassert(bp, params->port); in bnx2x_phy_init()
12754 struct bnx2x *bp = params->bp; in bnx2x_link_reset() local
12764 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, in bnx2x_link_reset()
12771 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
12774 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12775 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12776 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12779 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12780 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); in bnx2x_link_reset()
12786 if (!CHIP_IS_E3(bp)) in bnx2x_link_reset()
12787 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
12794 bnx2x_set_mdio_emac_per_phy(bp, params); in bnx2x_link_reset()
12815 bnx2x_rearm_latch_signal(bp, port, 0); in bnx2x_link_reset()
12816 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4, in bnx2x_link_reset()
12824 if (!CHIP_IS_E3(bp)) { in bnx2x_link_reset()
12826 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
12828 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12829 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12833 if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_link_reset()
12835 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
12845 struct bnx2x *bp = params->bp; in bnx2x_lfa_reset() local
12855 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
12861 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
12862 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_lfa_reset()
12864 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
12882 if (!CHIP_IS_E3(bp)) in bnx2x_lfa_reset()
12883 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1); in bnx2x_lfa_reset()
12885 if (CHIP_IS_E3(bp)) { in bnx2x_lfa_reset()
12890 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
12897 static int bnx2x_8073_common_init_phy(struct bnx2x *bp, in bnx2x_8073_common_init_phy() argument
12908 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8073_common_init_phy()
12909 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8073_common_init_phy()
12911 bnx2x_ext_phy_hw_reset(bp, port); in bnx2x_8073_common_init_phy()
12916 if (CHIP_IS_E1x(bp)) { in bnx2x_8073_common_init_phy()
12927 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8073_common_init_phy()
12934 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8073_common_init_phy()
12944 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
12949 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8073_common_init_phy()
12968 if (CHIP_IS_E1x(bp)) in bnx2x_8073_common_init_phy()
12975 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12980 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
12985 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13000 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13004 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13010 bnx2x_cl45_read(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13013 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8073_common_init_phy()
13018 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, in bnx2x_8073_common_init_phy()
13023 static int bnx2x_8726_common_init_phy(struct bnx2x *bp, in bnx2x_8726_common_init_phy() argument
13033 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_8726_common_init_phy()
13036 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
13038 bnx2x_ext_phy_hw_reset(bp, 0); in bnx2x_8726_common_init_phy()
13044 if (CHIP_IS_E1x(bp)) { in bnx2x_8726_common_init_phy()
13052 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8726_common_init_phy()
13060 bnx2x_cl45_write(bp, &phy, in bnx2x_8726_common_init_phy()
13065 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, in bnx2x_8726_common_init_phy()
13072 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base, in bnx2x_get_ext_phy_reset_gpio() argument
13076 u32 phy_gpio_reset = REG_RD(bp, shmem_base + in bnx2x_get_ext_phy_reset_gpio()
13118 static int bnx2x_8727_common_init_phy(struct bnx2x *bp, in bnx2x_8727_common_init_phy() argument
13128 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_8727_common_init_phy()
13129 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_8727_common_init_phy()
13137 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], in bnx2x_8727_common_init_phy()
13144 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, in bnx2x_8727_common_init_phy()
13147 bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, in bnx2x_8727_common_init_phy()
13157 if (CHIP_IS_E1x(bp)) { in bnx2x_8727_common_init_phy()
13168 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_8727_common_init_phy()
13175 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + in bnx2x_8727_common_init_phy()
13184 bnx2x_cl45_write(bp, &phy[port], in bnx2x_8727_common_init_phy()
13199 if (CHIP_IS_E1x(bp)) in bnx2x_8727_common_init_phy()
13205 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13209 bnx2x_cl45_write(bp, phy_blk[port], in bnx2x_8727_common_init_phy()
13217 static int bnx2x_84833_common_init_phy(struct bnx2x *bp, in bnx2x_84833_common_init_phy() argument
13224 reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id); in bnx2x_84833_common_init_phy()
13225 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); in bnx2x_84833_common_init_phy()
13227 bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); in bnx2x_84833_common_init_phy()
13233 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_ext_phy_common_init() argument
13241 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13248 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13257 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13266 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, in bnx2x_ext_phy_common_init()
13281 netdev_err(bp->dev, "Warning: PHY was not initialized," in bnx2x_ext_phy_common_init()
13287 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[], in bnx2x_common_init_phy() argument
13295 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0); in bnx2x_common_init_phy()
13296 bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1); in bnx2x_common_init_phy()
13298 if (CHIP_IS_E3(bp)) { in bnx2x_common_init_phy()
13300 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG); in bnx2x_common_init_phy()
13301 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13304 phy_ver = REG_RD(bp, shmem_base_path[0] + in bnx2x_common_init_phy()
13316 ext_phy_config = bnx2x_get_ext_phy_config(bp, in bnx2x_common_init_phy()
13320 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path, in bnx2x_common_init_phy()
13331 struct bnx2x *bp = params->bp; in bnx2x_check_over_curr() local
13336 cfg_pin = (REG_RD(bp, params->shmem_base + in bnx2x_check_over_curr()
13343 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) in bnx2x_check_over_curr()
13348 netdev_err(bp->dev, "Error: Power fault on Port %d has" in bnx2x_check_over_curr()
13368 struct bnx2x *bp = params->bp; in bnx2x_analyze_link_error() local
13404 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13417 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13429 bnx2x_notify_link_changed(bp); in bnx2x_analyze_link_error()
13447 struct bnx2x *bp = params->bp; in bnx2x_check_half_open_conn() local
13452 (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) in bnx2x_check_half_open_conn()
13455 if (CHIP_IS_E3(bp) && in bnx2x_check_half_open_conn()
13456 (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13466 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13467 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13470 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS)) in bnx2x_check_half_open_conn()
13476 } else if (REG_RD(bp, MISC_REG_RESET_REG_2) & in bnx2x_check_half_open_conn()
13484 if (CHIP_IS_E2(bp)) in bnx2x_check_half_open_conn()
13489 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2); in bnx2x_check_half_open_conn()
13502 struct bnx2x *bp = params->bp; in bnx2x_sfp_tx_fault_detection() local
13507 cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region, in bnx2x_sfp_tx_fault_detection()
13512 if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) { in bnx2x_sfp_tx_fault_detection()
13545 struct bnx2x *bp = params->bp; in bnx2x_kr2_recovery() local
13555 struct bnx2x *bp = params->bp; in bnx2x_check_kr2_wa() local
13579 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, in bnx2x_check_kr2_wa()
13581 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13583 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, in bnx2x_check_kr2_wa()
13627 struct bnx2x *bp = params->bp; in bnx2x_period_func() local
13638 if (CHIP_IS_E3(bp)) { in bnx2x_period_func()
13648 if ((REG_RD(bp, params->shmem_base + in bnx2x_period_func()
13667 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, in bnx2x_fan_failure_det_req() argument
13676 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base, in bnx2x_fan_failure_det_req()
13691 struct bnx2x *bp = params->bp; in bnx2x_hw_reset_phy() local
13693 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, in bnx2x_hw_reset_phy()
13710 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars, in bnx2x_init_mod_abs_int() argument
13717 if (CHIP_IS_E3(bp)) { in bnx2x_init_mod_abs_int()
13718 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id, in bnx2x_init_mod_abs_int()
13728 if (bnx2x_populate_phy(bp, phy_index, shmem_base, in bnx2x_init_mod_abs_int()
13746 bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); in bnx2x_init_mod_abs_int()
13748 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP); in bnx2x_init_mod_abs_int()
13749 swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE); in bnx2x_init_mod_abs_int()
13758 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
13769 aeu_mask = REG_RD(bp, offset); in bnx2x_init_mod_abs_int()
13771 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
13774 val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN); in bnx2x_init_mod_abs_int()
13776 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()