Lines Matching refs:bp
288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
296 static void __storm_memset_dma_mapping(struct bnx2x *bp, in __storm_memset_dma_mapping() argument
299 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
300 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
303 static void storm_memset_spq_addr(struct bnx2x *bp, in storm_memset_spq_addr() argument
309 __storm_memset_dma_mapping(bp, addr, mapping); in storm_memset_spq_addr()
312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid, in storm_memset_vf_to_pf() argument
315 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
317 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
319 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
321 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid), in storm_memset_vf_to_pf()
325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid, in storm_memset_func_en() argument
328 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
330 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
332 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
334 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid), in storm_memset_func_en()
338 static void storm_memset_eq_data(struct bnx2x *bp, in storm_memset_eq_data() argument
346 __storm_memset_struct(bp, addr, size, (u32 *)eq_data); in storm_memset_eq_data()
349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod, in storm_memset_eq_prod() argument
353 REG_WR16(bp, addr, eq_prod); in storm_memset_eq_prod()
359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val) in bnx2x_reg_wr_ind() argument
361 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_wr_ind()
362 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val); in bnx2x_reg_wr_ind()
363 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_wr_ind()
367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr) in bnx2x_reg_rd_ind() argument
371 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr); in bnx2x_reg_rd_ind()
372 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val); in bnx2x_reg_rd_ind()
373 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_reg_rd_ind()
385 static void bnx2x_dp_dmae(struct bnx2x *bp, in bnx2x_dp_dmae() argument
452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx) in bnx2x_post_dmae() argument
459 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
461 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, in bnx2x_dmae_opcode() argument
485 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); in bnx2x_dmae_opcode()
486 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) | in bnx2x_dmae_opcode()
487 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); in bnx2x_dmae_opcode()
500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, in bnx2x_prep_dmae_with_comp() argument
507 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type, in bnx2x_prep_dmae_with_comp()
511 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
512 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp)); in bnx2x_prep_dmae_with_comp()
517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, in bnx2x_issue_dmae_with_comp() argument
520 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000; in bnx2x_issue_dmae_with_comp()
523 bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE); in bnx2x_issue_dmae_with_comp()
530 spin_lock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
536 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp)); in bnx2x_issue_dmae_with_comp()
543 (bp->recovery_state != BNX2X_RECOVERY_DONE && in bnx2x_issue_dmae_with_comp()
544 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_issue_dmae_with_comp()
559 spin_unlock_bh(&bp->dmae_lock); in bnx2x_issue_dmae_with_comp()
564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, in bnx2x_write_dmae() argument
570 if (!bp->dmae_ready) { in bnx2x_write_dmae()
571 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_write_dmae()
573 if (CHIP_IS_E1(bp)) in bnx2x_write_dmae()
574 bnx2x_init_ind_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
576 bnx2x_init_str_wr(bp, dst_addr, data, len32); in bnx2x_write_dmae()
581 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); in bnx2x_write_dmae()
591 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_write_dmae()
600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32) in bnx2x_read_dmae() argument
605 if (!bp->dmae_ready) { in bnx2x_read_dmae()
606 u32 *data = bnx2x_sp(bp, wb_data[0]); in bnx2x_read_dmae()
609 if (CHIP_IS_E1(bp)) in bnx2x_read_dmae()
611 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4); in bnx2x_read_dmae()
614 data[i] = REG_RD(bp, src_addr + i*4); in bnx2x_read_dmae()
620 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); in bnx2x_read_dmae()
625 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
626 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data)); in bnx2x_read_dmae()
630 rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp)); in bnx2x_read_dmae()
639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr, in bnx2x_write_dmae_phys_len() argument
642 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp); in bnx2x_write_dmae_phys_len()
646 bnx2x_write_dmae(bp, phys_addr + offset, in bnx2x_write_dmae_phys_len()
652 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len); in bnx2x_write_dmae_phys_len()
666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp, in bnx2x_get_assert_list_entry() argument
686 static int bnx2x_mc_assert(struct bnx2x *bp) in bnx2x_mc_assert() argument
712 last_idx = REG_RD8(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
722 regs[j] = REG_RD(bp, bar_storm_intmem[storm] + in bnx2x_mc_assert()
723 bnx2x_get_assert_list_entry(bp, in bnx2x_mc_assert()
741 CHIP_IS_E1(bp) ? "everest1" : in bnx2x_mc_assert()
742 CHIP_IS_E1H(bp) ? "everest1h" : in bnx2x_mc_assert()
743 CHIP_IS_E2(bp) ? "everest2" : "everest3", in bnx2x_mc_assert()
752 #define SCRATCH_BUFFER_SIZE(bp) \ argument
753 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl) in bnx2x_fw_dump_lvl() argument
762 if (BP_NOMCP(bp)) { in bnx2x_fw_dump_lvl()
766 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n", in bnx2x_fw_dump_lvl()
767 (bp->common.bc_ver & 0xff0000) >> 16, in bnx2x_fw_dump_lvl()
768 (bp->common.bc_ver & 0xff00) >> 8, in bnx2x_fw_dump_lvl()
769 (bp->common.bc_ver & 0xff)); in bnx2x_fw_dump_lvl()
771 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER); in bnx2x_fw_dump_lvl()
772 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER)) in bnx2x_fw_dump_lvl()
775 if (BP_PATH(bp) == 0) in bnx2x_fw_dump_lvl()
776 trace_shmem_base = bp->common.shmem_base; in bnx2x_fw_dump_lvl()
778 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x_fw_dump_lvl()
781 if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE || in bnx2x_fw_dump_lvl()
782 trace_shmem_base >= MCPR_SCRATCH_BASE(bp) + in bnx2x_fw_dump_lvl()
783 SCRATCH_BUFFER_SIZE(bp)) { in bnx2x_fw_dump_lvl()
792 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
800 mark = REG_RD(bp, addr); in bnx2x_fw_dump_lvl()
801 mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000; in bnx2x_fw_dump_lvl()
813 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
821 data[word] = htonl(REG_RD(bp, offset + 4*word)); in bnx2x_fw_dump_lvl()
828 static void bnx2x_fw_dump(struct bnx2x *bp) in bnx2x_fw_dump() argument
830 bnx2x_fw_dump_lvl(bp, KERN_ERR); in bnx2x_fw_dump()
833 static void bnx2x_hc_int_disable(struct bnx2x *bp) in bnx2x_hc_int_disable() argument
835 int port = BP_PORT(bp); in bnx2x_hc_int_disable()
837 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_disable()
843 if (CHIP_IS_E1(bp)) { in bnx2x_hc_int_disable()
848 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
866 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
867 if (REG_RD(bp, addr) != val) in bnx2x_hc_int_disable()
871 static void bnx2x_igu_int_disable(struct bnx2x *bp) in bnx2x_igu_int_disable() argument
873 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_disable()
884 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
885 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val) in bnx2x_igu_int_disable()
889 static void bnx2x_int_disable(struct bnx2x *bp) in bnx2x_int_disable() argument
891 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_disable()
892 bnx2x_hc_int_disable(bp); in bnx2x_int_disable()
894 bnx2x_igu_int_disable(bp); in bnx2x_int_disable()
897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int) in bnx2x_panic_dump() argument
902 int func = BP_FUNC(bp); in bnx2x_panic_dump()
907 if (IS_PF(bp) && disable_int) in bnx2x_panic_dump()
908 bnx2x_int_disable(bp); in bnx2x_panic_dump()
910 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_panic_dump()
911 bp->eth_stats.unrecoverable_error++; in bnx2x_panic_dump()
918 if (IS_PF(bp)) { in bnx2x_panic_dump()
919 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_panic_dump()
923 bp->def_idx, bp->def_att_idx, bp->attn_state, in bnx2x_panic_dump()
924 bp->spq_prod_idx, bp->stats_counter); in bnx2x_panic_dump()
941 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset + in bnx2x_panic_dump()
954 for_each_eth_queue(bp, i) { in bnx2x_panic_dump()
955 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
960 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
964 CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
971 if (!bp->fp) in bnx2x_panic_dump()
1004 loop = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1025 if (IS_VF(bp)) in bnx2x_panic_dump()
1029 data_size = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1033 sb_data_p = CHIP_IS_E1x(bp) ? in bnx2x_panic_dump()
1038 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM + in bnx2x_panic_dump()
1042 if (!CHIP_IS_E1x(bp)) { in bnx2x_panic_dump()
1079 if (IS_PF(bp)) { in bnx2x_panic_dump()
1081 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod); in bnx2x_panic_dump()
1083 u32 *data = (u32 *)&bp->eq_ring[i].message.data; in bnx2x_panic_dump()
1086 i, bp->eq_ring[i].message.opcode, in bnx2x_panic_dump()
1087 bp->eq_ring[i].message.error); in bnx2x_panic_dump()
1095 for_each_valid_rx_queue(bp, i) { in bnx2x_panic_dump()
1096 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1098 if (!bp->fp) in bnx2x_panic_dump()
1135 for_each_valid_tx_queue(bp, i) { in bnx2x_panic_dump()
1136 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_panic_dump()
1138 if (!bp->fp) in bnx2x_panic_dump()
1173 if (IS_PF(bp)) { in bnx2x_panic_dump()
1174 bnx2x_fw_dump(bp); in bnx2x_panic_dump()
1175 bnx2x_mc_assert(bp); in bnx2x_panic_dump()
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_buf_flushed() argument
1210 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1211 crd = crd_start = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1212 init_crd = REG_RD(bp, regs->init_crd); in bnx2x_pbf_pN_buf_flushed()
1222 crd = REG_RD(bp, regs->crd); in bnx2x_pbf_pN_buf_flushed()
1223 crd_freed = REG_RD(bp, regs->crd_freed); in bnx2x_pbf_pN_buf_flushed()
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp, in bnx2x_pbf_pN_cmd_flushed() argument
1245 occup = to_free = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1246 freed = freed_start = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1254 occup = REG_RD(bp, regs->lines_occup); in bnx2x_pbf_pN_cmd_flushed()
1255 freed = REG_RD(bp, regs->lines_freed); in bnx2x_pbf_pN_cmd_flushed()
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_reg_poll() argument
1276 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--) in bnx2x_flr_clnup_reg_poll()
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, in bnx2x_flr_clnup_poll_hw_counter() argument
1285 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt); in bnx2x_flr_clnup_poll_hw_counter()
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp) in bnx2x_flr_clnup_poll_count() argument
1297 if (CHIP_REV_IS_EMUL(bp)) in bnx2x_flr_clnup_poll_count()
1300 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_flr_clnup_poll_count()
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count) in bnx2x_tx_hw_flushed() argument
1309 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1312 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1315 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1318 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1321 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1324 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1330 {0, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1333 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1336 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1339 {1, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1342 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1345 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1348 {4, (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1351 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1354 (CHIP_IS_E3B0(bp)) ? in bnx2x_tx_hw_flushed()
1363 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1367 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count); in bnx2x_tx_hw_flushed()
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt) in bnx2x_send_final_clnup() argument
1386 if (REG_RD(bp, comp_addr)) { in bnx2x_send_final_clnup()
1397 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1399 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) { in bnx2x_send_final_clnup()
1402 (REG_RD(bp, comp_addr))); in bnx2x_send_final_clnup()
1407 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt) in bnx2x_poll_hw_usage_counters() argument
1425 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1432 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1439 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1440 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp), in bnx2x_poll_hw_usage_counters()
1446 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1447 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1451 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1452 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp), in bnx2x_poll_hw_usage_counters()
1458 if (bnx2x_flr_clnup_poll_hw_counter(bp, in bnx2x_poll_hw_usage_counters()
1459 dmae_reg_go_c[INIT_DMAE_C(bp)], in bnx2x_poll_hw_usage_counters()
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp) in bnx2x_hw_enable_status() argument
1471 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF); in bnx2x_hw_enable_status()
1474 val = REG_RD(bp, PBF_REG_DISABLE_PF); in bnx2x_hw_enable_status()
1477 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN); in bnx2x_hw_enable_status()
1480 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN); in bnx2x_hw_enable_status()
1483 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK); in bnx2x_hw_enable_status()
1486 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); in bnx2x_hw_enable_status()
1489 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); in bnx2x_hw_enable_status()
1492 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); in bnx2x_hw_enable_status()
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp) in bnx2x_pf_flr_clnup() argument
1499 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp); in bnx2x_pf_flr_clnup()
1501 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp)); in bnx2x_pf_flr_clnup()
1504 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
1508 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt)) in bnx2x_pf_flr_clnup()
1514 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt)) in bnx2x_pf_flr_clnup()
1520 bnx2x_tx_hw_flushed(bp, poll_cnt); in bnx2x_pf_flr_clnup()
1526 if (bnx2x_is_pcie_pending(bp->pdev)) in bnx2x_pf_flr_clnup()
1530 bnx2x_hw_enable_status(bp); in bnx2x_pf_flr_clnup()
1536 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_pf_flr_clnup()
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp) in bnx2x_hc_int_enable() argument
1543 int port = BP_PORT(bp); in bnx2x_hc_int_enable()
1545 u32 val = REG_RD(bp, addr); in bnx2x_hc_int_enable()
1546 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1547 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_hc_int_enable()
1548 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_hc_int_enable()
1568 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1572 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1578 if (CHIP_IS_E1(bp)) in bnx2x_hc_int_enable()
1579 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1585 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1592 if (!CHIP_IS_E1(bp)) { in bnx2x_hc_int_enable()
1594 if (IS_MF(bp)) { in bnx2x_hc_int_enable()
1595 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_hc_int_enable()
1596 if (bp->port.pmf) in bnx2x_hc_int_enable()
1602 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1603 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp) in bnx2x_igu_int_enable() argument
1613 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1614 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false; in bnx2x_igu_int_enable()
1615 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false; in bnx2x_igu_int_enable()
1617 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_igu_int_enable()
1641 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1642 bnx2x_ack_int(bp); in bnx2x_igu_int_enable()
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1653 pci_intx(bp->pdev, true); in bnx2x_igu_int_enable()
1658 if (IS_MF(bp)) { in bnx2x_igu_int_enable()
1659 val = (0xee0f | (1 << (BP_VN(bp) + 4))); in bnx2x_igu_int_enable()
1660 if (bp->port.pmf) in bnx2x_igu_int_enable()
1666 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1667 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1673 void bnx2x_int_enable(struct bnx2x *bp) in bnx2x_int_enable() argument
1675 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_int_enable()
1676 bnx2x_hc_int_enable(bp); in bnx2x_int_enable()
1678 bnx2x_igu_int_enable(bp); in bnx2x_int_enable()
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw) in bnx2x_int_disable_sync() argument
1683 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_int_disable_sync()
1688 bnx2x_int_disable(bp); in bnx2x_int_disable_sync()
1692 synchronize_irq(bp->msix_table[0].vector); in bnx2x_int_disable_sync()
1694 if (CNIC_SUPPORT(bp)) in bnx2x_int_disable_sync()
1696 for_each_eth_queue(bp, i) in bnx2x_int_disable_sync()
1697 synchronize_irq(bp->msix_table[offset++].vector); in bnx2x_int_disable_sync()
1699 synchronize_irq(bp->pdev->irq); in bnx2x_int_disable_sync()
1702 cancel_delayed_work(&bp->sp_task); in bnx2x_int_disable_sync()
1703 cancel_delayed_work(&bp->period_task); in bnx2x_int_disable_sync()
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_trylock_hw_lock() argument
1718 int func = BP_FUNC(bp); in bnx2x_trylock_hw_lock()
1739 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
1740 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_trylock_hw_lock()
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp) in bnx2x_get_leader_lock_resource() argument
1759 if (BP_PATH(bp)) in bnx2x_get_leader_lock_resource()
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp) in bnx2x_trylock_leader_lock() argument
1774 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_trylock_leader_lock()
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp) in bnx2x_schedule_sp_task() argument
1786 atomic_set(&bp->interrupt_occurred, 1); in bnx2x_schedule_sp_task()
1795 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0); in bnx2x_schedule_sp_task()
1800 struct bnx2x *bp = fp->bp; in bnx2x_sp_event() local
1804 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_sp_event()
1808 fp->index, cid, command, bp->state, in bnx2x_sp_event()
1816 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj); in bnx2x_sp_event()
1861 q_obj->complete_cmd(bp, q_obj, drv_cmd)) in bnx2x_sp_event()
1876 atomic_inc(&bp->cq_spq_left); in bnx2x_sp_event()
1880 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left)); in bnx2x_sp_event()
1883 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) { in bnx2x_sp_event()
1894 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state); in bnx2x_sp_event()
1896 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_sp_event()
1900 bnx2x_schedule_sp_task(bp); in bnx2x_sp_event()
1908 struct bnx2x *bp = netdev_priv(dev_instance); in bnx2x_interrupt() local
1909 u16 status = bnx2x_ack_int(bp); in bnx2x_interrupt()
1922 if (unlikely(bp->panic)) in bnx2x_interrupt()
1926 for_each_eth_queue(bp, i) { in bnx2x_interrupt()
1927 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_interrupt()
1929 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp)); in bnx2x_interrupt()
1935 napi_schedule_irqoff(&bnx2x_fp(bp, fp->index, napi)); in bnx2x_interrupt()
1940 if (CNIC_SUPPORT(bp)) { in bnx2x_interrupt()
1946 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_interrupt()
1947 if (c_ops && (bp->cnic_eth_dev.drv_state & in bnx2x_interrupt()
1949 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_interrupt()
1961 bnx2x_schedule_sp_task(bp); in bnx2x_interrupt()
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_acquire_hw_lock() argument
1985 int func = BP_FUNC(bp); in bnx2x_acquire_hw_lock()
2004 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2014 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
2015 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_acquire_hw_lock()
2025 int bnx2x_release_leader_lock(struct bnx2x *bp) in bnx2x_release_leader_lock() argument
2027 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp)); in bnx2x_release_leader_lock()
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource) in bnx2x_release_hw_lock() argument
2034 int func = BP_FUNC(bp); in bnx2x_release_hw_lock()
2052 lock_status = REG_RD(bp, hw_lock_control_reg); in bnx2x_release_hw_lock()
2059 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port) in bnx2x_get_gpio() argument
2066 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_get_gpio()
2067 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_get_gpio()
2080 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_get_gpio()
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio() argument
2094 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio()
2095 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio()
2106 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2108 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); in bnx2x_set_gpio()
2141 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
2142 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio()
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode) in bnx2x_set_mult_gpio() argument
2154 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2156 gpio_reg = REG_RD(bp, MISC_REG_GPIO); in bnx2x_set_mult_gpio()
2187 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_mult_gpio()
2189 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_mult_gpio()
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port) in bnx2x_set_gpio_int() argument
2197 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) && in bnx2x_set_gpio_int()
2198 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port; in bnx2x_set_gpio_int()
2209 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2211 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT); in bnx2x_set_gpio_int()
2236 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
2237 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO); in bnx2x_set_gpio_int()
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode) in bnx2x_set_spio() argument
2252 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2254 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT); in bnx2x_set_spio()
2281 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2282 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO); in bnx2x_set_spio()
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp) in bnx2x_calc_fc_adv() argument
2289 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_calc_fc_adv()
2290 switch (bp->link_vars.ieee_fc & in bnx2x_calc_fc_adv()
2293 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2298 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2303 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; in bnx2x_calc_fc_adv()
2307 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | in bnx2x_calc_fc_adv()
2313 static void bnx2x_set_requested_fc(struct bnx2x *bp) in bnx2x_set_requested_fc() argument
2319 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000)) in bnx2x_set_requested_fc()
2320 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX; in bnx2x_set_requested_fc()
2322 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH; in bnx2x_set_requested_fc()
2325 static void bnx2x_init_dropless_fc(struct bnx2x *bp) in bnx2x_init_dropless_fc() argument
2329 if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) { in bnx2x_init_dropless_fc()
2330 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) in bnx2x_init_dropless_fc()
2333 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_dropless_fc()
2334 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)), in bnx2x_init_dropless_fc()
2342 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode) in bnx2x_initial_phy_init() argument
2344 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp); in bnx2x_initial_phy_init()
2345 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx]; in bnx2x_initial_phy_init()
2347 if (!BP_NOMCP(bp)) { in bnx2x_initial_phy_init()
2348 bnx2x_set_requested_fc(bp); in bnx2x_initial_phy_init()
2349 bnx2x_acquire_phy_lock(bp); in bnx2x_initial_phy_init()
2352 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2367 struct link_params *lp = &bp->link_params; in bnx2x_initial_phy_init()
2371 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_initial_phy_init()
2373 bnx2x_release_phy_lock(bp); in bnx2x_initial_phy_init()
2375 bnx2x_init_dropless_fc(bp); in bnx2x_initial_phy_init()
2377 bnx2x_calc_fc_adv(bp); in bnx2x_initial_phy_init()
2379 if (bp->link_vars.link_up) { in bnx2x_initial_phy_init()
2380 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_initial_phy_init()
2381 bnx2x_link_report(bp); in bnx2x_initial_phy_init()
2383 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_initial_phy_init()
2384 bp->link_params.req_line_speed[cfx_idx] = req_line_speed; in bnx2x_initial_phy_init()
2391 void bnx2x_link_set(struct bnx2x *bp) in bnx2x_link_set() argument
2393 if (!BP_NOMCP(bp)) { in bnx2x_link_set()
2394 bnx2x_acquire_phy_lock(bp); in bnx2x_link_set()
2395 bnx2x_phy_init(&bp->link_params, &bp->link_vars); in bnx2x_link_set()
2396 bnx2x_release_phy_lock(bp); in bnx2x_link_set()
2398 bnx2x_init_dropless_fc(bp); in bnx2x_link_set()
2400 bnx2x_calc_fc_adv(bp); in bnx2x_link_set()
2405 static void bnx2x__link_reset(struct bnx2x *bp) in bnx2x__link_reset() argument
2407 if (!BP_NOMCP(bp)) { in bnx2x__link_reset()
2408 bnx2x_acquire_phy_lock(bp); in bnx2x__link_reset()
2409 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars); in bnx2x__link_reset()
2410 bnx2x_release_phy_lock(bp); in bnx2x__link_reset()
2415 void bnx2x_force_link_reset(struct bnx2x *bp) in bnx2x_force_link_reset() argument
2417 bnx2x_acquire_phy_lock(bp); in bnx2x_force_link_reset()
2418 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1); in bnx2x_force_link_reset()
2419 bnx2x_release_phy_lock(bp); in bnx2x_force_link_reset()
2422 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes) in bnx2x_link_test() argument
2426 if (!BP_NOMCP(bp)) { in bnx2x_link_test()
2427 bnx2x_acquire_phy_lock(bp); in bnx2x_link_test()
2428 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars, in bnx2x_link_test()
2430 bnx2x_release_phy_lock(bp); in bnx2x_link_test()
2446 static void bnx2x_calc_vn_min(struct bnx2x *bp, in bnx2x_calc_vn_min() argument
2452 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_calc_vn_min()
2453 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_min()
2470 if (BNX2X_IS_ETS_ENABLED(bp)) { in bnx2x_calc_vn_min()
2484 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn, in bnx2x_calc_vn_max() argument
2488 u32 vn_cfg = bp->mf_config[vn]; in bnx2x_calc_vn_max()
2493 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg); in bnx2x_calc_vn_max()
2495 if (IS_MF_SI(bp)) { in bnx2x_calc_vn_max()
2497 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100; in bnx2x_calc_vn_max()
2508 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp) in bnx2x_get_cmng_fns_mode() argument
2510 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_get_cmng_fns_mode()
2512 if (IS_MF(bp)) in bnx2x_get_cmng_fns_mode()
2518 void bnx2x_read_mf_cfg(struct bnx2x *bp) in bnx2x_read_mf_cfg() argument
2520 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1); in bnx2x_read_mf_cfg()
2522 if (BP_NOMCP(bp)) in bnx2x_read_mf_cfg()
2536 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in bnx2x_read_mf_cfg()
2537 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); in bnx2x_read_mf_cfg()
2542 bp->mf_config[vn] = in bnx2x_read_mf_cfg()
2543 MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_read_mf_cfg()
2545 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_read_mf_cfg()
2547 bp->flags |= MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2550 bp->flags &= ~MF_FUNC_DIS; in bnx2x_read_mf_cfg()
2554 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type) in bnx2x_cmng_fns_init() argument
2559 input.port_rate = bp->link_vars.line_speed; in bnx2x_cmng_fns_init()
2566 bnx2x_read_mf_cfg(bp); in bnx2x_cmng_fns_init()
2569 bnx2x_calc_vn_min(bp, &input); in bnx2x_cmng_fns_init()
2572 if (bp->port.pmf) in bnx2x_cmng_fns_init()
2573 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) in bnx2x_cmng_fns_init()
2574 bnx2x_calc_vn_max(bp, vn, &input); in bnx2x_cmng_fns_init()
2580 bnx2x_init_cmng(&input, &bp->cmng); in bnx2x_cmng_fns_init()
2589 static void storm_memset_cmng(struct bnx2x *bp, in storm_memset_cmng() argument
2599 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port); in storm_memset_cmng()
2601 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { in storm_memset_cmng()
2602 int func = func_by_vn(bp, vn); in storm_memset_cmng()
2607 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2613 __storm_memset_struct(bp, addr, size, in storm_memset_cmng()
2619 void bnx2x_set_local_cmng(struct bnx2x *bp) in bnx2x_set_local_cmng() argument
2621 int cmng_fns = bnx2x_get_cmng_fns_mode(bp); in bnx2x_set_local_cmng()
2624 bnx2x_cmng_fns_init(bp, false, cmng_fns); in bnx2x_set_local_cmng()
2625 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_set_local_cmng()
2634 static void bnx2x_link_attn(struct bnx2x *bp) in bnx2x_link_attn() argument
2637 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x_link_attn()
2639 bnx2x_link_update(&bp->link_params, &bp->link_vars); in bnx2x_link_attn()
2641 bnx2x_init_dropless_fc(bp); in bnx2x_link_attn()
2643 if (bp->link_vars.link_up) { in bnx2x_link_attn()
2645 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) { in bnx2x_link_attn()
2648 pstats = bnx2x_sp(bp, port_stats); in bnx2x_link_attn()
2653 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_link_attn()
2654 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x_link_attn()
2657 if (bp->link_vars.link_up && bp->link_vars.line_speed) in bnx2x_link_attn()
2658 bnx2x_set_local_cmng(bp); in bnx2x_link_attn()
2660 __bnx2x_link_report(bp); in bnx2x_link_attn()
2662 if (IS_MF(bp)) in bnx2x_link_attn()
2663 bnx2x_link_sync_notify(bp); in bnx2x_link_attn()
2666 void bnx2x__link_status_update(struct bnx2x *bp) in bnx2x__link_status_update() argument
2668 if (bp->state != BNX2X_STATE_OPEN) in bnx2x__link_status_update()
2672 if (IS_PF(bp)) { in bnx2x__link_status_update()
2673 bnx2x_dcbx_pmf_update(bp); in bnx2x__link_status_update()
2674 bnx2x_link_status_update(&bp->link_params, &bp->link_vars); in bnx2x__link_status_update()
2675 if (bp->link_vars.link_up) in bnx2x__link_status_update()
2676 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2678 bnx2x_stats_handle(bp, STATS_EVENT_STOP); in bnx2x__link_status_update()
2680 bnx2x_link_report(bp); in bnx2x__link_status_update()
2683 bp->port.supported[0] |= (SUPPORTED_10baseT_Half | in bnx2x__link_status_update()
2695 bp->port.advertising[0] = bp->port.supported[0]; in bnx2x__link_status_update()
2697 bp->link_params.bp = bp; in bnx2x__link_status_update()
2698 bp->link_params.port = BP_PORT(bp); in bnx2x__link_status_update()
2699 bp->link_params.req_duplex[0] = DUPLEX_FULL; in bnx2x__link_status_update()
2700 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2701 bp->link_params.req_line_speed[0] = SPEED_10000; in bnx2x__link_status_update()
2702 bp->link_params.speed_cap_mask[0] = 0x7f0000; in bnx2x__link_status_update()
2703 bp->link_params.switch_cfg = SWITCH_CFG_10G; in bnx2x__link_status_update()
2704 bp->link_vars.mac_type = MAC_TYPE_BMAC; in bnx2x__link_status_update()
2705 bp->link_vars.line_speed = SPEED_10000; in bnx2x__link_status_update()
2706 bp->link_vars.link_status = in bnx2x__link_status_update()
2709 bp->link_vars.link_up = 1; in bnx2x__link_status_update()
2710 bp->link_vars.duplex = DUPLEX_FULL; in bnx2x__link_status_update()
2711 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE; in bnx2x__link_status_update()
2712 __bnx2x_link_report(bp); in bnx2x__link_status_update()
2714 bnx2x_sample_bulletin(bp); in bnx2x__link_status_update()
2721 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP); in bnx2x__link_status_update()
2725 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid, in bnx2x_afex_func_update() argument
2732 func_params.f_obj = &bp->func_obj; in bnx2x_afex_func_update()
2744 if (bnx2x_func_state_change(bp, &func_params) < 0) in bnx2x_afex_func_update()
2745 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_afex_func_update()
2750 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type, in bnx2x_afex_handle_vif_list_cmd() argument
2764 func_params.f_obj = &bp->func_obj; in bnx2x_afex_handle_vif_list_cmd()
2781 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_afex_handle_vif_list_cmd()
2783 bnx2x_fw_command(bp, drv_msg_code, 0); in bnx2x_afex_handle_vif_list_cmd()
2788 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd) in bnx2x_handle_afex_cmd() argument
2791 u32 func = BP_ABS_FUNC(bp); in bnx2x_handle_afex_cmd()
2801 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2804 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0); in bnx2x_handle_afex_cmd()
2808 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2809 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2813 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid, in bnx2x_handle_afex_cmd()
2818 addr_to_write = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2819 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2820 stats_type = SHMEM2_RD(bp, in bnx2x_handle_afex_cmd()
2821 afex_param1_to_driver[BP_FW_MB_IDX(bp)]); in bnx2x_handle_afex_cmd()
2827 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type); in bnx2x_handle_afex_cmd()
2831 REG_WR(bp, addr_to_write + i*sizeof(u32), in bnx2x_handle_afex_cmd()
2835 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0); in bnx2x_handle_afex_cmd()
2839 mf_config = MF_CFG_RD(bp, func_mf_config[func].config); in bnx2x_handle_afex_cmd()
2840 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2852 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp)); in bnx2x_handle_afex_cmd()
2854 bp->mf_config[BP_VN(bp)] = mf_config; in bnx2x_handle_afex_cmd()
2856 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input); in bnx2x_handle_afex_cmd()
2858 cmng_input.vnic_max_rate[BP_VN(bp)]; in bnx2x_handle_afex_cmd()
2863 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn); in bnx2x_handle_afex_cmd()
2867 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2871 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_afex_cmd()
2879 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2884 (MF_CFG_RD(bp, in bnx2x_handle_afex_cmd()
2890 if (bnx2x_afex_func_update(bp, vif_id, vlan_val, in bnx2x_handle_afex_cmd()
2894 bp->afex_def_vlan_tag = vlan_val; in bnx2x_handle_afex_cmd()
2895 bp->afex_vlan_mode = vlan_mode; in bnx2x_handle_afex_cmd()
2898 bnx2x_link_report(bp); in bnx2x_handle_afex_cmd()
2901 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0); in bnx2x_handle_afex_cmd()
2904 bp->afex_def_vlan_tag = -1; in bnx2x_handle_afex_cmd()
2909 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp) in bnx2x_handle_update_svid_cmd() argument
2916 func_params.f_obj = &bp->func_obj; in bnx2x_handle_update_svid_cmd()
2919 if (IS_MF_UFP(bp)) { in bnx2x_handle_update_svid_cmd()
2920 int func = BP_ABS_FUNC(bp); in bnx2x_handle_update_svid_cmd()
2924 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_handle_update_svid_cmd()
2927 bp->mf_ov = val; in bnx2x_handle_update_svid_cmd()
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, in bnx2x_handle_update_svid_cmd()
2935 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2940 switch_update_params->vlan = bp->mf_ov; in bnx2x_handle_update_svid_cmd()
2942 if (bnx2x_func_state_change(bp, &func_params) < 0) { in bnx2x_handle_update_svid_cmd()
2944 bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2948 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov); in bnx2x_handle_update_svid_cmd()
2950 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0); in bnx2x_handle_update_svid_cmd()
2957 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0); in bnx2x_handle_update_svid_cmd()
2960 static void bnx2x_pmf_update(struct bnx2x *bp) in bnx2x_pmf_update() argument
2962 int port = BP_PORT(bp); in bnx2x_pmf_update()
2965 bp->port.pmf = 1; in bnx2x_pmf_update()
2966 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf); in bnx2x_pmf_update()
2975 queue_delayed_work(bnx2x_wq, &bp->period_task, 0); in bnx2x_pmf_update()
2977 bnx2x_dcbx_pmf_update(bp); in bnx2x_pmf_update()
2980 val = (0xff0f | (1 << (BP_VN(bp) + 4))); in bnx2x_pmf_update()
2981 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_pmf_update()
2982 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2983 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2984 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_pmf_update()
2985 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
2986 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
2989 bnx2x_stats_handle(bp, STATS_EVENT_PMF); in bnx2x_pmf_update()
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param) in bnx2x_fw_command() argument
3003 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_fw_command()
3007 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10; in bnx2x_fw_command()
3009 mutex_lock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3010 seq = ++bp->fw_seq; in bnx2x_fw_command()
3011 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param); in bnx2x_fw_command()
3012 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq)); in bnx2x_fw_command()
3021 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header); in bnx2x_fw_command()
3035 bnx2x_fw_dump(bp); in bnx2x_fw_command()
3038 mutex_unlock(&bp->fw_mb_mutex); in bnx2x_fw_command()
3043 static void storm_memset_func_cfg(struct bnx2x *bp, in storm_memset_func_cfg() argument
3052 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); in storm_memset_func_cfg()
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p) in bnx2x_func_init() argument
3057 if (CHIP_IS_E1x(bp)) { in bnx2x_func_init()
3060 storm_memset_func_cfg(bp, &tcfg, p->func_id); in bnx2x_func_init()
3064 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id); in bnx2x_func_init()
3065 storm_memset_func_en(bp, p->func_id, 1); in bnx2x_func_init()
3069 storm_memset_spq_addr(bp, p->spq_map, p->func_id); in bnx2x_func_init()
3070 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp, in bnx2x_get_common_flags() argument
3102 if (bp->flags & TX_SWITCHING) in bnx2x_get_common_flags()
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp, in bnx2x_get_q_flags() argument
3122 if (IS_MF_SD(bp)) in bnx2x_get_q_flags()
3147 if (IS_MF_AFEX(bp)) in bnx2x_get_q_flags()
3150 return flags | bnx2x_get_common_flags(bp, fp, true); in bnx2x_get_q_flags()
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp, in bnx2x_pf_q_prep_general() argument
3164 gen_init->mtu = bp->dev->mtu; in bnx2x_pf_q_prep_general()
3171 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp, in bnx2x_pf_rx_q_prep() argument
3180 pause->sge_th_lo = SGE_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3181 pause->sge_th_hi = SGE_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3184 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3189 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >> in bnx2x_pf_rx_q_prep()
3197 if (!CHIP_IS_E1(bp)) { in bnx2x_pf_rx_q_prep()
3198 pause->bd_th_lo = BD_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3199 pause->bd_th_hi = BD_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3201 pause->rcq_th_lo = RCQ_TH_LO(bp); in bnx2x_pf_rx_q_prep()
3202 pause->rcq_th_hi = RCQ_TH_HI(bp); in bnx2x_pf_rx_q_prep()
3207 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3209 bp->rx_ring_size); in bnx2x_pf_rx_q_prep()
3210 WARN_ON(bp->dropless_fc && in bnx2x_pf_rx_q_prep()
3233 rxq_init->rss_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3234 rxq_init->mcast_engine_id = BP_FUNC(bp); in bnx2x_pf_rx_q_prep()
3241 rxq_init->max_tpa_queues = MAX_AGG_QS(bp); in bnx2x_pf_rx_q_prep()
3253 if (IS_MF_AFEX(bp)) { in bnx2x_pf_rx_q_prep()
3254 rxq_init->silent_removal_value = bp->afex_def_vlan_tag; in bnx2x_pf_rx_q_prep()
3259 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp, in bnx2x_pf_tx_q_prep() argument
3272 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id); in bnx2x_pf_tx_q_prep()
3280 static void bnx2x_pf_init(struct bnx2x *bp) in bnx2x_pf_init() argument
3286 if (!CHIP_IS_E1x(bp)) { in bnx2x_pf_init()
3289 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3291 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3292 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3294 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3297 (CHIP_MODE_IS_4_PORT(bp) ? in bnx2x_pf_init()
3298 BP_FUNC(bp) : BP_VN(bp))*4, 0); in bnx2x_pf_init()
3307 flags |= (bp->dev->features & NETIF_F_LRO) ? FUNC_FLG_TPA : 0; in bnx2x_pf_init()
3310 func_init.pf_id = BP_FUNC(bp); in bnx2x_pf_init()
3311 func_init.func_id = BP_FUNC(bp); in bnx2x_pf_init()
3312 func_init.spq_map = bp->spq_mapping; in bnx2x_pf_init()
3313 func_init.spq_prod = bp->spq_prod_idx; in bnx2x_pf_init()
3315 bnx2x_func_init(bp, &func_init); in bnx2x_pf_init()
3317 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port)); in bnx2x_pf_init()
3325 bp->link_vars.line_speed = SPEED_10000; in bnx2x_pf_init()
3326 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp)); in bnx2x_pf_init()
3329 if (bp->port.pmf) in bnx2x_pf_init()
3330 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_pf_init()
3333 eq_data.base_addr.hi = U64_HI(bp->eq_mapping); in bnx2x_pf_init()
3334 eq_data.base_addr.lo = U64_LO(bp->eq_mapping); in bnx2x_pf_init()
3335 eq_data.producer = bp->eq_prod; in bnx2x_pf_init()
3338 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp)); in bnx2x_pf_init()
3341 static void bnx2x_e1h_disable(struct bnx2x *bp) in bnx2x_e1h_disable() argument
3343 int port = BP_PORT(bp); in bnx2x_e1h_disable()
3345 bnx2x_tx_disable(bp); in bnx2x_e1h_disable()
3347 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3350 static void bnx2x_e1h_enable(struct bnx2x *bp) in bnx2x_e1h_enable() argument
3352 int port = BP_PORT(bp); in bnx2x_e1h_enable()
3354 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) in bnx2x_e1h_enable()
3355 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_e1h_enable()
3358 netif_tx_wake_all_queues(bp->dev); in bnx2x_e1h_enable()
3368 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp) in bnx2x_drv_info_ether_stat() argument
3371 &bp->slowpath->drv_info_to_mcp.ether_stat; in bnx2x_drv_info_ether_stat()
3373 &bp->sp_objs->mac_obj; in bnx2x_drv_info_ether_stat()
3390 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj, in bnx2x_drv_info_ether_stat()
3394 ether_stat->mtu_size = bp->dev->mtu; in bnx2x_drv_info_ether_stat()
3395 if (bp->dev->features & NETIF_F_RXCSUM) in bnx2x_drv_info_ether_stat()
3397 if (bp->dev->features & NETIF_F_TSO) in bnx2x_drv_info_ether_stat()
3399 ether_stat->feature_flags |= bp->common.boot_mode; in bnx2x_drv_info_ether_stat()
3401 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0; in bnx2x_drv_info_ether_stat()
3403 ether_stat->txq_size = bp->tx_ring_size; in bnx2x_drv_info_ether_stat()
3404 ether_stat->rxq_size = bp->rx_ring_size; in bnx2x_drv_info_ether_stat()
3407 ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0; in bnx2x_drv_info_ether_stat()
3411 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp) in bnx2x_drv_info_fcoe_stat() argument
3413 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_fcoe_stat()
3415 &bp->slowpath->drv_info_to_mcp.fcoe_stat; in bnx2x_drv_info_fcoe_stat()
3417 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_fcoe_stat()
3420 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN); in bnx2x_drv_info_fcoe_stat()
3426 if (!NO_FCOE(bp)) { in bnx2x_drv_info_fcoe_stat()
3428 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3432 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)]. in bnx2x_drv_info_fcoe_stat()
3436 &bp->fw_stats_data->fcoe; in bnx2x_drv_info_fcoe_stat()
3510 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD); in bnx2x_drv_info_fcoe_stat()
3513 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp) in bnx2x_drv_info_iscsi_stat() argument
3515 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app; in bnx2x_drv_info_iscsi_stat()
3517 &bp->slowpath->drv_info_to_mcp.iscsi_stat; in bnx2x_drv_info_iscsi_stat()
3519 if (!CNIC_LOADED(bp)) in bnx2x_drv_info_iscsi_stat()
3522 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac, in bnx2x_drv_info_iscsi_stat()
3529 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD); in bnx2x_drv_info_iscsi_stat()
3537 static void bnx2x_config_mf_bw(struct bnx2x *bp) in bnx2x_config_mf_bw() argument
3539 if (bp->link_vars.link_up) { in bnx2x_config_mf_bw()
3540 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX); in bnx2x_config_mf_bw()
3541 bnx2x_link_sync_notify(bp); in bnx2x_config_mf_bw()
3543 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp)); in bnx2x_config_mf_bw()
3546 static void bnx2x_set_mf_bw(struct bnx2x *bp) in bnx2x_set_mf_bw() argument
3548 bnx2x_config_mf_bw(bp); in bnx2x_set_mf_bw()
3549 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0); in bnx2x_set_mf_bw()
3552 static void bnx2x_handle_eee_event(struct bnx2x *bp) in bnx2x_handle_eee_event() argument
3555 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); in bnx2x_handle_eee_event()
3561 static void bnx2x_handle_drv_info_req(struct bnx2x *bp) in bnx2x_handle_drv_info_req() argument
3564 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control); in bnx2x_handle_drv_info_req()
3570 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3578 mutex_lock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3580 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_handle_drv_info_req()
3585 bnx2x_drv_info_ether_stat(bp); in bnx2x_handle_drv_info_req()
3588 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_handle_drv_info_req()
3591 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_handle_drv_info_req()
3595 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0); in bnx2x_handle_drv_info_req()
3602 SHMEM2_WR(bp, drv_info_host_addr_lo, in bnx2x_handle_drv_info_req()
3603 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3604 SHMEM2_WR(bp, drv_info_host_addr_hi, in bnx2x_handle_drv_info_req()
3605 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp))); in bnx2x_handle_drv_info_req()
3607 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0); in bnx2x_handle_drv_info_req()
3613 if (!SHMEM2_HAS(bp, mfw_drv_indication)) { in bnx2x_handle_drv_info_req()
3615 } else if (!bp->drv_info_mng_owner) { in bnx2x_handle_drv_info_req()
3616 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1)); in bnx2x_handle_drv_info_req()
3619 u32 indication = SHMEM2_RD(bp, mfw_drv_indication); in bnx2x_handle_drv_info_req()
3623 SHMEM2_WR(bp, mfw_drv_indication, in bnx2x_handle_drv_info_req()
3634 bp->drv_info_mng_owner = true; in bnx2x_handle_drv_info_req()
3638 mutex_unlock(&bp->drv_info_mutex); in bnx2x_handle_drv_info_req()
3662 void bnx2x_update_mng_version(struct bnx2x *bp) in bnx2x_update_mng_version() argument
3667 int idx = BP_FW_MB_IDX(bp); in bnx2x_update_mng_version()
3670 if (!SHMEM2_HAS(bp, func_os_drv_ver)) in bnx2x_update_mng_version()
3673 mutex_lock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3675 if (bp->drv_info_mng_owner) in bnx2x_update_mng_version()
3678 if (bp->state != BNX2X_STATE_OPEN) in bnx2x_update_mng_version()
3683 if (!CNIC_LOADED(bp)) in bnx2x_update_mng_version()
3687 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3689 bnx2x_drv_info_iscsi_stat(bp); in bnx2x_update_mng_version()
3690 version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version; in bnx2x_update_mng_version()
3693 memset(&bp->slowpath->drv_info_to_mcp, 0, in bnx2x_update_mng_version()
3695 bnx2x_drv_info_fcoe_stat(bp); in bnx2x_update_mng_version()
3696 version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version; in bnx2x_update_mng_version()
3700 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver); in bnx2x_update_mng_version()
3701 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver); in bnx2x_update_mng_version()
3702 SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever); in bnx2x_update_mng_version()
3704 mutex_unlock(&bp->drv_info_mutex); in bnx2x_update_mng_version()
3710 static void bnx2x_oem_event(struct bnx2x *bp, u32 event) in bnx2x_oem_event() argument
3737 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) { in bnx2x_oem_event()
3739 bp->flags |= MF_FUNC_DIS; in bnx2x_oem_event()
3741 bnx2x_e1h_disable(bp); in bnx2x_oem_event()
3744 bp->flags &= ~MF_FUNC_DIS; in bnx2x_oem_event()
3746 bnx2x_e1h_enable(bp); in bnx2x_oem_event()
3754 bnx2x_config_mf_bw(bp); in bnx2x_oem_event()
3761 bnx2x_fw_command(bp, cmd_fail, 0); in bnx2x_oem_event()
3763 bnx2x_fw_command(bp, cmd_ok, 0); in bnx2x_oem_event()
3767 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp) in bnx2x_sp_get_next() argument
3769 struct eth_spe *next_spe = bp->spq_prod_bd; in bnx2x_sp_get_next()
3771 if (bp->spq_prod_bd == bp->spq_last_bd) { in bnx2x_sp_get_next()
3772 bp->spq_prod_bd = bp->spq; in bnx2x_sp_get_next()
3773 bp->spq_prod_idx = 0; in bnx2x_sp_get_next()
3776 bp->spq_prod_bd++; in bnx2x_sp_get_next()
3777 bp->spq_prod_idx++; in bnx2x_sp_get_next()
3783 static void bnx2x_sp_prod_update(struct bnx2x *bp) in bnx2x_sp_prod_update() argument
3785 int func = BP_FUNC(bp); in bnx2x_sp_prod_update()
3794 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func), in bnx2x_sp_prod_update()
3795 bp->spq_prod_idx); in bnx2x_sp_prod_update()
3833 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, in bnx2x_sp_post() argument
3841 if (unlikely(bp->panic)) { in bnx2x_sp_post()
3847 spin_lock_bh(&bp->spq_lock); in bnx2x_sp_post()
3850 if (!atomic_read(&bp->eq_spq_left)) { in bnx2x_sp_post()
3852 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3856 } else if (!atomic_read(&bp->cq_spq_left)) { in bnx2x_sp_post()
3858 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3863 spe = bnx2x_sp_get_next(bp); in bnx2x_sp_post()
3868 HW_CID(bp, cid)); in bnx2x_sp_post()
3877 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) & in bnx2x_sp_post()
3894 atomic_dec(&bp->eq_spq_left); in bnx2x_sp_post()
3896 atomic_dec(&bp->cq_spq_left); in bnx2x_sp_post()
3900 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping), in bnx2x_sp_post()
3901 (u32)(U64_LO(bp->spq_mapping) + in bnx2x_sp_post()
3902 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common, in bnx2x_sp_post()
3903 HW_CID(bp, cid), data_hi, data_lo, type, in bnx2x_sp_post()
3904 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left)); in bnx2x_sp_post()
3906 bnx2x_sp_prod_update(bp); in bnx2x_sp_post()
3907 spin_unlock_bh(&bp->spq_lock); in bnx2x_sp_post()
3912 static int bnx2x_acquire_alr(struct bnx2x *bp) in bnx2x_acquire_alr() argument
3919 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); in bnx2x_acquire_alr()
3920 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK); in bnx2x_acquire_alr()
3935 static void bnx2x_release_alr(struct bnx2x *bp) in bnx2x_release_alr() argument
3937 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
3943 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp) in bnx2x_update_dsb_idx() argument
3945 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_update_dsb_idx()
3949 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) { in bnx2x_update_dsb_idx()
3950 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index; in bnx2x_update_dsb_idx()
3954 if (bp->def_idx != def_sb->sp_sb.running_index) { in bnx2x_update_dsb_idx()
3955 bp->def_idx = def_sb->sp_sb.running_index; in bnx2x_update_dsb_idx()
3968 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted) in bnx2x_attn_int_asserted() argument
3970 int port = BP_PORT(bp); in bnx2x_attn_int_asserted()
3979 if (bp->attn_state & asserted) in bnx2x_attn_int_asserted()
3982 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
3983 aeu_mask = REG_RD(bp, aeu_addr); in bnx2x_attn_int_asserted()
3990 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
3991 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_asserted()
3993 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
3994 bp->attn_state |= asserted; in bnx2x_attn_int_asserted()
3995 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_asserted()
4000 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_asserted()
4003 nig_mask = REG_RD(bp, nig_int_mask_addr); in bnx2x_attn_int_asserted()
4009 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4011 bnx2x_link_attn(bp); in bnx2x_attn_int_asserted()
4031 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4035 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4039 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4044 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4048 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4052 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4058 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_asserted()
4065 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_asserted()
4066 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
4073 if (bp->common.int_block != INT_BLOCK_HC) { in bnx2x_attn_int_asserted()
4076 igu_acked = REG_RD(bp, in bnx2x_attn_int_asserted()
4085 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
4086 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_asserted()
4090 static void bnx2x_fan_failure(struct bnx2x *bp) in bnx2x_fan_failure() argument
4092 int port = BP_PORT(bp); in bnx2x_fan_failure()
4096 SHMEM_RD(bp, in bnx2x_fan_failure()
4101 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config, in bnx2x_fan_failure()
4105 …netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card … in bnx2x_fan_failure()
4112 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0); in bnx2x_fan_failure()
4115 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted0() argument
4117 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted0()
4126 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4128 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4133 bnx2x_hw_reset_phy(&bp->link_params); in bnx2x_attn_int_deasserted0()
4134 bnx2x_fan_failure(bp); in bnx2x_attn_int_deasserted0()
4137 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) { in bnx2x_attn_int_deasserted0()
4138 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4139 bnx2x_handle_module_detect_int(&bp->link_params); in bnx2x_attn_int_deasserted0()
4140 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted0()
4145 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted0()
4147 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4155 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted1() argument
4161 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR); in bnx2x_attn_int_deasserted1()
4170 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted1()
4176 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted1()
4178 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
4186 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted2() argument
4192 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR); in bnx2x_attn_int_deasserted2()
4200 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0); in bnx2x_attn_int_deasserted2()
4206 if (!CHIP_IS_E1x(bp)) { in bnx2x_attn_int_deasserted2()
4207 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1); in bnx2x_attn_int_deasserted2()
4214 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted2()
4220 val = REG_RD(bp, reg_offset); in bnx2x_attn_int_deasserted2()
4222 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
4230 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted3() argument
4237 int func = BP_FUNC(bp); in bnx2x_attn_int_deasserted3()
4239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4240 bnx2x_read_mf_cfg(bp); in bnx2x_attn_int_deasserted3()
4241 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp, in bnx2x_attn_int_deasserted3()
4242 func_mf_config[BP_ABS_FUNC(bp)].config); in bnx2x_attn_int_deasserted3()
4243 val = SHMEM_RD(bp, in bnx2x_attn_int_deasserted3()
4244 func_mb[BP_FW_MB_IDX(bp)].drv_status); in bnx2x_attn_int_deasserted3()
4248 bnx2x_oem_event(bp, in bnx2x_attn_int_deasserted3()
4253 bnx2x_set_mf_bw(bp); in bnx2x_attn_int_deasserted3()
4256 bnx2x_handle_drv_info_req(bp); in bnx2x_attn_int_deasserted3()
4259 bnx2x_schedule_iov_task(bp, in bnx2x_attn_int_deasserted3()
4262 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF)) in bnx2x_attn_int_deasserted3()
4263 bnx2x_pmf_update(bp); in bnx2x_attn_int_deasserted3()
4265 if (bp->port.pmf && in bnx2x_attn_int_deasserted3()
4267 bp->dcbx_enabled > 0) in bnx2x_attn_int_deasserted3()
4269 bnx2x_dcbx_set_params(bp, in bnx2x_attn_int_deasserted3()
4272 bnx2x_handle_afex_cmd(bp, in bnx2x_attn_int_deasserted3()
4275 bnx2x_handle_eee_event(bp); in bnx2x_attn_int_deasserted3()
4278 bnx2x_handle_update_svid_cmd(bp); in bnx2x_attn_int_deasserted3()
4280 if (bp->link_vars.periodic_flags & in bnx2x_attn_int_deasserted3()
4283 bnx2x_acquire_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4284 bp->link_vars.periodic_flags &= in bnx2x_attn_int_deasserted3()
4286 bnx2x_release_phy_lock(bp); in bnx2x_attn_int_deasserted3()
4287 if (IS_MF(bp)) in bnx2x_attn_int_deasserted3()
4288 bnx2x_link_sync_notify(bp); in bnx2x_attn_int_deasserted3()
4289 bnx2x_link_report(bp); in bnx2x_attn_int_deasserted3()
4294 bnx2x__link_status_update(bp); in bnx2x_attn_int_deasserted3()
4298 bnx2x_mc_assert(bp); in bnx2x_attn_int_deasserted3()
4299 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4300 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4302 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4308 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4309 bnx2x_fw_dump(bp); in bnx2x_attn_int_deasserted3()
4318 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4319 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN); in bnx2x_attn_int_deasserted3()
4323 val = CHIP_IS_E1(bp) ? 0 : in bnx2x_attn_int_deasserted3()
4324 REG_RD(bp, MISC_REG_GRC_RSV_ATTN); in bnx2x_attn_int_deasserted3()
4327 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4360 void bnx2x_set_reset_global(struct bnx2x *bp) in bnx2x_set_reset_global() argument
4363 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4364 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_global()
4365 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); in bnx2x_set_reset_global()
4366 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_global()
4374 static void bnx2x_clear_reset_global(struct bnx2x *bp) in bnx2x_clear_reset_global() argument
4377 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4378 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_reset_global()
4379 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); in bnx2x_clear_reset_global()
4380 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_reset_global()
4388 static bool bnx2x_reset_is_global(struct bnx2x *bp) in bnx2x_reset_is_global() argument
4390 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_global()
4401 static void bnx2x_set_reset_done(struct bnx2x *bp) in bnx2x_set_reset_done() argument
4404 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_done()
4406 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4407 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_done()
4411 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_done()
4413 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_done()
4421 void bnx2x_set_reset_in_progress(struct bnx2x *bp) in bnx2x_set_reset_in_progress() argument
4424 u32 bit = BP_PATH(bp) ? in bnx2x_set_reset_in_progress()
4426 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4427 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_reset_in_progress()
4431 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_in_progress()
4432 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_reset_in_progress()
4439 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine) in bnx2x_reset_is_done() argument
4441 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_reset_is_done()
4454 void bnx2x_set_pf_load(struct bnx2x *bp) in bnx2x_set_pf_load() argument
4457 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_set_pf_load()
4459 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_set_pf_load()
4462 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4463 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_set_pf_load()
4471 val1 |= (1 << bp->pf_num); in bnx2x_set_pf_load()
4479 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_pf_load()
4480 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_set_pf_load()
4492 bool bnx2x_clear_pf_load(struct bnx2x *bp) in bnx2x_clear_pf_load() argument
4495 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK : in bnx2x_clear_pf_load()
4497 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT : in bnx2x_clear_pf_load()
4500 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4501 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_clear_pf_load()
4508 val1 &= ~(1 << bp->pf_num); in bnx2x_clear_pf_load()
4516 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_clear_pf_load()
4517 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG); in bnx2x_clear_pf_load()
4526 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine) in bnx2x_get_load_status() argument
4532 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG); in bnx2x_get_load_status()
4544 static void _print_parity(struct bnx2x *bp, u32 reg) in _print_parity() argument
4546 pr_cont(" [0x%08x] ", REG_RD(bp, reg)); in _print_parity()
4554 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity0() argument
4572 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4578 _print_parity(bp, PRS_REG_PRS_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4582 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4588 _print_parity(bp, SRC_REG_SRC_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4592 _print_parity(bp, TCM_REG_TCM_PRTY_STS); in bnx2x_check_blocks_with_parity0()
4597 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4599 _print_parity(bp, in bnx2x_check_blocks_with_parity0()
4604 _print_parity(bp, GRCBASE_XPB + in bnx2x_check_blocks_with_parity0()
4618 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity1() argument
4636 _print_parity(bp, PBF_REG_PBF_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4642 _print_parity(bp, QM_REG_QM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4648 _print_parity(bp, TM_REG_TM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4654 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4661 _print_parity(bp, XCM_REG_XCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4668 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4670 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4678 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4685 if (CHIP_IS_E1x(bp)) { in bnx2x_check_blocks_with_parity1()
4686 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4689 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4691 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4706 _print_parity(bp, DBG_REG_DBG_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4712 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4719 _print_parity(bp, UCM_REG_UCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4726 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4728 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4735 _print_parity(bp, GRCBASE_UPB + in bnx2x_check_blocks_with_parity1()
4742 _print_parity(bp, in bnx2x_check_blocks_with_parity1()
4749 _print_parity(bp, CCM_REG_CCM_PRTY_STS); in bnx2x_check_blocks_with_parity1()
4762 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity2() argument
4780 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4782 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4787 _print_parity(bp, PXP_REG_PXP_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4788 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4790 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4799 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4804 _print_parity(bp, CDU_REG_CDU_PRTY_STS); in bnx2x_check_blocks_with_parity2()
4808 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4813 if (CHIP_IS_E1x(bp)) in bnx2x_check_blocks_with_parity2()
4814 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4817 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4822 _print_parity(bp, in bnx2x_check_blocks_with_parity2()
4836 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity3() argument
4874 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, in bnx2x_check_blocks_with_parity3()
4887 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig, in bnx2x_check_blocks_with_parity4() argument
4905 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4910 _print_parity(bp, in bnx2x_check_blocks_with_parity4()
4923 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print, in bnx2x_parity_attn() argument
4942 netdev_err(bp->dev, in bnx2x_parity_attn()
4944 res |= bnx2x_check_blocks_with_parity0(bp, in bnx2x_parity_attn()
4946 res |= bnx2x_check_blocks_with_parity1(bp, in bnx2x_parity_attn()
4948 res |= bnx2x_check_blocks_with_parity2(bp, in bnx2x_parity_attn()
4950 res |= bnx2x_check_blocks_with_parity3(bp, in bnx2x_parity_attn()
4952 res |= bnx2x_check_blocks_with_parity4(bp, in bnx2x_parity_attn()
4969 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print) in bnx2x_chk_parity_attn() argument
4972 int port = BP_PORT(bp); in bnx2x_chk_parity_attn()
4974 attn.sig[0] = REG_RD(bp, in bnx2x_chk_parity_attn()
4977 attn.sig[1] = REG_RD(bp, in bnx2x_chk_parity_attn()
4980 attn.sig[2] = REG_RD(bp, in bnx2x_chk_parity_attn()
4983 attn.sig[3] = REG_RD(bp, in bnx2x_chk_parity_attn()
4989 attn.sig[3] &= ((REG_RD(bp, in bnx2x_chk_parity_attn()
4995 if (!CHIP_IS_E1x(bp)) in bnx2x_chk_parity_attn()
4996 attn.sig[4] = REG_RD(bp, in bnx2x_chk_parity_attn()
5000 return bnx2x_parity_attn(bp, global, print, attn.sig); in bnx2x_chk_parity_attn()
5003 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn) in bnx2x_attn_int_deasserted4() argument
5008 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5032 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR); in bnx2x_attn_int_deasserted4()
5056 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted) in bnx2x_attn_int_deasserted() argument
5059 int port = BP_PORT(bp); in bnx2x_attn_int_deasserted()
5068 bnx2x_acquire_alr(bp); in bnx2x_attn_int_deasserted()
5070 if (bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_attn_int_deasserted()
5072 bp->recovery_state = BNX2X_RECOVERY_INIT; in bnx2x_attn_int_deasserted()
5073 schedule_delayed_work(&bp->sp_rtnl_task, 0); in bnx2x_attn_int_deasserted()
5075 bnx2x_int_disable(bp); in bnx2x_attn_int_deasserted()
5082 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5086 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5087 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5088 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5089 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5090 if (!CHIP_IS_E1x(bp)) in bnx2x_attn_int_deasserted()
5092 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); in bnx2x_attn_int_deasserted()
5101 group_mask = &bp->attn_group[index]; in bnx2x_attn_int_deasserted()
5109 bnx2x_attn_int_deasserted4(bp, in bnx2x_attn_int_deasserted()
5111 bnx2x_attn_int_deasserted3(bp, in bnx2x_attn_int_deasserted()
5113 bnx2x_attn_int_deasserted1(bp, in bnx2x_attn_int_deasserted()
5115 bnx2x_attn_int_deasserted2(bp, in bnx2x_attn_int_deasserted()
5117 bnx2x_attn_int_deasserted0(bp, in bnx2x_attn_int_deasserted()
5122 bnx2x_release_alr(bp); in bnx2x_attn_int_deasserted()
5124 if (bp->common.int_block == INT_BLOCK_HC) in bnx2x_attn_int_deasserted()
5132 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); in bnx2x_attn_int_deasserted()
5133 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5135 if (~bp->attn_state & deasserted) in bnx2x_attn_int_deasserted()
5141 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5142 aeu_mask = REG_RD(bp, reg_addr); in bnx2x_attn_int_deasserted()
5149 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
5150 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); in bnx2x_attn_int_deasserted()
5152 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5153 bp->attn_state &= ~deasserted; in bnx2x_attn_int_deasserted()
5154 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state); in bnx2x_attn_int_deasserted()
5157 static void bnx2x_attn_int(struct bnx2x *bp) in bnx2x_attn_int() argument
5160 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5162 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block. in bnx2x_attn_int()
5164 u32 attn_state = bp->attn_state; in bnx2x_attn_int()
5179 bnx2x_attn_int_asserted(bp, asserted); in bnx2x_attn_int()
5182 bnx2x_attn_int_deasserted(bp, deasserted); in bnx2x_attn_int()
5185 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, in bnx2x_igu_ack_sb() argument
5188 u32 igu_addr = bp->igu_base_addr; in bnx2x_igu_ack_sb()
5190 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update, in bnx2x_igu_ack_sb()
5194 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod) in bnx2x_update_eq_prod() argument
5197 storm_memset_eq_prod(bp, prod, BP_FUNC(bp)); in bnx2x_update_eq_prod()
5201 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid, in bnx2x_cnic_handle_cfc_del() argument
5206 if (!bp->cnic_eth_dev.starting_cid || in bnx2x_cnic_handle_cfc_del()
5207 (cid < bp->cnic_eth_dev.starting_cid && in bnx2x_cnic_handle_cfc_del()
5208 cid != bp->cnic_eth_dev.iscsi_l2_cid)) in bnx2x_cnic_handle_cfc_del()
5217 bnx2x_panic_dump(bp, false); in bnx2x_cnic_handle_cfc_del()
5219 bnx2x_cnic_cfc_comp(bp, cid, err); in bnx2x_cnic_handle_cfc_del()
5223 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp) in bnx2x_handle_mcast_eqe() argument
5230 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_handle_mcast_eqe()
5232 netif_addr_lock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5235 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw); in bnx2x_handle_mcast_eqe()
5238 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) { in bnx2x_handle_mcast_eqe()
5239 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT); in bnx2x_handle_mcast_eqe()
5245 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_mcast_eqe()
5248 static void bnx2x_handle_classification_eqe(struct bnx2x *bp, in bnx2x_handle_classification_eqe() argument
5263 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp))) in bnx2x_handle_classification_eqe()
5264 vlan_mac_obj = &bp->iscsi_l2_mac_obj; in bnx2x_handle_classification_eqe()
5266 vlan_mac_obj = &bp->sp_objs[cid].mac_obj; in bnx2x_handle_classification_eqe()
5274 bnx2x_handle_mcast_eqe(bp); in bnx2x_handle_classification_eqe()
5282 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags); in bnx2x_handle_classification_eqe()
5290 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5292 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp) in bnx2x_handle_rx_mode_eqe() argument
5294 netif_addr_lock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5296 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_handle_rx_mode_eqe()
5299 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5300 bnx2x_set_storm_rx_mode(bp); in bnx2x_handle_rx_mode_eqe()
5302 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5303 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_handle_rx_mode_eqe()
5305 &bp->sp_state)) in bnx2x_handle_rx_mode_eqe()
5306 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_handle_rx_mode_eqe()
5308 netif_addr_unlock_bh(bp->dev); in bnx2x_handle_rx_mode_eqe()
5311 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp, in bnx2x_after_afex_vif_lists() argument
5318 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK, in bnx2x_after_afex_vif_lists()
5323 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0); in bnx2x_after_afex_vif_lists()
5328 static void bnx2x_after_function_update(struct bnx2x *bp) in bnx2x_after_function_update() argument
5347 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) { in bnx2x_after_function_update()
5352 (bp->afex_def_vlan_tag & VLAN_VID_MASK); in bnx2x_after_function_update()
5356 for_each_eth_queue(bp, q) { in bnx2x_after_function_update()
5358 fp = &bp->fp[q]; in bnx2x_after_function_update()
5359 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5362 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5368 if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) { in bnx2x_after_function_update()
5369 fp = &bp->fp[FCOE_IDX(bp)]; in bnx2x_after_function_update()
5370 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_after_function_update()
5377 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state); in bnx2x_after_function_update()
5381 rc = bnx2x_queue_state_change(bp, &queue_params); in bnx2x_after_function_update()
5387 bnx2x_link_report(bp); in bnx2x_after_function_update()
5388 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_after_function_update()
5393 struct bnx2x *bp, u32 cid) in bnx2x_cid_to_q_obj() argument
5397 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp))) in bnx2x_cid_to_q_obj()
5398 return &bnx2x_fcoe_sp_obj(bp, q_obj); in bnx2x_cid_to_q_obj()
5400 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj; in bnx2x_cid_to_q_obj()
5403 static void bnx2x_eq_int(struct bnx2x *bp) in bnx2x_eq_int() argument
5412 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj; in bnx2x_eq_int()
5413 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw; in bnx2x_eq_int()
5415 hw_cons = le16_to_cpu(*bp->eq_cons_sb); in bnx2x_eq_int()
5429 sw_cons = bp->eq_cons; in bnx2x_eq_int()
5430 sw_prod = bp->eq_prod; in bnx2x_eq_int()
5433 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left)); in bnx2x_eq_int()
5438 elem = &bp->eq_ring[EQ_DESC(sw_cons)]; in bnx2x_eq_int()
5440 rc = bnx2x_iov_eq_sp_event(bp, elem); in bnx2x_eq_int()
5455 bnx2x_vf_mbx_schedule(bp, in bnx2x_eq_int()
5462 bp->stats_comp++); in bnx2x_eq_int()
5475 if (CNIC_LOADED(bp) && in bnx2x_eq_int()
5476 !bnx2x_cnic_handle_cfc_del(bp, cid, elem)) in bnx2x_eq_int()
5479 q_obj = bnx2x_cid_to_q_obj(bp, cid); in bnx2x_eq_int()
5481 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL)) in bnx2x_eq_int()
5488 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED); in bnx2x_eq_int()
5489 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5496 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED); in bnx2x_eq_int()
5497 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5508 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE)) in bnx2x_eq_int()
5516 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5523 bnx2x_schedule_sp_rtnl(bp, cmd, 0); in bnx2x_eq_int()
5529 f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5531 bnx2x_after_afex_vif_lists(bp, elem); in bnx2x_eq_int()
5536 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START)) in bnx2x_eq_int()
5544 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP)) in bnx2x_eq_int()
5552 if (f_obj->complete_cmd(bp, f_obj, in bnx2x_eq_int()
5558 switch (opcode | bp->state) { in bnx2x_eq_int()
5581 bnx2x_handle_classification_eqe(bp, elem); in bnx2x_eq_int()
5591 bnx2x_handle_mcast_eqe(bp); in bnx2x_eq_int()
5601 bnx2x_handle_rx_mode_eqe(bp); in bnx2x_eq_int()
5606 elem->message.opcode, bp->state); in bnx2x_eq_int()
5613 atomic_add(spqe_cnt, &bp->eq_spq_left); in bnx2x_eq_int()
5615 bp->eq_cons = sw_cons; in bnx2x_eq_int()
5616 bp->eq_prod = sw_prod; in bnx2x_eq_int()
5621 bnx2x_update_eq_prod(bp, bp->eq_prod); in bnx2x_eq_int()
5626 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work); in bnx2x_sp_task() local
5632 if (atomic_read(&bp->interrupt_occurred)) { in bnx2x_sp_task()
5635 u16 status = bnx2x_update_dsb_idx(bp); in bnx2x_sp_task()
5639 atomic_set(&bp->interrupt_occurred, 0); in bnx2x_sp_task()
5643 bnx2x_attn_int(bp); in bnx2x_sp_task()
5649 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_sp_task()
5651 if (FCOE_INIT(bp) && in bnx2x_sp_task()
5657 napi_schedule(&bnx2x_fcoe(bp, napi)); in bnx2x_sp_task()
5662 bnx2x_eq_int(bp); in bnx2x_sp_task()
5663 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, in bnx2x_sp_task()
5664 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1); in bnx2x_sp_task()
5675 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID, in bnx2x_sp_task()
5676 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1); in bnx2x_sp_task()
5681 &bp->sp_state)) { in bnx2x_sp_task()
5682 bnx2x_link_report(bp); in bnx2x_sp_task()
5683 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); in bnx2x_sp_task()
5690 struct bnx2x *bp = netdev_priv(dev); in bnx2x_msix_sp_int() local
5692 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, in bnx2x_msix_sp_int()
5696 if (unlikely(bp->panic)) in bnx2x_msix_sp_int()
5700 if (CNIC_LOADED(bp)) { in bnx2x_msix_sp_int()
5704 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_msix_sp_int()
5706 c_ops->cnic_handler(bp->cnic_data, NULL); in bnx2x_msix_sp_int()
5713 bnx2x_schedule_sp_task(bp); in bnx2x_msix_sp_int()
5720 void bnx2x_drv_pulse(struct bnx2x *bp) in bnx2x_drv_pulse() argument
5722 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb, in bnx2x_drv_pulse()
5723 bp->fw_drv_pulse_wr_seq); in bnx2x_drv_pulse()
5728 struct bnx2x *bp = (struct bnx2x *) data; in bnx2x_timer() local
5730 if (!netif_running(bp->dev)) in bnx2x_timer()
5733 if (IS_PF(bp) && in bnx2x_timer()
5734 !BP_NOMCP(bp)) { in bnx2x_timer()
5735 int mb_idx = BP_FW_MB_IDX(bp); in bnx2x_timer()
5739 ++bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5740 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; in bnx2x_timer()
5741 drv_pulse = bp->fw_drv_pulse_wr_seq; in bnx2x_timer()
5742 bnx2x_drv_pulse(bp); in bnx2x_timer()
5744 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & in bnx2x_timer()
5756 if (bp->state == BNX2X_STATE_OPEN) in bnx2x_timer()
5757 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE); in bnx2x_timer()
5760 if (IS_VF(bp)) in bnx2x_timer()
5761 bnx2x_timer_sriov(bp); in bnx2x_timer()
5763 mod_timer(&bp->timer, jiffies + bp->current_interval); in bnx2x_timer()
5774 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) in bnx2x_fill() argument
5779 REG_WR(bp, addr + i, fill); in bnx2x_fill()
5782 REG_WR8(bp, addr + i, fill); in bnx2x_fill()
5786 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp, in bnx2x_wr_fp_sb_data() argument
5793 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
5799 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id) in bnx2x_zero_fp_sb() argument
5807 if (!CHIP_IS_E1x(bp)) { in bnx2x_zero_fp_sb()
5821 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_zero_fp_sb()
5823 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5826 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_fp_sb()
5832 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp, in bnx2x_wr_sp_sb_data() argument
5835 int func = BP_FUNC(bp); in bnx2x_wr_sp_sb_data()
5838 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
5844 static void bnx2x_zero_sp_sb(struct bnx2x *bp) in bnx2x_zero_sp_sb() argument
5846 int func = BP_FUNC(bp); in bnx2x_zero_sp_sb()
5853 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_zero_sp_sb()
5855 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5858 bnx2x_fill(bp, BAR_CSTRORM_INTMEM + in bnx2x_zero_sp_sb()
5901 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, in bnx2x_init_sb() argument
5912 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_init_sb()
5917 bnx2x_zero_fp_sb(bp, fw_sb_id); in bnx2x_init_sb()
5919 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_sb()
5922 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5925 sb_data_e2.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
5937 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp); in bnx2x_init_sb()
5940 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp); in bnx2x_init_sb()
5958 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size); in bnx2x_init_sb()
5961 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id, in bnx2x_update_coalesce_sb() argument
5964 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS, in bnx2x_update_coalesce_sb()
5966 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
5969 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
5972 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, in bnx2x_update_coalesce_sb()
5977 static void bnx2x_init_def_sb(struct bnx2x *bp) in bnx2x_init_def_sb() argument
5979 struct host_sp_status_block *def_sb = bp->def_status_blk; in bnx2x_init_def_sb()
5980 dma_addr_t mapping = bp->def_status_blk_mapping; in bnx2x_init_def_sb()
5983 int port = BP_PORT(bp); in bnx2x_init_def_sb()
5984 int func = BP_FUNC(bp); in bnx2x_init_def_sb()
5991 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_def_sb()
5995 igu_sp_sb_index = bp->igu_dsb_id; in bnx2x_init_def_sb()
6004 bp->attn_state = 0; in bnx2x_init_def_sb()
6014 bp->attn_group[index].sig[sindex] = in bnx2x_init_def_sb()
6015 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index); in bnx2x_init_def_sb()
6017 if (!CHIP_IS_E1x(bp)) in bnx2x_init_def_sb()
6023 bp->attn_group[index].sig[4] = REG_RD(bp, in bnx2x_init_def_sb()
6026 bp->attn_group[index].sig[4] = 0; in bnx2x_init_def_sb()
6029 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_def_sb()
6033 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
6034 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
6035 } else if (!CHIP_IS_E1x(bp)) { in bnx2x_init_def_sb()
6036 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
6037 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
6043 bnx2x_zero_sp_sb(bp); in bnx2x_init_def_sb()
6052 sp_sb_data.p_func.vnic_id = BP_VN(bp); in bnx2x_init_def_sb()
6055 bnx2x_wr_sp_sb_data(bp, &sp_sb_data); in bnx2x_init_def_sb()
6057 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); in bnx2x_init_def_sb()
6060 void bnx2x_update_coalesce(struct bnx2x *bp) in bnx2x_update_coalesce() argument
6064 for_each_eth_queue(bp, i) in bnx2x_update_coalesce()
6065 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id, in bnx2x_update_coalesce()
6066 bp->tx_ticks, bp->rx_ticks); in bnx2x_update_coalesce()
6069 static void bnx2x_init_sp_ring(struct bnx2x *bp) in bnx2x_init_sp_ring() argument
6071 spin_lock_init(&bp->spq_lock); in bnx2x_init_sp_ring()
6072 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING); in bnx2x_init_sp_ring()
6074 bp->spq_prod_idx = 0; in bnx2x_init_sp_ring()
6075 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX; in bnx2x_init_sp_ring()
6076 bp->spq_prod_bd = bp->spq; in bnx2x_init_sp_ring()
6077 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT; in bnx2x_init_sp_ring()
6080 static void bnx2x_init_eq_ring(struct bnx2x *bp) in bnx2x_init_eq_ring() argument
6085 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1]; in bnx2x_init_eq_ring()
6088 cpu_to_le32(U64_HI(bp->eq_mapping + in bnx2x_init_eq_ring()
6091 cpu_to_le32(U64_LO(bp->eq_mapping + in bnx2x_init_eq_ring()
6094 bp->eq_cons = 0; in bnx2x_init_eq_ring()
6095 bp->eq_prod = NUM_EQ_DESC; in bnx2x_init_eq_ring()
6096 bp->eq_cons_sb = BNX2X_EQ_INDEX; in bnx2x_init_eq_ring()
6098 atomic_set(&bp->eq_spq_left, in bnx2x_init_eq_ring()
6103 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, in bnx2x_set_q_rx_mode() argument
6117 ramrod_param.rx_mode_obj = &bp->rx_mode_obj; in bnx2x_set_q_rx_mode()
6118 ramrod_param.func_id = BP_FUNC(bp); in bnx2x_set_q_rx_mode()
6120 ramrod_param.pstate = &bp->sp_state; in bnx2x_set_q_rx_mode()
6123 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6124 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata); in bnx2x_set_q_rx_mode()
6126 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state); in bnx2x_set_q_rx_mode()
6134 rc = bnx2x_config_rx_mode(bp, &ramrod_param); in bnx2x_set_q_rx_mode()
6136 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode); in bnx2x_set_q_rx_mode()
6143 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode, in bnx2x_fill_accept_flags() argument
6194 if (IS_MF_SI(bp)) in bnx2x_fill_accept_flags()
6215 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp) in bnx2x_set_storm_rx_mode() argument
6221 if (!NO_FCOE(bp)) in bnx2x_set_storm_rx_mode()
6225 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags, in bnx2x_set_storm_rx_mode()
6233 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, in bnx2x_set_storm_rx_mode()
6238 static void bnx2x_init_internal_common(struct bnx2x *bp) in bnx2x_init_internal_common() argument
6245 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
6247 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_internal_common()
6248 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET, in bnx2x_init_internal_common()
6249 CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_internal_common()
6254 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code) in bnx2x_init_internal() argument
6259 bnx2x_init_internal_common(bp); in bnx2x_init_internal()
6279 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_igu_sb_id()
6284 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp); in bnx2x_fp_fw_sb_id()
6289 if (CHIP_IS_E1x(fp->bp)) in bnx2x_fp_cl_id()
6290 return BP_L_ID(fp->bp) + fp->index; in bnx2x_fp_cl_id()
6295 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx) in bnx2x_init_eth_fp() argument
6297 struct bnx2x_fastpath *fp = &bp->fp[fp_idx]; in bnx2x_init_eth_fp()
6323 bnx2x_init_txdata(bp, fp->txdata_ptr[cos], in bnx2x_init_eth_fp()
6324 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp), in bnx2x_init_eth_fp()
6325 FP_COS_TO_TXQ(fp, cos, bp), in bnx2x_init_eth_fp()
6331 if (IS_VF(bp)) in bnx2x_init_eth_fp()
6334 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false, in bnx2x_init_eth_fp()
6337 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids, in bnx2x_init_eth_fp()
6338 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_eth_fp()
6339 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_eth_fp()
6348 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_eth_fp()
6381 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp) in bnx2x_init_tx_rings_cnic() argument
6385 for_each_tx_queue_cnic(bp, i) in bnx2x_init_tx_rings_cnic()
6386 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]); in bnx2x_init_tx_rings_cnic()
6389 static void bnx2x_init_tx_rings(struct bnx2x *bp) in bnx2x_init_tx_rings() argument
6394 for_each_eth_queue(bp, i) in bnx2x_init_tx_rings()
6395 for_each_cos_in_tx_queue(&bp->fp[i], cos) in bnx2x_init_tx_rings()
6396 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]); in bnx2x_init_tx_rings()
6399 static void bnx2x_init_fcoe_fp(struct bnx2x *bp) in bnx2x_init_fcoe_fp() argument
6401 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); in bnx2x_init_fcoe_fp()
6404 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); in bnx2x_init_fcoe_fp()
6405 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, in bnx2x_init_fcoe_fp()
6407 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); in bnx2x_init_fcoe_fp()
6408 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; in bnx2x_init_fcoe_fp()
6409 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; in bnx2x_init_fcoe_fp()
6410 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; in bnx2x_init_fcoe_fp()
6411 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), in bnx2x_init_fcoe_fp()
6412 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, in bnx2x_init_fcoe_fp()
6418 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); in bnx2x_init_fcoe_fp()
6420 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = in bnx2x_init_fcoe_fp()
6430 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, in bnx2x_init_fcoe_fp()
6431 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), in bnx2x_init_fcoe_fp()
6432 bnx2x_sp_mapping(bp, q_rdata), q_type); in bnx2x_init_fcoe_fp()
6436 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, in bnx2x_init_fcoe_fp()
6440 void bnx2x_nic_init_cnic(struct bnx2x *bp) in bnx2x_nic_init_cnic() argument
6442 if (!NO_FCOE(bp)) in bnx2x_nic_init_cnic()
6443 bnx2x_init_fcoe_fp(bp); in bnx2x_nic_init_cnic()
6445 bnx2x_init_sb(bp, bp->cnic_sb_mapping, in bnx2x_nic_init_cnic()
6447 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp)); in bnx2x_nic_init_cnic()
6451 bnx2x_init_rx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6452 bnx2x_init_tx_rings_cnic(bp); in bnx2x_nic_init_cnic()
6459 void bnx2x_pre_irq_nic_init(struct bnx2x *bp) in bnx2x_pre_irq_nic_init() argument
6464 for_each_eth_queue(bp, i) in bnx2x_pre_irq_nic_init()
6465 bnx2x_init_eth_fp(bp, i); in bnx2x_pre_irq_nic_init()
6469 bnx2x_init_rx_rings(bp); in bnx2x_pre_irq_nic_init()
6470 bnx2x_init_tx_rings(bp); in bnx2x_pre_irq_nic_init()
6472 if (IS_PF(bp)) { in bnx2x_pre_irq_nic_init()
6474 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id, in bnx2x_pre_irq_nic_init()
6475 bp->common.shmem_base, in bnx2x_pre_irq_nic_init()
6476 bp->common.shmem2_base, BP_PORT(bp)); in bnx2x_pre_irq_nic_init()
6479 bnx2x_init_def_sb(bp); in bnx2x_pre_irq_nic_init()
6480 bnx2x_update_dsb_idx(bp); in bnx2x_pre_irq_nic_init()
6481 bnx2x_init_sp_ring(bp); in bnx2x_pre_irq_nic_init()
6483 bnx2x_memset_stats(bp); in bnx2x_pre_irq_nic_init()
6487 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code) in bnx2x_post_irq_nic_init() argument
6489 bnx2x_init_eq_ring(bp); in bnx2x_post_irq_nic_init()
6490 bnx2x_init_internal(bp, load_code); in bnx2x_post_irq_nic_init()
6491 bnx2x_pf_init(bp); in bnx2x_post_irq_nic_init()
6492 bnx2x_stats_init(bp); in bnx2x_post_irq_nic_init()
6498 bnx2x_int_enable(bp); in bnx2x_post_irq_nic_init()
6501 bnx2x_attn_int_deasserted0(bp, in bnx2x_post_irq_nic_init()
6502 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) & in bnx2x_post_irq_nic_init()
6507 static int bnx2x_gunzip_init(struct bnx2x *bp) in bnx2x_gunzip_init() argument
6509 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE, in bnx2x_gunzip_init()
6510 &bp->gunzip_mapping, GFP_KERNEL); in bnx2x_gunzip_init()
6511 if (bp->gunzip_buf == NULL) in bnx2x_gunzip_init()
6514 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL); in bnx2x_gunzip_init()
6515 if (bp->strm == NULL) in bnx2x_gunzip_init()
6518 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize()); in bnx2x_gunzip_init()
6519 if (bp->strm->workspace == NULL) in bnx2x_gunzip_init()
6525 kfree(bp->strm); in bnx2x_gunzip_init()
6526 bp->strm = NULL; in bnx2x_gunzip_init()
6529 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_init()
6530 bp->gunzip_mapping); in bnx2x_gunzip_init()
6531 bp->gunzip_buf = NULL; in bnx2x_gunzip_init()
6538 static void bnx2x_gunzip_end(struct bnx2x *bp) in bnx2x_gunzip_end() argument
6540 if (bp->strm) { in bnx2x_gunzip_end()
6541 vfree(bp->strm->workspace); in bnx2x_gunzip_end()
6542 kfree(bp->strm); in bnx2x_gunzip_end()
6543 bp->strm = NULL; in bnx2x_gunzip_end()
6546 if (bp->gunzip_buf) { in bnx2x_gunzip_end()
6547 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf, in bnx2x_gunzip_end()
6548 bp->gunzip_mapping); in bnx2x_gunzip_end()
6549 bp->gunzip_buf = NULL; in bnx2x_gunzip_end()
6553 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len) in bnx2x_gunzip() argument
6570 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n; in bnx2x_gunzip()
6571 bp->strm->avail_in = len - n; in bnx2x_gunzip()
6572 bp->strm->next_out = bp->gunzip_buf; in bnx2x_gunzip()
6573 bp->strm->avail_out = FW_BUF_SIZE; in bnx2x_gunzip()
6575 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS); in bnx2x_gunzip()
6579 rc = zlib_inflate(bp->strm, Z_FINISH); in bnx2x_gunzip()
6581 netdev_err(bp->dev, "Firmware decompression error: %s\n", in bnx2x_gunzip()
6582 bp->strm->msg); in bnx2x_gunzip()
6584 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out); in bnx2x_gunzip()
6585 if (bp->gunzip_outlen & 0x3) in bnx2x_gunzip()
6586 netdev_err(bp->dev, in bnx2x_gunzip()
6588 bp->gunzip_outlen); in bnx2x_gunzip()
6589 bp->gunzip_outlen >>= 2; in bnx2x_gunzip()
6591 zlib_inflateEnd(bp->strm); in bnx2x_gunzip()
6606 static void bnx2x_lb_pckt(struct bnx2x *bp) in bnx2x_lb_pckt() argument
6614 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6620 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); in bnx2x_lb_pckt()
6627 static int bnx2x_int_mem_test(struct bnx2x *bp) in bnx2x_int_mem_test() argument
6633 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_int_mem_test()
6635 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_int_mem_test()
6641 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6642 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6643 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6644 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6647 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6650 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6657 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6658 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6673 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6686 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6688 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6690 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6691 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6696 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6697 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6698 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6699 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6702 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6706 bnx2x_lb_pckt(bp); in bnx2x_int_mem_test()
6713 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_int_mem_test()
6714 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_int_mem_test()
6727 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6732 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6737 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS); in bnx2x_int_mem_test()
6743 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO); in bnx2x_int_mem_test()
6744 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY); in bnx2x_int_mem_test()
6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6753 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6755 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_int_mem_test()
6756 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_int_mem_test()
6757 if (!CNIC_SUPPORT(bp)) in bnx2x_int_mem_test()
6759 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
6762 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6763 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6764 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6765 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6772 static void bnx2x_enable_blocks_attention(struct bnx2x *bp) in bnx2x_enable_blocks_attention() argument
6776 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6777 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6778 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6780 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6781 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6782 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6789 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6790 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6791 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6792 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6793 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6794 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6797 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6798 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6799 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6802 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6803 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6804 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6805 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6812 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6815 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); in bnx2x_enable_blocks_attention()
6817 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6818 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6819 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6822 if (!CHIP_IS_E1x(bp)) in bnx2x_enable_blocks_attention()
6824 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6826 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6827 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6829 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6832 static void bnx2x_reset_common(struct bnx2x *bp) in bnx2x_reset_common() argument
6837 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
6840 if (CHIP_IS_E3(bp)) { in bnx2x_reset_common()
6845 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); in bnx2x_reset_common()
6848 static void bnx2x_setup_dmae(struct bnx2x *bp) in bnx2x_setup_dmae() argument
6850 bp->dmae_ready = 0; in bnx2x_setup_dmae()
6851 spin_lock_init(&bp->dmae_lock); in bnx2x_setup_dmae()
6854 static void bnx2x_init_pxp(struct bnx2x *bp) in bnx2x_init_pxp() argument
6859 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl); in bnx2x_init_pxp()
6862 if (bp->mrrs == -1) in bnx2x_init_pxp()
6865 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs); in bnx2x_init_pxp()
6866 r_order = bp->mrrs; in bnx2x_init_pxp()
6869 bnx2x_init_pxp_arb(bp, r_order, w_order); in bnx2x_init_pxp()
6872 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp) in bnx2x_setup_fan_failure_detection() argument
6878 if (BP_NOMCP(bp)) in bnx2x_setup_fan_failure_detection()
6882 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) & in bnx2x_setup_fan_failure_detection()
6897 bp, in bnx2x_setup_fan_failure_detection()
6898 bp->common.shmem_base, in bnx2x_setup_fan_failure_detection()
6899 bp->common.shmem2_base, in bnx2x_setup_fan_failure_detection()
6909 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); in bnx2x_setup_fan_failure_detection()
6912 val = REG_RD(bp, MISC_REG_SPIO_INT); in bnx2x_setup_fan_failure_detection()
6914 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
6917 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_setup_fan_failure_detection()
6919 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
6922 void bnx2x_pf_disable(struct bnx2x *bp) in bnx2x_pf_disable() argument
6924 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION); in bnx2x_pf_disable()
6927 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
6928 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6929 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
6932 static void bnx2x__common_init_phy(struct bnx2x *bp) in bnx2x__common_init_phy() argument
6936 if (SHMEM2_RD(bp, size) > in bnx2x__common_init_phy()
6937 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x__common_init_phy()
6939 shmem_base[0] = bp->common.shmem_base; in bnx2x__common_init_phy()
6940 shmem2_base[0] = bp->common.shmem2_base; in bnx2x__common_init_phy()
6941 if (!CHIP_IS_E1x(bp)) { in bnx2x__common_init_phy()
6943 SHMEM2_RD(bp, other_shmem_base_addr); in bnx2x__common_init_phy()
6945 SHMEM2_RD(bp, other_shmem2_base_addr); in bnx2x__common_init_phy()
6947 bnx2x_acquire_phy_lock(bp); in bnx2x__common_init_phy()
6948 bnx2x_common_init_phy(bp, shmem_base, shmem2_base, in bnx2x__common_init_phy()
6949 bp->common.chip_id); in bnx2x__common_init_phy()
6950 bnx2x_release_phy_lock(bp); in bnx2x__common_init_phy()
6953 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val) in bnx2x_config_endianity() argument
6955 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); in bnx2x_config_endianity()
6956 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); in bnx2x_config_endianity()
6957 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); in bnx2x_config_endianity()
6958 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); in bnx2x_config_endianity()
6959 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); in bnx2x_config_endianity()
6962 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
6964 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); in bnx2x_config_endianity()
6965 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); in bnx2x_config_endianity()
6966 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); in bnx2x_config_endianity()
6967 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); in bnx2x_config_endianity()
6970 static void bnx2x_set_endianity(struct bnx2x *bp) in bnx2x_set_endianity() argument
6973 bnx2x_config_endianity(bp, 1); in bnx2x_set_endianity()
6975 bnx2x_config_endianity(bp, 0); in bnx2x_set_endianity()
6979 static void bnx2x_reset_endianity(struct bnx2x *bp) in bnx2x_reset_endianity() argument
6981 bnx2x_config_endianity(bp, 0); in bnx2x_reset_endianity()
6989 static int bnx2x_init_hw_common(struct bnx2x *bp) in bnx2x_init_hw_common() argument
6993 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
6999 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7001 bnx2x_reset_common(bp); in bnx2x_init_hw_common()
7002 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7005 if (CHIP_IS_E3(bp)) { in bnx2x_init_hw_common()
7009 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); in bnx2x_init_hw_common()
7011 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_init_hw_common()
7013 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON); in bnx2x_init_hw_common()
7015 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7025 for (abs_func_id = BP_PATH(bp); in bnx2x_init_hw_common()
7027 if (abs_func_id == BP_ABS_FUNC(bp)) { in bnx2x_init_hw_common()
7028 REG_WR(bp, in bnx2x_init_hw_common()
7034 bnx2x_pretend_func(bp, abs_func_id); in bnx2x_init_hw_common()
7036 bnx2x_pf_disable(bp); in bnx2x_init_hw_common()
7037 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7041 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON); in bnx2x_init_hw_common()
7042 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7045 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7048 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON); in bnx2x_init_hw_common()
7049 bnx2x_init_pxp(bp); in bnx2x_init_hw_common()
7050 bnx2x_set_endianity(bp); in bnx2x_init_hw_common()
7051 bnx2x_ilt_init_page_size(bp, INITOP_SET); in bnx2x_init_hw_common()
7053 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7054 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7059 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE); in bnx2x_init_hw_common()
7064 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE); in bnx2x_init_hw_common()
7075 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7159 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6)); in bnx2x_init_hw_common()
7160 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR); in bnx2x_init_hw_common()
7161 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); in bnx2x_init_hw_common()
7163 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7164 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7165 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
7168 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7169 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7171 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7172 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 : in bnx2x_init_hw_common()
7173 (CHIP_REV_IS_FPGA(bp) ? 400 : 0); in bnx2x_init_hw_common()
7174 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON); in bnx2x_init_hw_common()
7176 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON); in bnx2x_init_hw_common()
7181 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE); in bnx2x_init_hw_common()
7190 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON); in bnx2x_init_hw_common()
7192 bnx2x_iov_init_dmae(bp); in bnx2x_init_hw_common()
7195 bp->dmae_ready = 1; in bnx2x_init_hw_common()
7196 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1); in bnx2x_init_hw_common()
7198 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON); in bnx2x_init_hw_common()
7200 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON); in bnx2x_init_hw_common()
7202 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON); in bnx2x_init_hw_common()
7204 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON); in bnx2x_init_hw_common()
7206 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7207 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7208 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7209 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3); in bnx2x_init_hw_common()
7211 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON); in bnx2x_init_hw_common()
7214 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_common()
7217 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
7218 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7220 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_common()
7221 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON); in bnx2x_init_hw_common()
7223 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON); in bnx2x_init_hw_common()
7225 if (!CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7227 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7229 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON); in bnx2x_init_hw_common()
7231 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON); in bnx2x_init_hw_common()
7232 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7234 if (!CHIP_IS_E1(bp)) in bnx2x_init_hw_common()
7235 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7237 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_common()
7238 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7242 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7243 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7244 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7245 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7246 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7251 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7252 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7256 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7257 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7258 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON); in bnx2x_init_hw_common()
7259 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON); in bnx2x_init_hw_common()
7261 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7263 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7266 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7273 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7274 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON); in bnx2x_init_hw_common()
7275 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7276 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON); in bnx2x_init_hw_common()
7279 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
7281 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
7284 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON); in bnx2x_init_hw_common()
7285 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON); in bnx2x_init_hw_common()
7286 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON); in bnx2x_init_hw_common()
7288 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7289 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_common()
7293 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7294 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7295 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7296 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7297 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7299 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7300 bp->path_has_ovlan ? 7 : 6); in bnx2x_init_hw_common()
7304 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
7306 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON); in bnx2x_init_hw_common()
7308 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_common()
7309 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7310 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7311 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7312 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7313 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7314 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7315 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7316 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7317 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7318 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7320 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7324 dev_alert(&bp->pdev->dev, in bnx2x_init_hw_common()
7328 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON); in bnx2x_init_hw_common()
7330 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
7332 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON); in bnx2x_init_hw_common()
7333 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7335 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7338 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7340 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON); in bnx2x_init_hw_common()
7342 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp)) in bnx2x_init_hw_common()
7343 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7345 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON); in bnx2x_init_hw_common()
7346 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON); in bnx2x_init_hw_common()
7349 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7350 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7352 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_common()
7353 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
7356 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
7360 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
7366 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON); in bnx2x_init_hw_common()
7367 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7369 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_common()
7370 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
7372 if (CHIP_IS_E1H(bp)) in bnx2x_init_hw_common()
7374 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
7376 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_init_hw_common()
7380 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7385 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7390 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10); in bnx2x_init_hw_common()
7395 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7397 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_common()
7400 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2); in bnx2x_init_hw_common()
7401 val = *bnx2x_sp(bp, wb_data[0]); in bnx2x_init_hw_common()
7404 if ((val == 0) && bnx2x_int_mem_test(bp)) { in bnx2x_init_hw_common()
7410 bnx2x_setup_fan_failure_detection(bp); in bnx2x_init_hw_common()
7413 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0); in bnx2x_init_hw_common()
7415 bnx2x_enable_blocks_attention(bp); in bnx2x_init_hw_common()
7416 bnx2x_enable_blocks_parity(bp); in bnx2x_init_hw_common()
7418 if (!BP_NOMCP(bp)) { in bnx2x_init_hw_common()
7419 if (CHIP_IS_E1x(bp)) in bnx2x_init_hw_common()
7420 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common()
7432 static int bnx2x_init_hw_common_chip(struct bnx2x *bp) in bnx2x_init_hw_common_chip() argument
7434 int rc = bnx2x_init_hw_common(bp); in bnx2x_init_hw_common_chip()
7440 if (!BP_NOMCP(bp)) in bnx2x_init_hw_common_chip()
7441 bnx2x__common_init_phy(bp); in bnx2x_init_hw_common_chip()
7446 static int bnx2x_init_hw_port(struct bnx2x *bp) in bnx2x_init_hw_port() argument
7448 int port = BP_PORT(bp); in bnx2x_init_hw_port()
7455 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7457 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_port()
7458 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_port()
7459 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_port()
7466 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_port()
7467 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
7469 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_port()
7470 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_port()
7471 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_port()
7472 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_port()
7474 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_port()
7475 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_port()
7476 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_port()
7477 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_port()
7480 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET); in bnx2x_init_hw_port()
7482 if (CNIC_SUPPORT(bp)) { in bnx2x_init_hw_port()
7483 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_port()
7484 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
7485 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
7488 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_port()
7490 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_port()
7492 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) { in bnx2x_init_hw_port()
7494 if (IS_MF(bp)) in bnx2x_init_hw_port()
7495 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246); in bnx2x_init_hw_port()
7496 else if (bp->dev->mtu > 4096) { in bnx2x_init_hw_port()
7497 if (bp->flags & ONE_PORT_FLAG) in bnx2x_init_hw_port()
7500 val = bp->dev->mtu; in bnx2x_init_hw_port()
7506 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160); in bnx2x_init_hw_port()
7508 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
7509 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
7512 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_port()
7513 REG_WR(bp, (BP_PORT(bp) ? in bnx2x_init_hw_port()
7517 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_port()
7518 if (CHIP_IS_E3B0(bp)) { in bnx2x_init_hw_port()
7519 if (IS_MF_AFEX(bp)) { in bnx2x_init_hw_port()
7521 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7524 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7527 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7535 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7538 (bp->path_has_ovlan ? 7 : 6)); in bnx2x_init_hw_port()
7542 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_port()
7543 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_port()
7544 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_port()
7545 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_port()
7547 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_port()
7548 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_port()
7549 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_port()
7550 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_port()
7552 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_port()
7553 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_port()
7555 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_port()
7557 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7559 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7562 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
7564 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7567 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
7569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7572 if (CNIC_SUPPORT(bp)) in bnx2x_init_hw_port()
7573 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_port()
7575 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_port()
7576 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_port()
7578 if (CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7579 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7580 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7582 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_port()
7584 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_port()
7586 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_port()
7591 val = IS_MF(bp) ? 0xF7 : 0x7; in bnx2x_init_hw_port()
7593 val |= CHIP_IS_E1(bp) ? 0 : 0x10; in bnx2x_init_hw_port()
7594 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
7598 REG_WR(bp, reg, in bnx2x_init_hw_port()
7599 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7603 REG_WR(bp, reg, in bnx2x_init_hw_port()
7604 REG_RD(bp, reg) & in bnx2x_init_hw_port()
7607 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_port()
7609 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7613 if (IS_MF_AFEX(bp)) in bnx2x_init_hw_port()
7614 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7618 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7621 IS_MF_SD(bp) ? 7 : 6); in bnx2x_init_hw_port()
7623 if (CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7624 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7626 NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_port()
7628 if (!CHIP_IS_E3(bp)) in bnx2x_init_hw_port()
7629 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
7631 if (!CHIP_IS_E1(bp)) { in bnx2x_init_hw_port()
7633 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
7634 (IS_MF_SD(bp) ? 0x1 : 0x2)); in bnx2x_init_hw_port()
7636 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_port()
7638 switch (bp->mf_mode) { in bnx2x_init_hw_port()
7648 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
7652 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7653 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7654 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
7659 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN); in bnx2x_init_hw_port()
7663 val = REG_RD(bp, reg_addr); in bnx2x_init_hw_port()
7665 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
7671 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr) in bnx2x_ilt_wr() argument
7676 if (CHIP_IS_E1(bp)) in bnx2x_ilt_wr()
7683 REG_WR_DMAE(bp, reg, wb_write, 2); in bnx2x_ilt_wr()
7686 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf) in bnx2x_igu_clear_sb_gen() argument
7697 if (CHIP_INT_MODE_IS_BC(bp)) in bnx2x_igu_clear_sb_gen()
7711 REG_WR(bp, igu_addr_data, data); in bnx2x_igu_clear_sb_gen()
7716 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_igu_clear_sb_gen()
7721 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) in bnx2x_igu_clear_sb_gen()
7724 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { in bnx2x_igu_clear_sb_gen()
7731 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id) in bnx2x_igu_clear_sb() argument
7733 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/); in bnx2x_igu_clear_sb()
7736 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func) in bnx2x_clear_func_ilt() argument
7740 bnx2x_ilt_wr(bp, i, 0); in bnx2x_clear_func_ilt()
7743 static void bnx2x_init_searcher(struct bnx2x *bp) in bnx2x_init_searcher() argument
7745 int port = BP_PORT(bp); in bnx2x_init_searcher()
7746 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM); in bnx2x_init_searcher()
7748 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_searcher()
7751 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend) in bnx2x_func_switch_update() argument
7762 func_params.f_obj = &bp->func_obj; in bnx2x_func_switch_update()
7772 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_switch_update()
7777 static int bnx2x_reset_nic_mode(struct bnx2x *bp) in bnx2x_reset_nic_mode() argument
7779 int rc, i, port = BP_PORT(bp); in bnx2x_reset_nic_mode()
7783 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7784 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_reset_nic_mode()
7786 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7788 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7791 mac_en[i] = REG_RD(bp, port ? in bnx2x_reset_nic_mode()
7796 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7803 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7811 rc = bnx2x_func_switch_update(bp, 1); in bnx2x_reset_nic_mode()
7818 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7821 if (bp->mf_mode == SINGLE_FUNCTION) { in bnx2x_reset_nic_mode()
7822 bnx2x_set_rx_filter(&bp->link_params, 1); in bnx2x_reset_nic_mode()
7824 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7827 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7835 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7839 rc = bnx2x_func_switch_update(bp, 0); in bnx2x_reset_nic_mode()
7849 int bnx2x_init_hw_func_cnic(struct bnx2x *bp) in bnx2x_init_hw_func_cnic() argument
7853 bnx2x_ilt_init_op_cnic(bp, INITOP_SET); in bnx2x_init_hw_func_cnic()
7855 if (CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func_cnic()
7857 bnx2x_init_searcher(bp); in bnx2x_init_hw_func_cnic()
7860 rc = bnx2x_reset_nic_mode(bp); in bnx2x_init_hw_func_cnic()
7876 static void bnx2x_clean_pglue_errors(struct bnx2x *bp) in bnx2x_clean_pglue_errors() argument
7878 if (!CHIP_IS_E1x(bp)) in bnx2x_clean_pglue_errors()
7879 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, in bnx2x_clean_pglue_errors()
7880 1 << BP_ABS_FUNC(bp)); in bnx2x_clean_pglue_errors()
7883 static int bnx2x_init_hw_func(struct bnx2x *bp) in bnx2x_init_hw_func() argument
7885 int port = BP_PORT(bp); in bnx2x_init_hw_func()
7886 int func = BP_FUNC(bp); in bnx2x_init_hw_func()
7888 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7897 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7898 rc = bnx2x_pf_flr_clnup(bp); in bnx2x_init_hw_func()
7900 bnx2x_fw_dump(bp); in bnx2x_init_hw_func()
7906 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
7908 val = REG_RD(bp, addr); in bnx2x_init_hw_func()
7910 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
7913 bnx2x_init_block(bp, BLOCK_PXP, init_phase); in bnx2x_init_hw_func()
7914 bnx2x_init_block(bp, BLOCK_PXP2, init_phase); in bnx2x_init_hw_func()
7916 ilt = BP_ILT(bp); in bnx2x_init_hw_func()
7919 if (IS_SRIOV(bp)) in bnx2x_init_hw_func()
7921 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start); in bnx2x_init_hw_func()
7927 for (i = 0; i < L2_ILT_LINES(bp); i++) { in bnx2x_init_hw_func()
7928 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt; in bnx2x_init_hw_func()
7930 bp->context[i].cxt_mapping; in bnx2x_init_hw_func()
7931 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size; in bnx2x_init_hw_func()
7934 bnx2x_ilt_init_op(bp, INITOP_SET); in bnx2x_init_hw_func()
7936 if (!CONFIGURE_NIC_MODE(bp)) { in bnx2x_init_hw_func()
7937 bnx2x_init_searcher(bp); in bnx2x_init_hw_func()
7938 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
7942 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
7946 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7952 if (!(bp->flags & USING_MSIX_FLAG)) in bnx2x_init_hw_func()
7966 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
7968 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
7971 bp->dmae_ready = 1; in bnx2x_init_hw_func()
7973 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase); in bnx2x_init_hw_func()
7975 bnx2x_clean_pglue_errors(bp); in bnx2x_init_hw_func()
7977 bnx2x_init_block(bp, BLOCK_ATC, init_phase); in bnx2x_init_hw_func()
7978 bnx2x_init_block(bp, BLOCK_DMAE, init_phase); in bnx2x_init_hw_func()
7979 bnx2x_init_block(bp, BLOCK_NIG, init_phase); in bnx2x_init_hw_func()
7980 bnx2x_init_block(bp, BLOCK_SRC, init_phase); in bnx2x_init_hw_func()
7981 bnx2x_init_block(bp, BLOCK_MISC, init_phase); in bnx2x_init_hw_func()
7982 bnx2x_init_block(bp, BLOCK_TCM, init_phase); in bnx2x_init_hw_func()
7983 bnx2x_init_block(bp, BLOCK_UCM, init_phase); in bnx2x_init_hw_func()
7984 bnx2x_init_block(bp, BLOCK_CCM, init_phase); in bnx2x_init_hw_func()
7985 bnx2x_init_block(bp, BLOCK_XCM, init_phase); in bnx2x_init_hw_func()
7986 bnx2x_init_block(bp, BLOCK_TSEM, init_phase); in bnx2x_init_hw_func()
7987 bnx2x_init_block(bp, BLOCK_USEM, init_phase); in bnx2x_init_hw_func()
7988 bnx2x_init_block(bp, BLOCK_CSEM, init_phase); in bnx2x_init_hw_func()
7989 bnx2x_init_block(bp, BLOCK_XSEM, init_phase); in bnx2x_init_hw_func()
7991 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
7992 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
7994 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
7995 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7996 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7997 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
7998 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8000 bnx2x_init_block(bp, BLOCK_QM, init_phase); in bnx2x_init_hw_func()
8002 bnx2x_init_block(bp, BLOCK_TM, init_phase); in bnx2x_init_hw_func()
8003 bnx2x_init_block(bp, BLOCK_DORQ, init_phase); in bnx2x_init_hw_func()
8004 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ in bnx2x_init_hw_func()
8006 bnx2x_iov_init_dq(bp); in bnx2x_init_hw_func()
8008 bnx2x_init_block(bp, BLOCK_BRB1, init_phase); in bnx2x_init_hw_func()
8009 bnx2x_init_block(bp, BLOCK_PRS, init_phase); in bnx2x_init_hw_func()
8010 bnx2x_init_block(bp, BLOCK_TSDM, init_phase); in bnx2x_init_hw_func()
8011 bnx2x_init_block(bp, BLOCK_CSDM, init_phase); in bnx2x_init_hw_func()
8012 bnx2x_init_block(bp, BLOCK_USDM, init_phase); in bnx2x_init_hw_func()
8013 bnx2x_init_block(bp, BLOCK_XSDM, init_phase); in bnx2x_init_hw_func()
8014 bnx2x_init_block(bp, BLOCK_UPB, init_phase); in bnx2x_init_hw_func()
8015 bnx2x_init_block(bp, BLOCK_XPB, init_phase); in bnx2x_init_hw_func()
8016 bnx2x_init_block(bp, BLOCK_PBF, init_phase); in bnx2x_init_hw_func()
8017 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8018 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8020 bnx2x_init_block(bp, BLOCK_CDU, init_phase); in bnx2x_init_hw_func()
8022 bnx2x_init_block(bp, BLOCK_CFC, init_phase); in bnx2x_init_hw_func()
8024 if (!CHIP_IS_E1x(bp)) in bnx2x_init_hw_func()
8025 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
8027 if (IS_MF(bp)) { in bnx2x_init_hw_func()
8028 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) { in bnx2x_init_hw_func()
8029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_init_hw_func()
8030 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, in bnx2x_init_hw_func()
8031 bp->mf_ov); in bnx2x_init_hw_func()
8035 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase); in bnx2x_init_hw_func()
8038 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_init_hw_func()
8039 if (CHIP_IS_E1H(bp)) { in bnx2x_init_hw_func()
8040 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8042 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8043 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8045 bnx2x_init_block(bp, BLOCK_HC, init_phase); in bnx2x_init_hw_func()
8050 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8052 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8053 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8054 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8057 bnx2x_init_block(bp, BLOCK_IGU, init_phase); in bnx2x_init_hw_func()
8059 if (!CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8082 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8084 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) { in bnx2x_init_hw_func()
8085 prod_offset = (bp->igu_base_sb + sb_idx) * in bnx2x_init_hw_func()
8091 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8094 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx, in bnx2x_init_hw_func()
8096 bnx2x_igu_clear_sb(bp, in bnx2x_init_hw_func()
8097 bp->igu_base_sb + sb_idx); in bnx2x_init_hw_func()
8101 num_segs = CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8104 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_init_hw_func()
8105 dsb_idx = BP_FUNC(bp); in bnx2x_init_hw_func()
8107 dsb_idx = BP_VN(bp); in bnx2x_init_hw_func()
8109 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? in bnx2x_init_hw_func()
8121 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8124 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_init_hw_func()
8125 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8127 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8129 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8131 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8133 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8136 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8138 bnx2x_ack_sb(bp, bp->igu_dsb_id, in bnx2x_init_hw_func()
8141 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id); in bnx2x_init_hw_func()
8145 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8146 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8147 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8148 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8149 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8150 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8155 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8156 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8158 if (CHIP_IS_E1x(bp)) { in bnx2x_init_hw_func()
8161 BP_PORT(bp) * (main_mem_size * 4); in bnx2x_init_hw_func()
8165 val = REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8175 bnx2x_read_dmae(bp, i, main_mem_width / 4); in bnx2x_init_hw_func()
8176 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), in bnx2x_init_hw_func()
8180 REG_RD(bp, main_mem_prty_clr); in bnx2x_init_hw_func()
8185 REG_WR8(bp, BAR_USTRORM_INTMEM + in bnx2x_init_hw_func()
8186 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8187 REG_WR8(bp, BAR_TSTRORM_INTMEM + in bnx2x_init_hw_func()
8188 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8189 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_init_hw_func()
8190 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8191 REG_WR8(bp, BAR_XSTRORM_INTMEM + in bnx2x_init_hw_func()
8192 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1); in bnx2x_init_hw_func()
8195 bnx2x_phy_probe(&bp->link_params); in bnx2x_init_hw_func()
8200 void bnx2x_free_mem_cnic(struct bnx2x *bp) in bnx2x_free_mem_cnic() argument
8202 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE); in bnx2x_free_mem_cnic()
8204 if (!CHIP_IS_E1x(bp)) in bnx2x_free_mem_cnic()
8205 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8208 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping, in bnx2x_free_mem_cnic()
8211 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem_cnic()
8214 void bnx2x_free_mem(struct bnx2x *bp) in bnx2x_free_mem() argument
8218 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping, in bnx2x_free_mem()
8219 bp->fw_stats_data_sz + bp->fw_stats_req_sz); in bnx2x_free_mem()
8221 if (IS_VF(bp)) in bnx2x_free_mem()
8224 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping, in bnx2x_free_mem()
8227 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping, in bnx2x_free_mem()
8230 for (i = 0; i < L2_ILT_LINES(bp); i++) in bnx2x_free_mem()
8231 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping, in bnx2x_free_mem()
8232 bp->context[i].size); in bnx2x_free_mem()
8233 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE); in bnx2x_free_mem()
8235 BNX2X_FREE(bp->ilt->lines); in bnx2x_free_mem()
8237 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_free_mem()
8239 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping, in bnx2x_free_mem()
8242 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ); in bnx2x_free_mem()
8244 bnx2x_iov_free_mem(bp); in bnx2x_free_mem()
8247 int bnx2x_alloc_mem_cnic(struct bnx2x *bp) in bnx2x_alloc_mem_cnic() argument
8249 if (!CHIP_IS_E1x(bp)) { in bnx2x_alloc_mem_cnic()
8251 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8253 if (!bp->cnic_sb.e2_sb) in bnx2x_alloc_mem_cnic()
8256 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping, in bnx2x_alloc_mem_cnic()
8258 if (!bp->cnic_sb.e1x_sb) in bnx2x_alloc_mem_cnic()
8262 if (CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem_cnic()
8264 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem_cnic()
8265 if (!bp->t2) in bnx2x_alloc_mem_cnic()
8270 bp->cnic_eth_dev.addr_drv_info_to_mcp = in bnx2x_alloc_mem_cnic()
8271 &bp->slowpath->drv_info_to_mcp; in bnx2x_alloc_mem_cnic()
8273 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem_cnic()
8279 bnx2x_free_mem_cnic(bp); in bnx2x_alloc_mem_cnic()
8284 int bnx2x_alloc_mem(struct bnx2x *bp) in bnx2x_alloc_mem() argument
8288 if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) { in bnx2x_alloc_mem()
8290 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ); in bnx2x_alloc_mem()
8291 if (!bp->t2) in bnx2x_alloc_mem()
8295 bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping, in bnx2x_alloc_mem()
8297 if (!bp->def_status_blk) in bnx2x_alloc_mem()
8300 bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping, in bnx2x_alloc_mem()
8302 if (!bp->slowpath) in bnx2x_alloc_mem()
8318 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp); in bnx2x_alloc_mem()
8321 bp->context[i].size = min(CDU_ILT_PAGE_SZ, in bnx2x_alloc_mem()
8323 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping, in bnx2x_alloc_mem()
8324 bp->context[i].size); in bnx2x_alloc_mem()
8325 if (!bp->context[i].vcxt) in bnx2x_alloc_mem()
8327 allocated += bp->context[i].size; in bnx2x_alloc_mem()
8329 bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line), in bnx2x_alloc_mem()
8331 if (!bp->ilt->lines) in bnx2x_alloc_mem()
8334 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC)) in bnx2x_alloc_mem()
8337 if (bnx2x_iov_alloc_mem(bp)) in bnx2x_alloc_mem()
8341 bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE); in bnx2x_alloc_mem()
8342 if (!bp->spq) in bnx2x_alloc_mem()
8346 bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping, in bnx2x_alloc_mem()
8348 if (!bp->eq_ring) in bnx2x_alloc_mem()
8354 bnx2x_free_mem(bp); in bnx2x_alloc_mem()
8363 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, in bnx2x_set_mac_one() argument
8389 rc = bnx2x_config_vlan_mac(bp, &ramrod_param); in bnx2x_set_mac_one()
8401 int bnx2x_del_all_macs(struct bnx2x *bp, in bnx2x_del_all_macs() argument
8415 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags); in bnx2x_del_all_macs()
8422 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set) in bnx2x_set_eth_mac() argument
8424 if (IS_PF(bp)) { in bnx2x_set_eth_mac()
8429 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8430 &bp->sp_objs->mac_obj, set, in bnx2x_set_eth_mac()
8433 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr, in bnx2x_set_eth_mac()
8434 bp->fp->index, true); in bnx2x_set_eth_mac()
8438 int bnx2x_setup_leading(struct bnx2x *bp) in bnx2x_setup_leading() argument
8440 if (IS_PF(bp)) in bnx2x_setup_leading()
8441 return bnx2x_setup_queue(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8443 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true); in bnx2x_setup_leading()
8453 int bnx2x_set_int_mode(struct bnx2x *bp) in bnx2x_set_int_mode() argument
8457 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) { in bnx2x_set_int_mode()
8465 rc = bnx2x_enable_msix(bp); in bnx2x_set_int_mode()
8472 if (rc && IS_VF(bp)) in bnx2x_set_int_mode()
8477 bp->num_queues, in bnx2x_set_int_mode()
8478 1 + bp->num_cnic_queues); in bnx2x_set_int_mode()
8482 bnx2x_enable_msi(bp); in bnx2x_set_int_mode()
8486 bp->num_ethernet_queues = 1; in bnx2x_set_int_mode()
8487 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues; in bnx2x_set_int_mode()
8498 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp) in bnx2x_cid_ilt_lines() argument
8500 if (IS_SRIOV(bp)) in bnx2x_cid_ilt_lines()
8502 return L2_ILT_LINES(bp); in bnx2x_cid_ilt_lines()
8505 void bnx2x_ilt_set_info(struct bnx2x *bp) in bnx2x_ilt_set_info() argument
8508 struct bnx2x_ilt *ilt = BP_ILT(bp); in bnx2x_ilt_set_info()
8511 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp)); in bnx2x_ilt_set_info()
8520 line += bnx2x_cid_ilt_lines(bp); in bnx2x_ilt_set_info()
8522 if (CNIC_SUPPORT(bp)) in bnx2x_ilt_set_info()
8534 if (QM_INIT(bp->qm_cid_count)) { in bnx2x_ilt_set_info()
8542 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4, in bnx2x_ilt_set_info()
8556 if (CNIC_SUPPORT(bp)) { in bnx2x_ilt_set_info()
8606 static void bnx2x_pf_q_prep_init(struct bnx2x *bp, in bnx2x_pf_q_prep_init() argument
8624 init_params->rx.hc_rate = bp->rx_ticks ? in bnx2x_pf_q_prep_init()
8625 (1000000 / bp->rx_ticks) : 0; in bnx2x_pf_q_prep_init()
8626 init_params->tx.hc_rate = bp->tx_ticks ? in bnx2x_pf_q_prep_init()
8627 (1000000 / bp->tx_ticks) : 0; in bnx2x_pf_q_prep_init()
8653 &bp->context[cxt_index].vcxt[cxt_offset].eth; in bnx2x_pf_q_prep_init()
8657 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_tx_only() argument
8668 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false); in bnx2x_setup_tx_only()
8674 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index); in bnx2x_setup_tx_only()
8677 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index); in bnx2x_setup_tx_only()
8686 return bnx2x_queue_state_change(bp, q_params); in bnx2x_setup_tx_only()
8700 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, in bnx2x_setup_queue() argument
8715 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, in bnx2x_setup_queue()
8718 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_setup_queue()
8723 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init); in bnx2x_setup_queue()
8729 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8741 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading); in bnx2x_setup_queue()
8744 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params, in bnx2x_setup_queue()
8747 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params, in bnx2x_setup_queue()
8750 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params, in bnx2x_setup_queue()
8757 bp->fcoe_init = true; in bnx2x_setup_queue()
8760 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_setup_queue()
8772 rc = bnx2x_setup_tx_only(bp, fp, &q_params, in bnx2x_setup_queue()
8784 static int bnx2x_stop_queue(struct bnx2x *bp, int index) in bnx2x_stop_queue() argument
8786 struct bnx2x_fastpath *fp = &bp->fp[index]; in bnx2x_stop_queue()
8793 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_stop_queue()
8814 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8823 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8830 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8839 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8847 return bnx2x_queue_state_change(bp, &q_params); in bnx2x_stop_queue()
8850 static void bnx2x_reset_func(struct bnx2x *bp) in bnx2x_reset_func() argument
8852 int port = BP_PORT(bp); in bnx2x_reset_func()
8853 int func = BP_FUNC(bp); in bnx2x_reset_func()
8857 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8858 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8859 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8860 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); in bnx2x_reset_func()
8863 for_each_eth_queue(bp, i) { in bnx2x_reset_func()
8864 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_reset_func()
8865 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8870 if (CNIC_LOADED(bp)) in bnx2x_reset_func()
8872 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8874 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED); in bnx2x_reset_func()
8877 REG_WR8(bp, BAR_CSTRORM_INTMEM + in bnx2x_reset_func()
8882 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
8886 if (bp->common.int_block == INT_BLOCK_HC) { in bnx2x_reset_func()
8887 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8888 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8890 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
8891 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
8894 if (CNIC_LOADED(bp)) { in bnx2x_reset_func()
8896 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
8903 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4)) in bnx2x_reset_func()
8908 bnx2x_clear_func_ilt(bp, func); in bnx2x_reset_func()
8913 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) { in bnx2x_reset_func()
8921 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR); in bnx2x_reset_func()
8925 if (!CHIP_IS_E1x(bp)) in bnx2x_reset_func()
8926 bnx2x_pf_disable(bp); in bnx2x_reset_func()
8928 bp->dmae_ready = 0; in bnx2x_reset_func()
8931 static void bnx2x_reset_port(struct bnx2x *bp) in bnx2x_reset_port() argument
8933 int port = BP_PORT(bp); in bnx2x_reset_port()
8937 bnx2x__link_reset(bp); in bnx2x_reset_port()
8939 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
8942 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
8944 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
8948 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
8952 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); in bnx2x_reset_port()
8960 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code) in bnx2x_reset_hw() argument
8967 func_params.f_obj = &bp->func_obj; in bnx2x_reset_hw()
8972 return bnx2x_func_state_change(bp, &func_params); in bnx2x_reset_hw()
8975 static int bnx2x_func_stop(struct bnx2x *bp) in bnx2x_func_stop() argument
8982 func_params.f_obj = &bp->func_obj; in bnx2x_func_stop()
8991 rc = bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
8998 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_stop()
9013 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode) in bnx2x_send_unload_req() argument
9016 int port = BP_PORT(bp); in bnx2x_send_unload_req()
9022 else if (bp->flags & NO_WOL_FLAG) in bnx2x_send_unload_req()
9025 else if (bp->wol) { in bnx2x_send_unload_req()
9027 u8 *mac_addr = bp->dev->dev_addr; in bnx2x_send_unload_req()
9028 struct pci_dev *pdev = bp->pdev; in bnx2x_send_unload_req()
9035 u8 entry = (BP_VN(bp) + 1)*8; in bnx2x_send_unload_req()
9038 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); in bnx2x_send_unload_req()
9042 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); in bnx2x_send_unload_req()
9055 if (!BP_NOMCP(bp)) in bnx2x_send_unload_req()
9056 reset_code = bnx2x_fw_command(bp, reset_code, 0); in bnx2x_send_unload_req()
9058 int path = BP_PATH(bp); in bnx2x_send_unload_req()
9085 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link) in bnx2x_send_unload_done() argument
9090 if (!BP_NOMCP(bp)) in bnx2x_send_unload_done()
9091 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param); in bnx2x_send_unload_done()
9094 static int bnx2x_func_wait_started(struct bnx2x *bp) in bnx2x_func_wait_started() argument
9097 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0; in bnx2x_func_wait_started()
9099 if (!bp->port.pmf) in bnx2x_func_wait_started()
9118 synchronize_irq(bp->msix_table[0].vector); in bnx2x_func_wait_started()
9120 synchronize_irq(bp->pdev->irq); in bnx2x_func_wait_started()
9125 while (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9129 if (bnx2x_func_get_state(bp, &bp->func_obj) != in bnx2x_func_wait_started()
9144 func_params.f_obj = &bp->func_obj; in bnx2x_func_wait_started()
9150 bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9154 return bnx2x_func_state_change(bp, &func_params); in bnx2x_func_wait_started()
9161 static void bnx2x_disable_ptp(struct bnx2x *bp) in bnx2x_disable_ptp() argument
9163 int port = BP_PORT(bp); in bnx2x_disable_ptp()
9166 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_disable_ptp()
9170 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9172 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9174 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9176 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9180 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_disable_ptp()
9185 static void bnx2x_stop_ptp(struct bnx2x *bp) in bnx2x_stop_ptp() argument
9190 cancel_work_sync(&bp->ptp_task); in bnx2x_stop_ptp()
9192 if (bp->ptp_tx_skb) { in bnx2x_stop_ptp()
9193 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_stop_ptp()
9194 bp->ptp_tx_skb = NULL; in bnx2x_stop_ptp()
9198 bnx2x_disable_ptp(bp); in bnx2x_stop_ptp()
9203 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link) in bnx2x_chip_cleanup() argument
9205 int port = BP_PORT(bp); in bnx2x_chip_cleanup()
9212 for_each_tx_queue(bp, i) { in bnx2x_chip_cleanup()
9213 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_chip_cleanup()
9216 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]); in bnx2x_chip_cleanup()
9227 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC, in bnx2x_chip_cleanup()
9233 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC, in bnx2x_chip_cleanup()
9240 if (!CHIP_IS_E1(bp)) in bnx2x_chip_cleanup()
9241 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9247 netif_addr_lock_bh(bp->dev); in bnx2x_chip_cleanup()
9249 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_chip_cleanup()
9250 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_chip_cleanup()
9252 bnx2x_set_storm_rx_mode(bp); in bnx2x_chip_cleanup()
9255 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_chip_cleanup()
9256 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_chip_cleanup()
9260 netif_addr_unlock_bh(bp->dev); in bnx2x_chip_cleanup()
9262 bnx2x_iov_chip_cleanup(bp); in bnx2x_chip_cleanup()
9269 reset_code = bnx2x_send_unload_req(bp, unload_mode); in bnx2x_chip_cleanup()
9275 rc = bnx2x_func_wait_started(bp); in bnx2x_chip_cleanup()
9286 for_each_eth_queue(bp, i) in bnx2x_chip_cleanup()
9287 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9294 if (CNIC_LOADED(bp)) { in bnx2x_chip_cleanup()
9295 for_each_cnic_queue(bp, i) in bnx2x_chip_cleanup()
9296 if (bnx2x_stop_queue(bp, i)) in bnx2x_chip_cleanup()
9307 if (!bnx2x_wait_sp_comp(bp, ~0x0UL)) in bnx2x_chip_cleanup()
9313 rc = bnx2x_func_stop(bp); in bnx2x_chip_cleanup()
9326 if (bp->flags & PTP_SUPPORTED) in bnx2x_chip_cleanup()
9327 bnx2x_stop_ptp(bp); in bnx2x_chip_cleanup()
9330 bnx2x_netif_stop(bp, 1); in bnx2x_chip_cleanup()
9332 bnx2x_del_all_napi(bp); in bnx2x_chip_cleanup()
9333 if (CNIC_LOADED(bp)) in bnx2x_chip_cleanup()
9334 bnx2x_del_all_napi_cnic(bp); in bnx2x_chip_cleanup()
9337 bnx2x_free_irq(bp); in bnx2x_chip_cleanup()
9340 rc = bnx2x_reset_hw(bp, reset_code); in bnx2x_chip_cleanup()
9345 bnx2x_send_unload_done(bp, keep_link); in bnx2x_chip_cleanup()
9348 void bnx2x_disable_close_the_gate(struct bnx2x *bp) in bnx2x_disable_close_the_gate() argument
9354 if (CHIP_IS_E1(bp)) { in bnx2x_disable_close_the_gate()
9355 int port = BP_PORT(bp); in bnx2x_disable_close_the_gate()
9359 val = REG_RD(bp, addr); in bnx2x_disable_close_the_gate()
9361 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
9363 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK); in bnx2x_disable_close_the_gate()
9366 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
9371 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close) in bnx2x_set_234_gates() argument
9376 if (!CHIP_IS_E1(bp)) { in bnx2x_set_234_gates()
9378 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bnx2x_set_234_gates()
9380 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bnx2x_set_234_gates()
9384 if (CHIP_IS_E1x(bp)) { in bnx2x_set_234_gates()
9386 val = REG_RD(bp, HC_REG_CONFIG_1); in bnx2x_set_234_gates()
9387 REG_WR(bp, HC_REG_CONFIG_1, in bnx2x_set_234_gates()
9391 val = REG_RD(bp, HC_REG_CONFIG_0); in bnx2x_set_234_gates()
9392 REG_WR(bp, HC_REG_CONFIG_0, in bnx2x_set_234_gates()
9397 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_set_234_gates()
9399 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, in bnx2x_set_234_gates()
9412 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_clp_reset_prep() argument
9415 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_prep()
9417 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); in bnx2x_clp_reset_prep()
9426 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val) in bnx2x_clp_reset_done() argument
9429 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb); in bnx2x_clp_reset_done()
9430 MF_CFG_WR(bp, shared_mf_config.clp_mb, in bnx2x_clp_reset_done()
9442 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val) in bnx2x_reset_mcp_prep() argument
9450 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_prep()
9451 bnx2x_clp_reset_prep(bp, magic_val); in bnx2x_reset_mcp_prep()
9454 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_reset_mcp_prep()
9456 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]); in bnx2x_reset_mcp_prep()
9460 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9471 static void bnx2x_mcp_wait_one(struct bnx2x *bp) in bnx2x_mcp_wait_one() argument
9475 if (CHIP_REV_IS_SLOW(bp)) in bnx2x_mcp_wait_one()
9484 static int bnx2x_init_shmem(struct bnx2x *bp) in bnx2x_init_shmem() argument
9490 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR); in bnx2x_init_shmem()
9491 if (bp->common.shmem_base) { in bnx2x_init_shmem()
9492 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]); in bnx2x_init_shmem()
9497 bnx2x_mcp_wait_one(bp); in bnx2x_init_shmem()
9506 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val) in bnx2x_reset_mcp_comp() argument
9508 int rc = bnx2x_init_shmem(bp); in bnx2x_reset_mcp_comp()
9511 if (!CHIP_IS_E1(bp)) in bnx2x_reset_mcp_comp()
9512 bnx2x_clp_reset_done(bp, magic_val); in bnx2x_reset_mcp_comp()
9517 static void bnx2x_pxp_prep(struct bnx2x *bp) in bnx2x_pxp_prep() argument
9519 if (!CHIP_IS_E1(bp)) { in bnx2x_pxp_prep()
9520 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9521 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9536 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global) in bnx2x_process_kill_chip_reset() argument
9588 if (CHIP_IS_E1(bp)) in bnx2x_process_kill_chip_reset()
9590 else if (CHIP_IS_E1H(bp)) in bnx2x_process_kill_chip_reset()
9592 else if (CHIP_IS_E2(bp)) in bnx2x_process_kill_chip_reset()
9615 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
9618 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
9624 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_process_kill_chip_reset()
9630 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
9643 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp) in bnx2x_er_poll_igu_vq() argument
9649 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS); in bnx2x_er_poll_igu_vq()
9666 static int bnx2x_process_kill(struct bnx2x *bp, bool global) in bnx2x_process_kill() argument
9675 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT); in bnx2x_process_kill()
9676 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT); in bnx2x_process_kill()
9677 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0); in bnx2x_process_kill()
9678 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1); in bnx2x_process_kill()
9679 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2); in bnx2x_process_kill()
9680 if (CHIP_IS_E3(bp)) in bnx2x_process_kill()
9681 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32); in bnx2x_process_kill()
9687 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff))) in bnx2x_process_kill()
9703 bnx2x_set_234_gates(bp, true); in bnx2x_process_kill()
9706 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp)) in bnx2x_process_kill()
9712 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9726 bnx2x_reset_mcp_prep(bp, &val); in bnx2x_process_kill()
9729 bnx2x_pxp_prep(bp); in bnx2x_process_kill()
9733 bnx2x_process_kill_chip_reset(bp, global); in bnx2x_process_kill()
9737 if (!CHIP_IS_E1x(bp)) in bnx2x_process_kill()
9738 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
9742 if (global && bnx2x_reset_mcp_comp(bp, val)) in bnx2x_process_kill()
9748 bnx2x_set_234_gates(bp, false); in bnx2x_process_kill()
9756 static int bnx2x_leader_reset(struct bnx2x *bp) in bnx2x_leader_reset() argument
9759 bool global = bnx2x_reset_is_global(bp); in bnx2x_leader_reset()
9765 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9766 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, in bnx2x_leader_reset()
9779 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0); in bnx2x_leader_reset()
9788 if (bnx2x_process_kill(bp, global)) { in bnx2x_leader_reset()
9790 BP_PATH(bp)); in bnx2x_leader_reset()
9799 bnx2x_set_reset_done(bp); in bnx2x_leader_reset()
9801 bnx2x_clear_reset_global(bp); in bnx2x_leader_reset()
9805 if (!global && !BP_NOMCP(bp)) { in bnx2x_leader_reset()
9806 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); in bnx2x_leader_reset()
9807 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0); in bnx2x_leader_reset()
9810 bp->is_leader = 0; in bnx2x_leader_reset()
9811 bnx2x_release_leader_lock(bp); in bnx2x_leader_reset()
9816 static void bnx2x_recovery_failed(struct bnx2x *bp) in bnx2x_recovery_failed() argument
9818 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n"); in bnx2x_recovery_failed()
9821 netif_device_detach(bp->dev); in bnx2x_recovery_failed()
9827 bnx2x_set_reset_in_progress(bp); in bnx2x_recovery_failed()
9830 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_recovery_failed()
9832 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_recovery_failed()
9842 static void bnx2x_parity_recover(struct bnx2x *bp) in bnx2x_parity_recover() argument
9850 switch (bp->recovery_state) { in bnx2x_parity_recover()
9853 is_parity = bnx2x_chk_parity_attn(bp, &global, false); in bnx2x_parity_recover()
9857 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
9858 bnx2x_set_reset_in_progress(bp); in bnx2x_parity_recover()
9866 bnx2x_set_reset_global(bp); in bnx2x_parity_recover()
9868 bp->is_leader = 1; in bnx2x_parity_recover()
9873 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false)) in bnx2x_parity_recover()
9876 bp->recovery_state = BNX2X_RECOVERY_WAIT; in bnx2x_parity_recover()
9887 if (bp->is_leader) { in bnx2x_parity_recover()
9888 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_parity_recover()
9890 bnx2x_get_load_status(bp, other_engine); in bnx2x_parity_recover()
9892 bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_parity_recover()
9893 global = bnx2x_reset_is_global(bp); in bnx2x_parity_recover()
9908 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
9917 if (bnx2x_leader_reset(bp)) { in bnx2x_parity_recover()
9918 bnx2x_recovery_failed(bp); in bnx2x_parity_recover()
9930 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) { in bnx2x_parity_recover()
9937 if (bnx2x_trylock_leader_lock(bp)) { in bnx2x_parity_recover()
9941 bp->is_leader = 1; in bnx2x_parity_recover()
9945 schedule_delayed_work(&bp->sp_rtnl_task, in bnx2x_parity_recover()
9954 if (bnx2x_reset_is_global(bp)) { in bnx2x_parity_recover()
9956 &bp->sp_rtnl_task, in bnx2x_parity_recover()
9962 bp->eth_stats.recoverable_error; in bnx2x_parity_recover()
9964 bp->eth_stats.unrecoverable_error; in bnx2x_parity_recover()
9965 bp->recovery_state = in bnx2x_parity_recover()
9967 if (bnx2x_nic_load(bp, LOAD_NORMAL)) { in bnx2x_parity_recover()
9969 netdev_err(bp->dev, in bnx2x_parity_recover()
9972 netif_device_detach(bp->dev); in bnx2x_parity_recover()
9975 bp, PCI_D3hot); in bnx2x_parity_recover()
9978 bp->recovery_state = in bnx2x_parity_recover()
9983 bp->eth_stats.recoverable_error = in bnx2x_parity_recover()
9985 bp->eth_stats.unrecoverable_error = in bnx2x_parity_recover()
10004 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work); in bnx2x_sp_rtnl_task() local
10008 if (!netif_running(bp->dev)) { in bnx2x_sp_rtnl_task()
10013 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) { in bnx2x_sp_rtnl_task()
10023 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10026 bnx2x_parity_recover(bp); in bnx2x_sp_rtnl_task()
10032 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10043 bp->sp_rtnl_state = 0; in bnx2x_sp_rtnl_task()
10046 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true); in bnx2x_sp_rtnl_task()
10047 bnx2x_nic_load(bp, LOAD_NORMAL); in bnx2x_sp_rtnl_task()
10055 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10056 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos); in bnx2x_sp_rtnl_task()
10057 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10058 bnx2x_after_function_update(bp); in bnx2x_sp_rtnl_task()
10064 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10066 netif_device_detach(bp->dev); in bnx2x_sp_rtnl_task()
10067 bnx2x_close(bp->dev); in bnx2x_sp_rtnl_task()
10072 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10075 bnx2x_vfpf_set_mcast(bp->dev); in bnx2x_sp_rtnl_task()
10078 &bp->sp_rtnl_state)){ in bnx2x_sp_rtnl_task()
10079 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) { in bnx2x_sp_rtnl_task()
10080 bnx2x_tx_disable(bp); in bnx2x_sp_rtnl_task()
10085 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10087 bnx2x_set_rx_mode_inner(bp); in bnx2x_sp_rtnl_task()
10091 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10092 bnx2x_pf_set_vfs_vlan(bp); in bnx2x_sp_rtnl_task()
10094 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10095 bnx2x_dcbx_stop_hw_tx(bp); in bnx2x_sp_rtnl_task()
10096 bnx2x_dcbx_resume_hw_tx(bp); in bnx2x_sp_rtnl_task()
10100 &bp->sp_rtnl_state)) in bnx2x_sp_rtnl_task()
10101 bnx2x_update_mng_version(bp); in bnx2x_sp_rtnl_task()
10109 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV, in bnx2x_sp_rtnl_task()
10110 &bp->sp_rtnl_state)) { in bnx2x_sp_rtnl_task()
10111 bnx2x_disable_sriov(bp); in bnx2x_sp_rtnl_task()
10112 bnx2x_enable_sriov(bp); in bnx2x_sp_rtnl_task()
10118 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work); in bnx2x_period_task() local
10120 if (!netif_running(bp->dev)) in bnx2x_period_task()
10123 if (CHIP_REV_IS_SLOW(bp)) { in bnx2x_period_task()
10128 bnx2x_acquire_phy_lock(bp); in bnx2x_period_task()
10135 if (bp->port.pmf) { in bnx2x_period_task()
10136 bnx2x_period_func(&bp->link_params, &bp->link_vars); in bnx2x_period_task()
10139 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ); in bnx2x_period_task()
10142 bnx2x_release_phy_lock(bp); in bnx2x_period_task()
10151 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp) in bnx2x_get_pretend_reg() argument
10155 return base + (BP_ABS_FUNC(bp)) * stride; in bnx2x_get_pretend_reg()
10158 static bool bnx2x_prev_unload_close_umac(struct bnx2x *bp, in bnx2x_prev_unload_close_umac() argument
10171 vals->umac_val[port] = REG_RD(bp, vals->umac_addr[port]); in bnx2x_prev_unload_close_umac()
10172 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10177 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp, in bnx2x_prev_unload_close_mac() argument
10182 u8 port = BP_PORT(bp); in bnx2x_prev_unload_close_mac()
10187 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2); in bnx2x_prev_unload_close_mac()
10189 if (!CHIP_IS_E3(bp)) { in bnx2x_prev_unload_close_mac()
10190 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); in bnx2x_prev_unload_close_mac()
10195 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM in bnx2x_prev_unload_close_mac()
10197 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL in bnx2x_prev_unload_close_mac()
10206 wb_data[0] = REG_RD(bp, base_addr + offset); in bnx2x_prev_unload_close_mac()
10207 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4); in bnx2x_prev_unload_close_mac()
10212 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10213 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10216 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4; in bnx2x_prev_unload_close_mac()
10217 vals->emac_val = REG_RD(bp, vals->emac_addr); in bnx2x_prev_unload_close_mac()
10218 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10223 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; in bnx2x_prev_unload_close_mac()
10224 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI); in bnx2x_prev_unload_close_mac()
10225 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10227 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10230 vals->xmac_val = REG_RD(bp, vals->xmac_addr); in bnx2x_prev_unload_close_mac()
10231 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10235 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 0, in bnx2x_prev_unload_close_mac()
10237 mac_stopped |= bnx2x_prev_unload_close_umac(bp, 1, in bnx2x_prev_unload_close_mac()
10256 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp) in bnx2x_prev_is_after_undi() argument
10261 if (!(REG_RD(bp, MISC_REG_RESET_REG_1) & in bnx2x_prev_is_after_undi()
10265 if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) { in bnx2x_prev_is_after_undi()
10273 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc) in bnx2x_prev_unload_undi_inc() argument
10278 if (BP_FUNC(bp) < 2) in bnx2x_prev_unload_undi_inc()
10279 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp)); in bnx2x_prev_unload_undi_inc()
10281 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2); in bnx2x_prev_unload_undi_inc()
10283 tmp_reg = REG_RD(bp, addr); in bnx2x_prev_unload_undi_inc()
10288 REG_WR(bp, addr, tmp_reg); in bnx2x_prev_unload_undi_inc()
10291 BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq); in bnx2x_prev_unload_undi_inc()
10294 static int bnx2x_prev_mcp_done(struct bnx2x *bp) in bnx2x_prev_mcp_done() argument
10296 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, in bnx2x_prev_mcp_done()
10307 bnx2x_prev_path_get_entry(struct bnx2x *bp) in bnx2x_prev_path_get_entry() argument
10312 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot && in bnx2x_prev_path_get_entry()
10313 bp->pdev->bus->number == tmp_list->bus && in bnx2x_prev_path_get_entry()
10314 BP_PATH(bp) == tmp_list->path) in bnx2x_prev_path_get_entry()
10320 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp) in bnx2x_prev_path_mark_eeh() argument
10331 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_path_mark_eeh()
10337 BP_PATH(bp)); in bnx2x_prev_path_mark_eeh()
10345 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp) in bnx2x_prev_is_path_marked() argument
10353 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_is_path_marked()
10357 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10361 BP_PATH(bp)); in bnx2x_prev_is_path_marked()
10370 bool bnx2x_port_after_undi(struct bnx2x *bp) in bnx2x_port_after_undi() argument
10377 entry = bnx2x_prev_path_get_entry(bp); in bnx2x_port_after_undi()
10378 val = !!(entry && (entry->undi & (1 << BP_PORT(bp)))); in bnx2x_port_after_undi()
10385 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi) in bnx2x_prev_mark_path() argument
10397 tmp_list = bnx2x_prev_path_get_entry(bp); in bnx2x_prev_mark_path()
10403 BP_PATH(bp)); in bnx2x_prev_mark_path()
10418 tmp_list->bus = bp->pdev->bus->number; in bnx2x_prev_mark_path()
10419 tmp_list->slot = PCI_SLOT(bp->pdev->devfn); in bnx2x_prev_mark_path()
10420 tmp_list->path = BP_PATH(bp); in bnx2x_prev_mark_path()
10422 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0; in bnx2x_prev_mark_path()
10430 BP_PATH(bp)); in bnx2x_prev_mark_path()
10438 static int bnx2x_do_flr(struct bnx2x *bp) in bnx2x_do_flr() argument
10440 struct pci_dev *dev = bp->pdev; in bnx2x_do_flr()
10442 if (CHIP_IS_E1x(bp)) { in bnx2x_do_flr()
10448 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { in bnx2x_do_flr()
10450 bp->common.bc_ver); in bnx2x_do_flr()
10458 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0); in bnx2x_do_flr()
10463 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp) in bnx2x_prev_unload_uncommon() argument
10470 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_uncommon()
10471 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10476 if (bnx2x_prev_is_after_undi(bp)) in bnx2x_prev_unload_uncommon()
10483 rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false); in bnx2x_prev_unload_uncommon()
10488 rc = bnx2x_do_flr(bp); in bnx2x_prev_unload_uncommon()
10501 rc = bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_uncommon()
10508 static int bnx2x_prev_unload_common(struct bnx2x *bp) in bnx2x_prev_unload_common() argument
10522 if (bnx2x_prev_is_path_marked(bp)) in bnx2x_prev_unload_common()
10523 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10525 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1); in bnx2x_prev_unload_common()
10532 bnx2x_prev_unload_close_mac(bp, &mac_vals); in bnx2x_prev_unload_common()
10535 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10536 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10537 bnx2x_set_rx_filter(&bp->link_params, 0); in bnx2x_prev_unload_common()
10538 bp->link_params.port ^= 1; in bnx2x_prev_unload_common()
10541 if (bnx2x_prev_is_after_undi(bp)) { in bnx2x_prev_unload_common()
10544 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10546 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0); in bnx2x_prev_unload_common()
10548 if (!CHIP_IS_E1x(bp)) in bnx2x_prev_unload_common()
10550 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10553 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10557 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS); in bnx2x_prev_unload_common()
10571 bnx2x_prev_unload_undi_inc(bp, 1); in bnx2x_prev_unload_common()
10581 bnx2x_reset_common(bp); in bnx2x_prev_unload_common()
10584 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); in bnx2x_prev_unload_common()
10586 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10588 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); in bnx2x_prev_unload_common()
10590 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); in bnx2x_prev_unload_common()
10592 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10593 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bnx2x_prev_unload_common()
10596 rc = bnx2x_prev_mark_path(bp, prev_undi); in bnx2x_prev_unload_common()
10598 bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10602 return bnx2x_prev_mcp_done(bp); in bnx2x_prev_unload_common()
10605 static int bnx2x_prev_unload(struct bnx2x *bp) in bnx2x_prev_unload() argument
10614 bnx2x_clean_pglue_errors(bp); in bnx2x_prev_unload()
10617 hw_lock_reg = (BP_FUNC(bp) <= 5) ? in bnx2x_prev_unload()
10618 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) : in bnx2x_prev_unload()
10619 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8); in bnx2x_prev_unload()
10621 hw_lock_val = REG_RD(bp, hw_lock_reg); in bnx2x_prev_unload()
10625 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_prev_unload()
10626 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp))); in bnx2x_prev_unload()
10630 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
10634 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) { in bnx2x_prev_unload()
10636 bnx2x_release_alr(bp); in bnx2x_prev_unload()
10642 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); in bnx2x_prev_unload()
10655 aer = !!(bnx2x_prev_path_get_entry(bp) && in bnx2x_prev_unload()
10656 bnx2x_prev_path_get_entry(bp)->aer); in bnx2x_prev_unload()
10661 rc = bnx2x_prev_unload_common(bp); in bnx2x_prev_unload()
10666 rc = bnx2x_prev_unload_uncommon(bp); in bnx2x_prev_unload()
10679 if (bnx2x_port_after_undi(bp)) in bnx2x_prev_unload()
10680 bp->link_params.feature_config_flags |= in bnx2x_prev_unload()
10688 static void bnx2x_get_common_hwinfo(struct bnx2x *bp) in bnx2x_get_common_hwinfo() argument
10695 val = REG_RD(bp, MISC_REG_CHIP_NUM); in bnx2x_get_common_hwinfo()
10697 val = REG_RD(bp, MISC_REG_CHIP_REV); in bnx2x_get_common_hwinfo()
10703 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3); in bnx2x_get_common_hwinfo()
10705 val = REG_RD(bp, MISC_REG_BOND_ID); in bnx2x_get_common_hwinfo()
10707 bp->common.chip_id = id; in bnx2x_get_common_hwinfo()
10710 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { in bnx2x_get_common_hwinfo()
10711 if (CHIP_IS_57810(bp)) in bnx2x_get_common_hwinfo()
10712 bp->common.chip_id = (CHIP_NUM_57811 << 16) | in bnx2x_get_common_hwinfo()
10713 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10714 else if (CHIP_IS_57810_MF(bp)) in bnx2x_get_common_hwinfo()
10715 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) | in bnx2x_get_common_hwinfo()
10716 (bp->common.chip_id & 0x0000FFFF); in bnx2x_get_common_hwinfo()
10717 bp->common.chip_id |= 0x1; in bnx2x_get_common_hwinfo()
10721 bp->db_size = (1 << BNX2X_DB_SHIFT); in bnx2x_get_common_hwinfo()
10723 if (!CHIP_IS_E1x(bp)) { in bnx2x_get_common_hwinfo()
10724 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR); in bnx2x_get_common_hwinfo()
10726 val = REG_RD(bp, MISC_REG_PORT4MODE_EN); in bnx2x_get_common_hwinfo()
10731 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE : in bnx2x_get_common_hwinfo()
10734 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_get_common_hwinfo()
10735 bp->pfid = (bp->pf_num >> 1); /* 0..3 */ in bnx2x_get_common_hwinfo()
10737 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */ in bnx2x_get_common_hwinfo()
10739 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */ in bnx2x_get_common_hwinfo()
10740 bp->pfid = bp->pf_num; /* 0..7 */ in bnx2x_get_common_hwinfo()
10743 BNX2X_DEV_INFO("pf_id: %x", bp->pfid); in bnx2x_get_common_hwinfo()
10745 bp->link_params.chip_id = bp->common.chip_id; in bnx2x_get_common_hwinfo()
10748 val = (REG_RD(bp, 0x2874) & 0x55); in bnx2x_get_common_hwinfo()
10749 if ((bp->common.chip_id & 0x1) || in bnx2x_get_common_hwinfo()
10750 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) { in bnx2x_get_common_hwinfo()
10751 bp->flags |= ONE_PORT_FLAG; in bnx2x_get_common_hwinfo()
10755 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4); in bnx2x_get_common_hwinfo()
10756 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE << in bnx2x_get_common_hwinfo()
10759 bp->common.flash_size, bp->common.flash_size); in bnx2x_get_common_hwinfo()
10761 bnx2x_init_shmem(bp); in bnx2x_get_common_hwinfo()
10763 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ? in bnx2x_get_common_hwinfo()
10767 bp->link_params.shmem_base = bp->common.shmem_base; in bnx2x_get_common_hwinfo()
10768 bp->link_params.shmem2_base = bp->common.shmem2_base; in bnx2x_get_common_hwinfo()
10769 if (SHMEM2_RD(bp, size) > in bnx2x_get_common_hwinfo()
10770 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)])) in bnx2x_get_common_hwinfo()
10771 bp->link_params.lfa_base = in bnx2x_get_common_hwinfo()
10772 REG_RD(bp, bp->common.shmem2_base + in bnx2x_get_common_hwinfo()
10774 lfa_host_addr[BP_PORT(bp)])); in bnx2x_get_common_hwinfo()
10776 bp->link_params.lfa_base = 0; in bnx2x_get_common_hwinfo()
10778 bp->common.shmem_base, bp->common.shmem2_base); in bnx2x_get_common_hwinfo()
10780 if (!bp->common.shmem_base) { in bnx2x_get_common_hwinfo()
10782 bp->flags |= NO_MCP_FLAG; in bnx2x_get_common_hwinfo()
10786 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config); in bnx2x_get_common_hwinfo()
10787 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config); in bnx2x_get_common_hwinfo()
10789 bp->link_params.hw_led_mode = ((bp->common.hw_config & in bnx2x_get_common_hwinfo()
10793 bp->link_params.feature_config_flags = 0; in bnx2x_get_common_hwinfo()
10794 val = SHMEM_RD(bp, dev_info.shared_feature_config.config); in bnx2x_get_common_hwinfo()
10796 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10799 bp->link_params.feature_config_flags &= in bnx2x_get_common_hwinfo()
10802 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8; in bnx2x_get_common_hwinfo()
10803 bp->common.bc_ver = val; in bnx2x_get_common_hwinfo()
10811 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10815 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10818 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10821 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10825 bp->link_params.feature_config_flags |= in bnx2x_get_common_hwinfo()
10829 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ? in bnx2x_get_common_hwinfo()
10832 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ? in bnx2x_get_common_hwinfo()
10835 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ? in bnx2x_get_common_hwinfo()
10838 bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ? in bnx2x_get_common_hwinfo()
10841 boot_mode = SHMEM_RD(bp, in bnx2x_get_common_hwinfo()
10842 dev_info.port_feature_config[BP_PORT(bp)].mba_config) & in bnx2x_get_common_hwinfo()
10846 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE; in bnx2x_get_common_hwinfo()
10849 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI; in bnx2x_get_common_hwinfo()
10852 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE; in bnx2x_get_common_hwinfo()
10855 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE; in bnx2x_get_common_hwinfo()
10859 pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc); in bnx2x_get_common_hwinfo()
10860 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG; in bnx2x_get_common_hwinfo()
10863 (bp->flags & NO_WOL_FLAG) ? "not " : ""); in bnx2x_get_common_hwinfo()
10865 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num); in bnx2x_get_common_hwinfo()
10866 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]); in bnx2x_get_common_hwinfo()
10867 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]); in bnx2x_get_common_hwinfo()
10868 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]); in bnx2x_get_common_hwinfo()
10870 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n", in bnx2x_get_common_hwinfo()
10877 static int bnx2x_get_igu_cam_info(struct bnx2x *bp) in bnx2x_get_igu_cam_info() argument
10879 int pfid = BP_FUNC(bp); in bnx2x_get_igu_cam_info()
10884 bp->igu_base_sb = 0xff; in bnx2x_get_igu_cam_info()
10885 if (CHIP_INT_MODE_IS_BC(bp)) { in bnx2x_get_igu_cam_info()
10886 int vn = BP_VN(bp); in bnx2x_get_igu_cam_info()
10887 igu_sb_cnt = bp->igu_sb_cnt; in bnx2x_get_igu_cam_info()
10888 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * in bnx2x_get_igu_cam_info()
10891 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x + in bnx2x_get_igu_cam_info()
10892 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn); in bnx2x_get_igu_cam_info()
10900 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); in bnx2x_get_igu_cam_info()
10909 bp->igu_dsb_id = igu_sb_id; in bnx2x_get_igu_cam_info()
10911 if (bp->igu_base_sb == 0xff) in bnx2x_get_igu_cam_info()
10912 bp->igu_base_sb = igu_sb_id; in bnx2x_get_igu_cam_info()
10925 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt); in bnx2x_get_igu_cam_info()
10936 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg) in bnx2x_link_settings_supported() argument
10938 int cfg_size = 0, idx, port = BP_PORT(bp); in bnx2x_link_settings_supported()
10941 bp->port.supported[0] = 0; in bnx2x_link_settings_supported()
10942 bp->port.supported[1] = 0; in bnx2x_link_settings_supported()
10943 switch (bp->link_params.num_phys) { in bnx2x_link_settings_supported()
10945 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported; in bnx2x_link_settings_supported()
10949 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
10953 if (bp->link_params.multi_phy_config & in bnx2x_link_settings_supported()
10955 bp->port.supported[1] = in bnx2x_link_settings_supported()
10956 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
10957 bp->port.supported[0] = in bnx2x_link_settings_supported()
10958 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
10960 bp->port.supported[0] = in bnx2x_link_settings_supported()
10961 bp->link_params.phy[EXT_PHY1].supported; in bnx2x_link_settings_supported()
10962 bp->port.supported[1] = in bnx2x_link_settings_supported()
10963 bp->link_params.phy[EXT_PHY2].supported; in bnx2x_link_settings_supported()
10969 if (!(bp->port.supported[0] || bp->port.supported[1])) { in bnx2x_link_settings_supported()
10971 SHMEM_RD(bp, in bnx2x_link_settings_supported()
10973 SHMEM_RD(bp, in bnx2x_link_settings_supported()
10978 if (CHIP_IS_E3(bp)) in bnx2x_link_settings_supported()
10979 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR); in bnx2x_link_settings_supported()
10983 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
10984 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); in bnx2x_link_settings_supported()
10987 bp->port.phy_addr = REG_RD( in bnx2x_link_settings_supported()
10988 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); in bnx2x_link_settings_supported()
10992 bp->port.link_config[0]); in bnx2x_link_settings_supported()
10996 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr); in bnx2x_link_settings_supported()
10999 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11001 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half; in bnx2x_link_settings_supported()
11003 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11005 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full; in bnx2x_link_settings_supported()
11007 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11009 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half; in bnx2x_link_settings_supported()
11011 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11013 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full; in bnx2x_link_settings_supported()
11015 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11017 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half | in bnx2x_link_settings_supported()
11020 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11022 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full; in bnx2x_link_settings_supported()
11024 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11026 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full; in bnx2x_link_settings_supported()
11028 if (!(bp->link_params.speed_cap_mask[idx] & in bnx2x_link_settings_supported()
11030 bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full; in bnx2x_link_settings_supported()
11033 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0], in bnx2x_link_settings_supported()
11034 bp->port.supported[1]); in bnx2x_link_settings_supported()
11037 static void bnx2x_link_settings_requested(struct bnx2x *bp) in bnx2x_link_settings_requested() argument
11040 bp->port.advertising[0] = 0; in bnx2x_link_settings_requested()
11041 bp->port.advertising[1] = 0; in bnx2x_link_settings_requested()
11042 switch (bp->link_params.num_phys) { in bnx2x_link_settings_requested()
11052 bp->link_params.req_duplex[idx] = DUPLEX_FULL; in bnx2x_link_settings_requested()
11053 link_config = bp->port.link_config[idx]; in bnx2x_link_settings_requested()
11056 if (bp->port.supported[idx] & SUPPORTED_Autoneg) { in bnx2x_link_settings_requested()
11057 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11059 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11060 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11061 if (bp->link_params.phy[EXT_PHY1].type == in bnx2x_link_settings_requested()
11063 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11068 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11070 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11078 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) { in bnx2x_link_settings_requested()
11079 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11081 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11087 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11093 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) { in bnx2x_link_settings_requested()
11094 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11096 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11098 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11104 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11110 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11112 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11114 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11120 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11126 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11128 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11130 bp->link_params.req_duplex[idx] = in bnx2x_link_settings_requested()
11132 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11138 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11144 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11146 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11148 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11154 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11160 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11162 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11164 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11170 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11176 if (bp->port.supported[idx] & in bnx2x_link_settings_requested()
11178 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11180 bp->port.advertising[idx] |= in bnx2x_link_settings_requested()
11186 bp->link_params.speed_cap_mask[idx]); in bnx2x_link_settings_requested()
11191 bp->link_params.req_line_speed[idx] = SPEED_20000; in bnx2x_link_settings_requested()
11197 bp->link_params.req_line_speed[idx] = in bnx2x_link_settings_requested()
11199 bp->port.advertising[idx] = in bnx2x_link_settings_requested()
11200 bp->port.supported[idx]; in bnx2x_link_settings_requested()
11204 bp->link_params.req_flow_ctrl[idx] = (link_config & in bnx2x_link_settings_requested()
11206 if (bp->link_params.req_flow_ctrl[idx] == in bnx2x_link_settings_requested()
11208 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg)) in bnx2x_link_settings_requested()
11209 bp->link_params.req_flow_ctrl[idx] = in bnx2x_link_settings_requested()
11212 bnx2x_set_requested_fc(bp); in bnx2x_link_settings_requested()
11216 bp->link_params.req_line_speed[idx], in bnx2x_link_settings_requested()
11217 bp->link_params.req_duplex[idx], in bnx2x_link_settings_requested()
11218 bp->link_params.req_flow_ctrl[idx], in bnx2x_link_settings_requested()
11219 bp->port.advertising[idx]); in bnx2x_link_settings_requested()
11231 static void bnx2x_get_port_hwinfo(struct bnx2x *bp) in bnx2x_get_port_hwinfo() argument
11233 int port = BP_PORT(bp); in bnx2x_get_port_hwinfo()
11237 bp->link_params.bp = bp; in bnx2x_get_port_hwinfo()
11238 bp->link_params.port = port; in bnx2x_get_port_hwinfo()
11240 bp->link_params.lane_config = in bnx2x_get_port_hwinfo()
11241 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config); in bnx2x_get_port_hwinfo()
11243 bp->link_params.speed_cap_mask[0] = in bnx2x_get_port_hwinfo()
11244 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11247 bp->link_params.speed_cap_mask[1] = in bnx2x_get_port_hwinfo()
11248 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11251 bp->port.link_config[0] = in bnx2x_get_port_hwinfo()
11252 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config); in bnx2x_get_port_hwinfo()
11254 bp->port.link_config[1] = in bnx2x_get_port_hwinfo()
11255 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2); in bnx2x_get_port_hwinfo()
11257 bp->link_params.multi_phy_config = in bnx2x_get_port_hwinfo()
11258 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config); in bnx2x_get_port_hwinfo()
11262 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config); in bnx2x_get_port_hwinfo()
11263 bp->wol = (!(bp->flags & NO_WOL_FLAG) && in bnx2x_get_port_hwinfo()
11267 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp)) in bnx2x_get_port_hwinfo()
11268 bp->flags |= NO_ISCSI_FLAG; in bnx2x_get_port_hwinfo()
11270 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp))) in bnx2x_get_port_hwinfo()
11271 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_port_hwinfo()
11274 bp->link_params.lane_config, in bnx2x_get_port_hwinfo()
11275 bp->link_params.speed_cap_mask[0], in bnx2x_get_port_hwinfo()
11276 bp->port.link_config[0]); in bnx2x_get_port_hwinfo()
11278 bp->link_params.switch_cfg = (bp->port.link_config[0] & in bnx2x_get_port_hwinfo()
11280 bnx2x_phy_probe(&bp->link_params); in bnx2x_get_port_hwinfo()
11281 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg); in bnx2x_get_port_hwinfo()
11283 bnx2x_link_settings_requested(bp); in bnx2x_get_port_hwinfo()
11290 SHMEM_RD(bp, in bnx2x_get_port_hwinfo()
11294 bp->mdio.prtad = bp->port.phy_addr; in bnx2x_get_port_hwinfo()
11298 bp->mdio.prtad = in bnx2x_get_port_hwinfo()
11302 eee_mode = (((SHMEM_RD(bp, dev_info. in bnx2x_get_port_hwinfo()
11307 bp->link_params.eee_mode = EEE_MODE_ADV_LPI | in bnx2x_get_port_hwinfo()
11311 bp->link_params.eee_mode = 0; in bnx2x_get_port_hwinfo()
11315 void bnx2x_get_iscsi_info(struct bnx2x *bp) in bnx2x_get_iscsi_info() argument
11318 int port = BP_PORT(bp); in bnx2x_get_iscsi_info()
11319 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_iscsi_info()
11322 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_iscsi_info()
11323 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11328 bp->cnic_eth_dev.max_iscsi_conn = in bnx2x_get_iscsi_info()
11333 bp->cnic_eth_dev.max_iscsi_conn); in bnx2x_get_iscsi_info()
11339 if (!bp->cnic_eth_dev.max_iscsi_conn) in bnx2x_get_iscsi_info()
11340 bp->flags |= no_flags; in bnx2x_get_iscsi_info()
11343 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func) in bnx2x_get_ext_wwn_info() argument
11346 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_ext_wwn_info()
11347 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper); in bnx2x_get_ext_wwn_info()
11348 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_ext_wwn_info()
11349 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower); in bnx2x_get_ext_wwn_info()
11352 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_ext_wwn_info()
11353 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper); in bnx2x_get_ext_wwn_info()
11354 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_ext_wwn_info()
11355 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower); in bnx2x_get_ext_wwn_info()
11358 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp) in bnx2x_shared_fcoe_funcs() argument
11362 if (IS_MF(bp)) { in bnx2x_shared_fcoe_funcs()
11366 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) { in bnx2x_shared_fcoe_funcs()
11367 if (IS_MF_SD(bp)) { in bnx2x_shared_fcoe_funcs()
11368 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11376 u32 cfg = MF_CFG_RD(bp, in bnx2x_shared_fcoe_funcs()
11386 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1; in bnx2x_shared_fcoe_funcs()
11389 u32 lic = SHMEM_RD(bp, in bnx2x_shared_fcoe_funcs()
11400 static void bnx2x_get_fcoe_info(struct bnx2x *bp) in bnx2x_get_fcoe_info() argument
11402 int port = BP_PORT(bp); in bnx2x_get_fcoe_info()
11403 int func = BP_ABS_FUNC(bp); in bnx2x_get_fcoe_info()
11404 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11406 u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp); in bnx2x_get_fcoe_info()
11408 if (!CNIC_SUPPORT(bp)) { in bnx2x_get_fcoe_info()
11409 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11414 bp->cnic_eth_dev.max_fcoe_conn = in bnx2x_get_fcoe_info()
11419 bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE; in bnx2x_get_fcoe_info()
11423 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func; in bnx2x_get_fcoe_info()
11426 if (!IS_MF(bp)) { in bnx2x_get_fcoe_info()
11428 bp->cnic_eth_dev.fcoe_wwn_port_name_hi = in bnx2x_get_fcoe_info()
11429 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11432 bp->cnic_eth_dev.fcoe_wwn_port_name_lo = in bnx2x_get_fcoe_info()
11433 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11438 bp->cnic_eth_dev.fcoe_wwn_node_name_hi = in bnx2x_get_fcoe_info()
11439 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11442 bp->cnic_eth_dev.fcoe_wwn_node_name_lo = in bnx2x_get_fcoe_info()
11443 SHMEM_RD(bp, in bnx2x_get_fcoe_info()
11446 } else if (!IS_MF_SD(bp)) { in bnx2x_get_fcoe_info()
11450 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp)) in bnx2x_get_fcoe_info()
11451 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11453 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp)) in bnx2x_get_fcoe_info()
11454 bnx2x_get_ext_wwn_info(bp, func); in bnx2x_get_fcoe_info()
11457 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn); in bnx2x_get_fcoe_info()
11463 if (!bp->cnic_eth_dev.max_fcoe_conn) in bnx2x_get_fcoe_info()
11464 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_fcoe_info()
11467 static void bnx2x_get_cnic_info(struct bnx2x *bp) in bnx2x_get_cnic_info() argument
11474 bnx2x_get_iscsi_info(bp); in bnx2x_get_cnic_info()
11475 bnx2x_get_fcoe_info(bp); in bnx2x_get_cnic_info()
11478 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_cnic_mac_hwinfo() argument
11481 int func = BP_ABS_FUNC(bp); in bnx2x_get_cnic_mac_hwinfo()
11482 int port = BP_PORT(bp); in bnx2x_get_cnic_mac_hwinfo()
11483 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac; in bnx2x_get_cnic_mac_hwinfo()
11484 u8 *fip_mac = bp->fip_mac; in bnx2x_get_cnic_mac_hwinfo()
11486 if (IS_MF(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11492 if (!IS_MF_SD(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11493 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg); in bnx2x_get_cnic_mac_hwinfo()
11495 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11497 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11503 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11507 val2 = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11509 val = MF_CFG_RD(bp, func_ext_config[func]. in bnx2x_get_cnic_mac_hwinfo()
11515 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11518 bp->mf_ext_config = cfg; in bnx2x_get_cnic_mac_hwinfo()
11521 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11523 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11528 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) { in bnx2x_get_cnic_mac_hwinfo()
11530 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11541 if (IS_MF_FCOE_AFEX(bp)) in bnx2x_get_cnic_mac_hwinfo()
11542 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN); in bnx2x_get_cnic_mac_hwinfo()
11544 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11546 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11550 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11552 val = SHMEM_RD(bp, dev_info.port_hw_config[port]. in bnx2x_get_cnic_mac_hwinfo()
11559 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11565 bp->flags |= NO_FCOE_FLAG; in bnx2x_get_cnic_mac_hwinfo()
11566 eth_zero_addr(bp->fip_mac); in bnx2x_get_cnic_mac_hwinfo()
11570 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp) in bnx2x_get_mac_hwinfo() argument
11573 int func = BP_ABS_FUNC(bp); in bnx2x_get_mac_hwinfo()
11574 int port = BP_PORT(bp); in bnx2x_get_mac_hwinfo()
11577 eth_zero_addr(bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11579 if (BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11581 eth_hw_addr_random(bp->dev); in bnx2x_get_mac_hwinfo()
11582 } else if (IS_MF(bp)) { in bnx2x_get_mac_hwinfo()
11583 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in bnx2x_get_mac_hwinfo()
11584 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower); in bnx2x_get_mac_hwinfo()
11587 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); in bnx2x_get_mac_hwinfo()
11589 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11590 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11593 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11594 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11595 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2); in bnx2x_get_mac_hwinfo()
11597 if (CNIC_SUPPORT(bp)) in bnx2x_get_mac_hwinfo()
11598 bnx2x_get_cnic_mac_hwinfo(bp); in bnx2x_get_mac_hwinfo()
11601 if (!BP_NOMCP(bp)) { in bnx2x_get_mac_hwinfo()
11603 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper); in bnx2x_get_mac_hwinfo()
11604 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower); in bnx2x_get_mac_hwinfo()
11605 bnx2x_set_mac_buf(bp->phys_port_id, val, val2); in bnx2x_get_mac_hwinfo()
11606 bp->flags |= HAS_PHYS_PORT_ID; in bnx2x_get_mac_hwinfo()
11609 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN); in bnx2x_get_mac_hwinfo()
11611 if (!is_valid_ether_addr(bp->dev->dev_addr)) in bnx2x_get_mac_hwinfo()
11612 dev_err(&bp->pdev->dev, in bnx2x_get_mac_hwinfo()
11615 bp->dev->dev_addr); in bnx2x_get_mac_hwinfo()
11618 static bool bnx2x_get_dropless_info(struct bnx2x *bp) in bnx2x_get_dropless_info() argument
11623 if (IS_VF(bp)) in bnx2x_get_dropless_info()
11626 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) { in bnx2x_get_dropless_info()
11628 tmp = BP_ABS_FUNC(bp); in bnx2x_get_dropless_info()
11629 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg); in bnx2x_get_dropless_info()
11633 tmp = BP_PORT(bp); in bnx2x_get_dropless_info()
11634 cfg = SHMEM_RD(bp, in bnx2x_get_dropless_info()
11641 static void validate_set_si_mode(struct bnx2x *bp) in validate_set_si_mode() argument
11643 u8 func = BP_ABS_FUNC(bp); in validate_set_si_mode()
11646 val = MF_CFG_RD(bp, func_mf_config[func].mac_upper); in validate_set_si_mode()
11650 bp->mf_mode = MULTI_FUNCTION_SI; in validate_set_si_mode()
11651 bp->mf_config[BP_VN(bp)] = in validate_set_si_mode()
11652 MF_CFG_RD(bp, func_mf_config[func].config); in validate_set_si_mode()
11657 static int bnx2x_get_hwinfo(struct bnx2x *bp) in bnx2x_get_hwinfo() argument
11659 int /*abs*/func = BP_ABS_FUNC(bp); in bnx2x_get_hwinfo()
11665 if (REG_RD(bp, MISC_REG_CHIP_NUM) == 0xffffffff) { in bnx2x_get_hwinfo()
11666 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11671 bnx2x_get_common_hwinfo(bp); in bnx2x_get_hwinfo()
11676 if (CHIP_IS_E1x(bp)) { in bnx2x_get_hwinfo()
11677 bp->common.int_block = INT_BLOCK_HC; in bnx2x_get_hwinfo()
11679 bp->igu_dsb_id = DEF_SB_IGU_ID; in bnx2x_get_hwinfo()
11680 bp->igu_base_sb = 0; in bnx2x_get_hwinfo()
11682 bp->common.int_block = INT_BLOCK_IGU; in bnx2x_get_hwinfo()
11685 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11687 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION); in bnx2x_get_hwinfo()
11695 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); in bnx2x_get_hwinfo()
11696 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
11698 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11703 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) { in bnx2x_get_hwinfo()
11704 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11706 bnx2x_release_hw_lock(bp, in bnx2x_get_hwinfo()
11714 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP; in bnx2x_get_hwinfo()
11718 rc = bnx2x_get_igu_cam_info(bp); in bnx2x_get_hwinfo()
11719 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET); in bnx2x_get_hwinfo()
11729 if (CHIP_IS_E1x(bp)) in bnx2x_get_hwinfo()
11730 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp); in bnx2x_get_hwinfo()
11736 bp->base_fw_ndsb = bp->igu_base_sb; in bnx2x_get_hwinfo()
11739 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb, in bnx2x_get_hwinfo()
11740 bp->igu_sb_cnt, bp->base_fw_ndsb); in bnx2x_get_hwinfo()
11746 bp->mf_ov = 0; in bnx2x_get_hwinfo()
11747 bp->mf_mode = 0; in bnx2x_get_hwinfo()
11748 bp->mf_sub_mode = 0; in bnx2x_get_hwinfo()
11749 vn = BP_VN(bp); in bnx2x_get_hwinfo()
11751 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { in bnx2x_get_hwinfo()
11753 bp->common.shmem2_base, SHMEM2_RD(bp, size), in bnx2x_get_hwinfo()
11756 if (SHMEM2_HAS(bp, mf_cfg_addr)) in bnx2x_get_hwinfo()
11757 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr); in bnx2x_get_hwinfo()
11759 bp->common.mf_cfg_base = bp->common.shmem_base + in bnx2x_get_hwinfo()
11770 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
11772 val = SHMEM_RD(bp, in bnx2x_get_hwinfo()
11778 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
11781 if ((!CHIP_IS_E1x(bp)) && in bnx2x_get_hwinfo()
11782 (MF_CFG_RD(bp, func_mf_config[func]. in bnx2x_get_hwinfo()
11784 (SHMEM2_HAS(bp, in bnx2x_get_hwinfo()
11786 bp->mf_mode = MULTI_FUNCTION_AFEX; in bnx2x_get_hwinfo()
11787 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
11795 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
11800 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
11801 bp->mf_config[vn] = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
11807 bp->mf_mode = MULTI_FUNCTION_SD; in bnx2x_get_hwinfo()
11808 bp->mf_sub_mode = SUB_MF_MODE_UFP; in bnx2x_get_hwinfo()
11809 bp->mf_config[vn] = in bnx2x_get_hwinfo()
11810 MF_CFG_RD(bp, in bnx2x_get_hwinfo()
11814 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
11817 val2 = SHMEM_RD(bp, in bnx2x_get_hwinfo()
11822 validate_set_si_mode(bp); in bnx2x_get_hwinfo()
11823 bp->mf_sub_mode = in bnx2x_get_hwinfo()
11828 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
11835 bp->mf_config[vn] = 0; in bnx2x_get_hwinfo()
11841 IS_MF(bp) ? "multi" : "single"); in bnx2x_get_hwinfo()
11843 switch (bp->mf_mode) { in bnx2x_get_hwinfo()
11845 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) & in bnx2x_get_hwinfo()
11848 bp->mf_ov = val; in bnx2x_get_hwinfo()
11849 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
11852 func, bp->mf_ov, bp->mf_ov); in bnx2x_get_hwinfo()
11853 } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) { in bnx2x_get_hwinfo()
11854 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11857 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
11859 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11874 dev_err(&bp->pdev->dev, in bnx2x_get_hwinfo()
11887 if (CHIP_MODE_IS_4_PORT(bp) && in bnx2x_get_hwinfo()
11888 !bp->path_has_ovlan && in bnx2x_get_hwinfo()
11889 !IS_MF(bp) && in bnx2x_get_hwinfo()
11890 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) { in bnx2x_get_hwinfo()
11891 u8 other_port = !BP_PORT(bp); in bnx2x_get_hwinfo()
11892 u8 other_func = BP_PATH(bp) + 2*other_port; in bnx2x_get_hwinfo()
11893 val = MF_CFG_RD(bp, in bnx2x_get_hwinfo()
11896 bp->path_has_ovlan = true; in bnx2x_get_hwinfo()
11901 if (CHIP_IS_E1H(bp) && IS_MF(bp)) in bnx2x_get_hwinfo()
11902 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT); in bnx2x_get_hwinfo()
11905 bnx2x_get_port_hwinfo(bp); in bnx2x_get_hwinfo()
11908 bnx2x_get_mac_hwinfo(bp); in bnx2x_get_hwinfo()
11910 bnx2x_get_cnic_info(bp); in bnx2x_get_hwinfo()
11915 static void bnx2x_read_fwinfo(struct bnx2x *bp) in bnx2x_read_fwinfo() argument
11925 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start); in bnx2x_read_fwinfo()
11926 memset(bp->fw_ver, 0, sizeof(bp->fw_ver)); in bnx2x_read_fwinfo()
11951 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN, in bnx2x_read_fwinfo()
11988 memcpy(bp->fw_ver, &vpd_data[rodi], len); in bnx2x_read_fwinfo()
11989 bp->fw_ver[len] = ' '; in bnx2x_read_fwinfo()
12000 static void bnx2x_set_modes_bitmap(struct bnx2x *bp) in bnx2x_set_modes_bitmap() argument
12004 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_set_modes_bitmap()
12006 else if (CHIP_REV_IS_EMUL(bp)) in bnx2x_set_modes_bitmap()
12011 if (CHIP_MODE_IS_4_PORT(bp)) in bnx2x_set_modes_bitmap()
12016 if (CHIP_IS_E2(bp)) in bnx2x_set_modes_bitmap()
12018 else if (CHIP_IS_E3(bp)) { in bnx2x_set_modes_bitmap()
12020 if (CHIP_REV(bp) == CHIP_REV_Ax) in bnx2x_set_modes_bitmap()
12026 if (IS_MF(bp)) { in bnx2x_set_modes_bitmap()
12028 switch (bp->mf_mode) { in bnx2x_set_modes_bitmap()
12047 INIT_MODE_FLAGS(bp) = flags; in bnx2x_set_modes_bitmap()
12050 static int bnx2x_init_bp(struct bnx2x *bp) in bnx2x_init_bp() argument
12055 mutex_init(&bp->port.phy_mutex); in bnx2x_init_bp()
12056 mutex_init(&bp->fw_mb_mutex); in bnx2x_init_bp()
12057 mutex_init(&bp->drv_info_mutex); in bnx2x_init_bp()
12058 sema_init(&bp->stats_lock, 1); in bnx2x_init_bp()
12059 bp->drv_info_mng_owner = false; in bnx2x_init_bp()
12061 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task); in bnx2x_init_bp()
12062 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task); in bnx2x_init_bp()
12063 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task); in bnx2x_init_bp()
12064 INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task); in bnx2x_init_bp()
12065 if (IS_PF(bp)) { in bnx2x_init_bp()
12066 rc = bnx2x_get_hwinfo(bp); in bnx2x_init_bp()
12070 eth_zero_addr(bp->dev->dev_addr); in bnx2x_init_bp()
12073 bnx2x_set_modes_bitmap(bp); in bnx2x_init_bp()
12075 rc = bnx2x_alloc_mem_bp(bp); in bnx2x_init_bp()
12079 bnx2x_read_fwinfo(bp); in bnx2x_init_bp()
12081 func = BP_FUNC(bp); in bnx2x_init_bp()
12084 if (IS_PF(bp) && !BP_NOMCP(bp)) { in bnx2x_init_bp()
12086 bp->fw_seq = in bnx2x_init_bp()
12087 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_init_bp()
12089 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq); in bnx2x_init_bp()
12091 rc = bnx2x_prev_unload(bp); in bnx2x_init_bp()
12093 bnx2x_free_mem_bp(bp); in bnx2x_init_bp()
12098 if (CHIP_REV_IS_FPGA(bp)) in bnx2x_init_bp()
12099 dev_err(&bp->pdev->dev, "FPGA detected\n"); in bnx2x_init_bp()
12101 if (BP_NOMCP(bp) && (func == 0)) in bnx2x_init_bp()
12102 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n"); in bnx2x_init_bp()
12104 bp->disable_tpa = disable_tpa; in bnx2x_init_bp()
12105 bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp); in bnx2x_init_bp()
12107 bp->disable_tpa |= is_kdump_kernel(); in bnx2x_init_bp()
12110 if (bp->disable_tpa) { in bnx2x_init_bp()
12111 bp->dev->hw_features &= ~NETIF_F_LRO; in bnx2x_init_bp()
12112 bp->dev->features &= ~NETIF_F_LRO; in bnx2x_init_bp()
12115 if (CHIP_IS_E1(bp)) in bnx2x_init_bp()
12116 bp->dropless_fc = 0; in bnx2x_init_bp()
12118 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp); in bnx2x_init_bp()
12120 bp->mrrs = mrrs; in bnx2x_init_bp()
12122 bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL; in bnx2x_init_bp()
12123 if (IS_VF(bp)) in bnx2x_init_bp()
12124 bp->rx_ring_size = MAX_RX_AVAIL; in bnx2x_init_bp()
12127 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12128 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR; in bnx2x_init_bp()
12130 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ; in bnx2x_init_bp()
12132 init_timer(&bp->timer); in bnx2x_init_bp()
12133 bp->timer.expires = jiffies + bp->current_interval; in bnx2x_init_bp()
12134 bp->timer.data = (unsigned long) bp; in bnx2x_init_bp()
12135 bp->timer.function = bnx2x_timer; in bnx2x_init_bp()
12137 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12138 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) && in bnx2x_init_bp()
12139 SHMEM2_RD(bp, dcbx_lldp_params_offset) && in bnx2x_init_bp()
12140 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) { in bnx2x_init_bp()
12141 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON); in bnx2x_init_bp()
12142 bnx2x_dcbx_init_params(bp); in bnx2x_init_bp()
12144 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF); in bnx2x_init_bp()
12147 if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12148 bp->cnic_base_cl_id = FP_SB_MAX_E1x; in bnx2x_init_bp()
12150 bp->cnic_base_cl_id = FP_SB_MAX_E2; in bnx2x_init_bp()
12153 if (IS_VF(bp)) in bnx2x_init_bp()
12154 bp->max_cos = 1; in bnx2x_init_bp()
12155 else if (CHIP_IS_E1x(bp)) in bnx2x_init_bp()
12156 bp->max_cos = BNX2X_MULTI_TX_COS_E1X; in bnx2x_init_bp()
12157 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp)) in bnx2x_init_bp()
12158 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0; in bnx2x_init_bp()
12159 else if (CHIP_IS_E3B0(bp)) in bnx2x_init_bp()
12160 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0; in bnx2x_init_bp()
12163 CHIP_NUM(bp), CHIP_REV(bp)); in bnx2x_init_bp()
12164 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos); in bnx2x_init_bp()
12170 if (IS_VF(bp)) in bnx2x_init_bp()
12171 bp->min_msix_vec_cnt = 1; in bnx2x_init_bp()
12172 else if (CNIC_SUPPORT(bp)) in bnx2x_init_bp()
12173 bp->min_msix_vec_cnt = 3; in bnx2x_init_bp()
12175 bp->min_msix_vec_cnt = 2; in bnx2x_init_bp()
12176 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt); in bnx2x_init_bp()
12178 bp->dump_preset_idx = 1; in bnx2x_init_bp()
12180 if (CHIP_IS_E3B0(bp)) in bnx2x_init_bp()
12181 bp->flags |= PTP_SUPPORTED; in bnx2x_init_bp()
12197 struct bnx2x *bp = netdev_priv(dev); in bnx2x_open() local
12200 bp->stats_init = true; in bnx2x_open()
12204 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_open()
12212 if (IS_PF(bp)) { in bnx2x_open()
12213 int other_engine = BP_PATH(bp) ? 0 : 1; in bnx2x_open()
12217 other_load_status = bnx2x_get_load_status(bp, other_engine); in bnx2x_open()
12218 load_status = bnx2x_get_load_status(bp, BP_PATH(bp)); in bnx2x_open()
12219 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) || in bnx2x_open()
12220 bnx2x_chk_parity_attn(bp, &global, true)) { in bnx2x_open()
12228 bnx2x_set_reset_global(bp); in bnx2x_open()
12237 bnx2x_trylock_leader_lock(bp) && in bnx2x_open()
12238 !bnx2x_leader_reset(bp)) { in bnx2x_open()
12239 netdev_info(bp->dev, in bnx2x_open()
12245 bnx2x_set_power_state(bp, PCI_D3hot); in bnx2x_open()
12246 bp->recovery_state = BNX2X_RECOVERY_FAILED; in bnx2x_open()
12256 bp->recovery_state = BNX2X_RECOVERY_DONE; in bnx2x_open()
12257 rc = bnx2x_nic_load(bp, LOAD_OPEN); in bnx2x_open()
12266 struct bnx2x *bp = netdev_priv(dev); in bnx2x_close() local
12269 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false); in bnx2x_close()
12274 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp, in bnx2x_init_mcast_macs_list() argument
12277 int mc_count = netdev_mc_count(bp->dev); in bnx2x_init_mcast_macs_list()
12287 netdev_for_each_mc_addr(ha, bp->dev) { in bnx2x_init_mcast_macs_list()
12316 static int bnx2x_set_uc_list(struct bnx2x *bp) in bnx2x_set_uc_list() argument
12319 struct net_device *dev = bp->dev; in bnx2x_set_uc_list()
12321 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj; in bnx2x_set_uc_list()
12325 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false); in bnx2x_set_uc_list()
12332 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true, in bnx2x_set_uc_list()
12350 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */, in bnx2x_set_uc_list()
12354 static int bnx2x_set_mc_list(struct bnx2x *bp) in bnx2x_set_mc_list() argument
12356 struct net_device *dev = bp->dev; in bnx2x_set_mc_list()
12360 rparam.mcast_obj = &bp->mcast_obj; in bnx2x_set_mc_list()
12363 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL); in bnx2x_set_mc_list()
12371 rc = bnx2x_init_mcast_macs_list(bp, &rparam); in bnx2x_set_mc_list()
12379 rc = bnx2x_config_mcast(bp, &rparam, in bnx2x_set_mc_list()
12394 struct bnx2x *bp = netdev_priv(dev); in bnx2x_set_rx_mode() local
12396 if (bp->state != BNX2X_STATE_OPEN) { in bnx2x_set_rx_mode()
12397 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state); in bnx2x_set_rx_mode()
12401 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE, in bnx2x_set_rx_mode()
12406 void bnx2x_set_rx_mode_inner(struct bnx2x *bp) in bnx2x_set_rx_mode_inner() argument
12410 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags); in bnx2x_set_rx_mode_inner()
12412 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12414 if (bp->dev->flags & IFF_PROMISC) { in bnx2x_set_rx_mode_inner()
12416 } else if ((bp->dev->flags & IFF_ALLMULTI) || in bnx2x_set_rx_mode_inner()
12417 ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) && in bnx2x_set_rx_mode_inner()
12418 CHIP_IS_E1(bp))) { in bnx2x_set_rx_mode_inner()
12421 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12423 if (bnx2x_set_mc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12427 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12428 if (bnx2x_set_uc_list(bp) < 0) in bnx2x_set_rx_mode_inner()
12430 netif_addr_lock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12435 bnx2x_schedule_sp_rtnl(bp, in bnx2x_set_rx_mode_inner()
12440 bp->rx_mode = rx_mode; in bnx2x_set_rx_mode_inner()
12442 if (IS_MF_ISCSI_ONLY(bp)) in bnx2x_set_rx_mode_inner()
12443 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_set_rx_mode_inner()
12446 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) { in bnx2x_set_rx_mode_inner()
12447 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state); in bnx2x_set_rx_mode_inner()
12448 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12452 if (IS_PF(bp)) { in bnx2x_set_rx_mode_inner()
12453 bnx2x_set_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12454 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12460 netif_addr_unlock_bh(bp->dev); in bnx2x_set_rx_mode_inner()
12461 bnx2x_vfpf_storm_rx_mode(bp); in bnx2x_set_rx_mode_inner()
12469 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_read() local
12479 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_read()
12480 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value); in bnx2x_mdio_read()
12481 bnx2x_release_phy_lock(bp); in bnx2x_mdio_read()
12493 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_mdio_write() local
12503 bnx2x_acquire_phy_lock(bp); in bnx2x_mdio_write()
12504 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value); in bnx2x_mdio_write()
12505 bnx2x_release_phy_lock(bp); in bnx2x_mdio_write()
12512 struct bnx2x *bp = netdev_priv(dev); in bnx2x_ioctl() local
12520 return bnx2x_hwtstamp_ioctl(bp, ifr); in bnx2x_ioctl()
12524 return mdio_mii_ioctl(&bp->mdio, mdio, cmd); in bnx2x_ioctl()
12531 struct bnx2x *bp = netdev_priv(dev); in poll_bnx2x() local
12534 for_each_eth_queue(bp, i) { in poll_bnx2x()
12535 struct bnx2x_fastpath *fp = &bp->fp[i]; in poll_bnx2x()
12536 napi_schedule(&bnx2x_fp(bp, fp->index, napi)); in poll_bnx2x()
12543 struct bnx2x *bp = netdev_priv(dev); in bnx2x_validate_addr() local
12546 if (IS_VF(bp)) in bnx2x_validate_addr()
12547 bnx2x_sample_bulletin(bp); in bnx2x_validate_addr()
12559 struct bnx2x *bp = netdev_priv(netdev); in bnx2x_get_phys_port_id() local
12561 if (!(bp->flags & HAS_PHYS_PORT_ID)) in bnx2x_get_phys_port_id()
12564 ppid->id_len = sizeof(bp->phys_port_id); in bnx2x_get_phys_port_id()
12565 memcpy(ppid->id, bp->phys_port_id, ppid->id_len); in bnx2x_get_phys_port_id()
12612 static int bnx2x_set_coherency_mask(struct bnx2x *bp) in bnx2x_set_coherency_mask() argument
12614 struct device *dev = &bp->pdev->dev; in bnx2x_set_coherency_mask()
12625 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp) in bnx2x_disable_pcie_error_reporting() argument
12627 if (bp->flags & AER_ENABLED) { in bnx2x_disable_pcie_error_reporting()
12628 pci_disable_pcie_error_reporting(bp->pdev); in bnx2x_disable_pcie_error_reporting()
12629 bp->flags &= ~AER_ENABLED; in bnx2x_disable_pcie_error_reporting()
12633 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev, in bnx2x_init_dev() argument
12644 bp->dev = dev; in bnx2x_init_dev()
12645 bp->pdev = pdev; in bnx2x_init_dev()
12649 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
12655 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
12661 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { in bnx2x_init_dev()
12662 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n"); in bnx2x_init_dev()
12678 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
12687 if (IS_PF(bp)) { in bnx2x_init_dev()
12689 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
12697 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n"); in bnx2x_init_dev()
12702 rc = bnx2x_set_coherency_mask(bp); in bnx2x_init_dev()
12712 bp->regview = pci_ioremap_bar(pdev, 0); in bnx2x_init_dev()
12713 if (!bp->regview) { in bnx2x_init_dev()
12714 dev_err(&bp->pdev->dev, in bnx2x_init_dev()
12726 bp->pf_num = PCI_FUNC(pdev->devfn); in bnx2x_init_dev()
12729 pci_read_config_dword(bp->pdev, in bnx2x_init_dev()
12731 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >> in bnx2x_init_dev()
12734 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num); in bnx2x_init_dev()
12737 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, in bnx2x_init_dev()
12746 bp->flags |= AER_ENABLED; in bnx2x_init_dev()
12754 if (IS_PF(bp)) { in bnx2x_init_dev()
12755 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
12756 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
12757 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
12758 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
12761 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
12762 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
12763 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
12764 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
12772 REG_WR(bp, in bnx2x_init_dev()
12779 bnx2x_set_ethtool_ops(bp, dev); in bnx2x_init_dev()
12812 bp->mdio.prtad = MDIO_PRTAD_NONE; in bnx2x_init_dev()
12813 bp->mdio.mmds = 0; in bnx2x_init_dev()
12814 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; in bnx2x_init_dev()
12815 bp->mdio.dev = dev; in bnx2x_init_dev()
12816 bp->mdio.mdio_read = bnx2x_mdio_read; in bnx2x_init_dev()
12817 bp->mdio.mdio_write = bnx2x_mdio_write; in bnx2x_init_dev()
12832 static int bnx2x_check_firmware(struct bnx2x *bp) in bnx2x_check_firmware() argument
12834 const struct firmware *firmware = bp->firmware; in bnx2x_check_firmware()
12956 bp->arr = kmalloc(len, GFP_KERNEL); \
12957 if (!bp->arr) \
12959 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12960 (u8 *)bp->arr, len); \
12963 static int bnx2x_init_firmware(struct bnx2x *bp) in bnx2x_init_firmware() argument
12969 if (bp->firmware) in bnx2x_init_firmware()
12972 if (CHIP_IS_E1(bp)) in bnx2x_init_firmware()
12974 else if (CHIP_IS_E1H(bp)) in bnx2x_init_firmware()
12976 else if (!CHIP_IS_E1x(bp)) in bnx2x_init_firmware()
12984 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); in bnx2x_init_firmware()
12991 rc = bnx2x_check_firmware(bp); in bnx2x_init_firmware()
12997 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data; in bnx2x_init_firmware()
13011 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13013 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13015 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13017 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13019 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13021 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13023 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13025 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data + in bnx2x_init_firmware()
13033 kfree(bp->init_ops_offsets); in bnx2x_init_firmware()
13035 kfree(bp->init_ops); in bnx2x_init_firmware()
13037 kfree(bp->init_data); in bnx2x_init_firmware()
13039 release_firmware(bp->firmware); in bnx2x_init_firmware()
13040 bp->firmware = NULL; in bnx2x_init_firmware()
13045 static void bnx2x_release_firmware(struct bnx2x *bp) in bnx2x_release_firmware() argument
13047 kfree(bp->init_ops_offsets); in bnx2x_release_firmware()
13048 kfree(bp->init_ops); in bnx2x_release_firmware()
13049 kfree(bp->init_data); in bnx2x_release_firmware()
13050 release_firmware(bp->firmware); in bnx2x_release_firmware()
13051 bp->firmware = NULL; in bnx2x_release_firmware()
13071 void bnx2x__init_func_obj(struct bnx2x *bp) in bnx2x__init_func_obj() argument
13074 bnx2x_setup_dmae(bp); in bnx2x__init_func_obj()
13076 bnx2x_init_func_obj(bp, &bp->func_obj, in bnx2x__init_func_obj()
13077 bnx2x_sp(bp, func_rdata), in bnx2x__init_func_obj()
13078 bnx2x_sp_mapping(bp, func_rdata), in bnx2x__init_func_obj()
13079 bnx2x_sp(bp, func_afex_rdata), in bnx2x__init_func_obj()
13080 bnx2x_sp_mapping(bp, func_afex_rdata), in bnx2x__init_func_obj()
13085 static int bnx2x_set_qm_cid_count(struct bnx2x *bp) in bnx2x_set_qm_cid_count() argument
13087 int cid_count = BNX2X_L2_MAX_CID(bp); in bnx2x_set_qm_cid_count()
13089 if (IS_SRIOV(bp)) in bnx2x_set_qm_cid_count()
13092 if (CNIC_SUPPORT(bp)) in bnx2x_set_qm_cid_count()
13192 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir, in bnx2x_send_update_drift_ramrod() argument
13203 func_params.f_obj = &bp->func_obj; in bnx2x_send_update_drift_ramrod()
13214 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_update_drift_ramrod()
13219 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjfreq() local
13227 if (!netif_running(bp->dev)) { in bnx2x_ptp_adjfreq()
13272 rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val, in bnx2x_ptp_adjfreq()
13287 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_adjtime() local
13291 timecounter_adjtime(&bp->timecounter, delta); in bnx2x_ptp_adjtime()
13298 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_gettime() local
13301 ns = timecounter_read(&bp->timecounter); in bnx2x_ptp_gettime()
13313 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_settime() local
13321 timecounter_init(&bp->timecounter, &bp->cyclecounter, ns); in bnx2x_ptp_settime()
13330 struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info); in bnx2x_ptp_enable() local
13336 static void bnx2x_register_phc(struct bnx2x *bp) in bnx2x_register_phc() argument
13339 bp->ptp_clock_info.owner = THIS_MODULE; in bnx2x_register_phc()
13340 snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name); in bnx2x_register_phc()
13341 bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */ in bnx2x_register_phc()
13342 bp->ptp_clock_info.n_alarm = 0; in bnx2x_register_phc()
13343 bp->ptp_clock_info.n_ext_ts = 0; in bnx2x_register_phc()
13344 bp->ptp_clock_info.n_per_out = 0; in bnx2x_register_phc()
13345 bp->ptp_clock_info.pps = 0; in bnx2x_register_phc()
13346 bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq; in bnx2x_register_phc()
13347 bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime; in bnx2x_register_phc()
13348 bp->ptp_clock_info.gettime64 = bnx2x_ptp_gettime; in bnx2x_register_phc()
13349 bp->ptp_clock_info.settime64 = bnx2x_ptp_settime; in bnx2x_register_phc()
13350 bp->ptp_clock_info.enable = bnx2x_ptp_enable; in bnx2x_register_phc()
13352 bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev); in bnx2x_register_phc()
13353 if (IS_ERR(bp->ptp_clock)) { in bnx2x_register_phc()
13354 bp->ptp_clock = NULL; in bnx2x_register_phc()
13363 struct bnx2x *bp; in bnx2x_init_one() local
13417 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count); in bnx2x_init_one()
13421 bp = netdev_priv(dev); in bnx2x_init_one()
13423 bp->flags = 0; in bnx2x_init_one()
13425 bp->flags |= IS_VF_FLAG; in bnx2x_init_one()
13427 bp->igu_sb_cnt = max_non_def_sbs; in bnx2x_init_one()
13428 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM; in bnx2x_init_one()
13429 bp->msg_enable = debug; in bnx2x_init_one()
13430 bp->cnic_support = cnic_cnt; in bnx2x_init_one()
13431 bp->cnic_probe = bnx2x_cnic_probe; in bnx2x_init_one()
13435 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data); in bnx2x_init_one()
13442 IS_PF(bp) ? "physical" : "virtual"); in bnx2x_init_one()
13443 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off"); in bnx2x_init_one()
13448 rc = bnx2x_init_bp(bp); in bnx2x_init_one()
13456 if (IS_VF(bp)) { in bnx2x_init_one()
13457 bp->doorbells = bnx2x_vf_doorbells(bp); in bnx2x_init_one()
13458 rc = bnx2x_vf_pci_alloc(bp); in bnx2x_init_one()
13462 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT); in bnx2x_init_one()
13464 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13469 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2), in bnx2x_init_one()
13472 if (!bp->doorbells) { in bnx2x_init_one()
13473 dev_err(&bp->pdev->dev, in bnx2x_init_one()
13479 if (IS_VF(bp)) { in bnx2x_init_one()
13480 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count); in bnx2x_init_one()
13486 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS); in bnx2x_init_one()
13491 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp); in bnx2x_init_one()
13492 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count); in bnx2x_init_one()
13495 if (CHIP_IS_E1x(bp)) in bnx2x_init_one()
13496 bp->flags |= NO_FCOE_FLAG; in bnx2x_init_one()
13499 bnx2x_set_num_queues(bp); in bnx2x_init_one()
13504 rc = bnx2x_set_int_mode(bp); in bnx2x_init_one()
13519 if (!NO_FCOE(bp)) { in bnx2x_init_one()
13522 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in bnx2x_init_one()
13525 if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) || in bnx2x_init_one()
13533 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4), in bnx2x_init_one()
13539 dev->base_addr, bp->pdev->irq, dev->dev_addr); in bnx2x_init_one()
13541 bnx2x_register_phc(bp); in bnx2x_init_one()
13546 bnx2x_disable_pcie_error_reporting(bp); in bnx2x_init_one()
13548 if (bp->regview) in bnx2x_init_one()
13549 iounmap(bp->regview); in bnx2x_init_one()
13551 if (IS_PF(bp) && bp->doorbells) in bnx2x_init_one()
13552 iounmap(bp->doorbells); in bnx2x_init_one()
13566 struct bnx2x *bp, in __bnx2x_remove() argument
13569 if (bp->ptp_clock) { in __bnx2x_remove()
13570 ptp_clock_unregister(bp->ptp_clock); in __bnx2x_remove()
13571 bp->ptp_clock = NULL; in __bnx2x_remove()
13575 if (!NO_FCOE(bp)) { in __bnx2x_remove()
13577 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN); in __bnx2x_remove()
13583 bnx2x_dcbnl_update_applist(bp, true); in __bnx2x_remove()
13586 if (IS_PF(bp) && in __bnx2x_remove()
13587 !BP_NOMCP(bp) && in __bnx2x_remove()
13588 (bp->flags & BC_SUPPORTS_RMMOD_CMD)) in __bnx2x_remove()
13589 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0); in __bnx2x_remove()
13600 bnx2x_iov_remove_one(bp); in __bnx2x_remove()
13603 if (IS_PF(bp)) { in __bnx2x_remove()
13604 bnx2x_set_power_state(bp, PCI_D0); in __bnx2x_remove()
13609 bnx2x_reset_endianity(bp); in __bnx2x_remove()
13613 bnx2x_disable_msi(bp); in __bnx2x_remove()
13616 if (IS_PF(bp)) in __bnx2x_remove()
13617 bnx2x_set_power_state(bp, PCI_D3hot); in __bnx2x_remove()
13620 cancel_delayed_work_sync(&bp->sp_rtnl_task); in __bnx2x_remove()
13623 if (IS_VF(bp)) in __bnx2x_remove()
13624 bnx2x_vfpf_release(bp); in __bnx2x_remove()
13628 pci_wake_from_d3(pdev, bp->wol); in __bnx2x_remove()
13632 bnx2x_disable_pcie_error_reporting(bp); in __bnx2x_remove()
13634 if (bp->regview) in __bnx2x_remove()
13635 iounmap(bp->regview); in __bnx2x_remove()
13640 if (IS_PF(bp)) { in __bnx2x_remove()
13641 if (bp->doorbells) in __bnx2x_remove()
13642 iounmap(bp->doorbells); in __bnx2x_remove()
13644 bnx2x_release_firmware(bp); in __bnx2x_remove()
13646 bnx2x_vf_pci_dealloc(bp); in __bnx2x_remove()
13648 bnx2x_free_mem_bp(bp); in __bnx2x_remove()
13662 struct bnx2x *bp; in bnx2x_remove_one() local
13668 bp = netdev_priv(dev); in bnx2x_remove_one()
13670 __bnx2x_remove(pdev, dev, bp, true); in bnx2x_remove_one()
13673 static int bnx2x_eeh_nic_unload(struct bnx2x *bp) in bnx2x_eeh_nic_unload() argument
13675 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT; in bnx2x_eeh_nic_unload()
13677 bp->rx_mode = BNX2X_RX_MODE_NONE; in bnx2x_eeh_nic_unload()
13679 if (CNIC_LOADED(bp)) in bnx2x_eeh_nic_unload()
13680 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD); in bnx2x_eeh_nic_unload()
13683 bnx2x_tx_disable(bp); in bnx2x_eeh_nic_unload()
13685 bnx2x_del_all_napi(bp); in bnx2x_eeh_nic_unload()
13686 if (CNIC_LOADED(bp)) in bnx2x_eeh_nic_unload()
13687 bnx2x_del_all_napi_cnic(bp); in bnx2x_eeh_nic_unload()
13688 netdev_reset_tc(bp->dev); in bnx2x_eeh_nic_unload()
13690 del_timer_sync(&bp->timer); in bnx2x_eeh_nic_unload()
13691 cancel_delayed_work_sync(&bp->sp_task); in bnx2x_eeh_nic_unload()
13692 cancel_delayed_work_sync(&bp->period_task); in bnx2x_eeh_nic_unload()
13694 if (!down_timeout(&bp->stats_lock, HZ / 10)) { in bnx2x_eeh_nic_unload()
13695 bp->stats_state = STATS_STATE_DISABLED; in bnx2x_eeh_nic_unload()
13696 up(&bp->stats_lock); in bnx2x_eeh_nic_unload()
13699 bnx2x_save_statistics(bp); in bnx2x_eeh_nic_unload()
13701 netif_carrier_off(bp->dev); in bnx2x_eeh_nic_unload()
13718 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_error_detected() local
13732 bnx2x_eeh_nic_unload(bp); in bnx2x_io_error_detected()
13734 bnx2x_prev_path_mark_eeh(bp); in bnx2x_io_error_detected()
13753 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_slot_reset() local
13770 bnx2x_set_power_state(bp, PCI_D0); in bnx2x_io_slot_reset()
13776 bnx2x_init_shmem(bp); in bnx2x_io_slot_reset()
13778 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) { in bnx2x_io_slot_reset()
13781 v = SHMEM2_RD(bp, in bnx2x_io_slot_reset()
13782 drv_capabilities_flag[BP_FW_MB_IDX(bp)]); in bnx2x_io_slot_reset()
13783 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)], in bnx2x_io_slot_reset()
13786 bnx2x_drain_tx_queues(bp); in bnx2x_io_slot_reset()
13787 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY); in bnx2x_io_slot_reset()
13788 bnx2x_netif_stop(bp, 1); in bnx2x_io_slot_reset()
13789 bnx2x_free_irq(bp); in bnx2x_io_slot_reset()
13792 bnx2x_send_unload_done(bp, true); in bnx2x_io_slot_reset()
13794 bp->sp_state = 0; in bnx2x_io_slot_reset()
13795 bp->port.pmf = 0; in bnx2x_io_slot_reset()
13797 bnx2x_prev_unload(bp); in bnx2x_io_slot_reset()
13802 bnx2x_squeeze_objects(bp); in bnx2x_io_slot_reset()
13803 bnx2x_free_skbs(bp); in bnx2x_io_slot_reset()
13804 for_each_rx_queue(bp, i) in bnx2x_io_slot_reset()
13805 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE); in bnx2x_io_slot_reset()
13806 bnx2x_free_fp_mem(bp); in bnx2x_io_slot_reset()
13807 bnx2x_free_mem(bp); in bnx2x_io_slot_reset()
13809 bp->state = BNX2X_STATE_CLOSED; in bnx2x_io_slot_reset()
13815 if (bp->flags & AER_ENABLED) { in bnx2x_io_slot_reset()
13835 struct bnx2x *bp = netdev_priv(dev); in bnx2x_io_resume() local
13837 if (bp->recovery_state != BNX2X_RECOVERY_DONE) { in bnx2x_io_resume()
13838 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n"); in bnx2x_io_resume()
13844 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & in bnx2x_io_resume()
13848 bnx2x_nic_load(bp, LOAD_NORMAL); in bnx2x_io_resume()
13864 struct bnx2x *bp; in bnx2x_shutdown() local
13869 bp = netdev_priv(dev); in bnx2x_shutdown()
13870 if (!bp) in bnx2x_shutdown()
13881 __bnx2x_remove(pdev, dev, bp, false); in bnx2x_shutdown()
13943 void bnx2x_notify_link_changed(struct bnx2x *bp) in bnx2x_notify_link_changed() argument
13945 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); in bnx2x_notify_link_changed()
13960 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp) in bnx2x_set_iscsi_eth_mac_addr() argument
13965 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac, in bnx2x_set_iscsi_eth_mac_addr()
13966 &bp->iscsi_l2_mac_obj, true, in bnx2x_set_iscsi_eth_mac_addr()
13971 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count) in bnx2x_cnic_sp_post() argument
13977 if (unlikely(bp->panic)) in bnx2x_cnic_sp_post()
13981 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
13982 BUG_ON(bp->cnic_spq_pending < count); in bnx2x_cnic_sp_post()
13983 bp->cnic_spq_pending -= count; in bnx2x_cnic_sp_post()
13985 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) { in bnx2x_cnic_sp_post()
13986 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type) in bnx2x_cnic_sp_post()
13989 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data) in bnx2x_cnic_sp_post()
13997 cxt_index = BNX2X_ISCSI_ETH_CID(bp) / in bnx2x_cnic_sp_post()
13999 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) - in bnx2x_cnic_sp_post()
14001 bnx2x_set_ctx_validation(bp, in bnx2x_cnic_sp_post()
14002 &bp->context[cxt_index]. in bnx2x_cnic_sp_post()
14004 BNX2X_ISCSI_ETH_CID(bp)); in bnx2x_cnic_sp_post()
14015 if (!atomic_read(&bp->cq_spq_left)) in bnx2x_cnic_sp_post()
14018 atomic_dec(&bp->cq_spq_left); in bnx2x_cnic_sp_post()
14020 if (!atomic_read(&bp->eq_spq_left)) in bnx2x_cnic_sp_post()
14023 atomic_dec(&bp->eq_spq_left); in bnx2x_cnic_sp_post()
14026 if (bp->cnic_spq_pending >= in bnx2x_cnic_sp_post()
14027 bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_post()
14030 bp->cnic_spq_pending++; in bnx2x_cnic_sp_post()
14037 spe = bnx2x_sp_get_next(bp); in bnx2x_cnic_sp_post()
14038 *spe = *bp->cnic_kwq_cons; in bnx2x_cnic_sp_post()
14041 bp->cnic_spq_pending, bp->cnic_kwq_pending, count); in bnx2x_cnic_sp_post()
14043 if (bp->cnic_kwq_cons == bp->cnic_kwq_last) in bnx2x_cnic_sp_post()
14044 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_cnic_sp_post()
14046 bp->cnic_kwq_cons++; in bnx2x_cnic_sp_post()
14048 bnx2x_sp_prod_update(bp); in bnx2x_cnic_sp_post()
14049 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_post()
14055 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_sp_queue() local
14059 if (unlikely(bp->panic)) { in bnx2x_cnic_sp_queue()
14065 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) && in bnx2x_cnic_sp_queue()
14066 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) { in bnx2x_cnic_sp_queue()
14071 spin_lock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14076 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT) in bnx2x_cnic_sp_queue()
14079 *bp->cnic_kwq_prod = *spe; in bnx2x_cnic_sp_queue()
14081 bp->cnic_kwq_pending++; in bnx2x_cnic_sp_queue()
14087 bp->cnic_kwq_pending); in bnx2x_cnic_sp_queue()
14089 if (bp->cnic_kwq_prod == bp->cnic_kwq_last) in bnx2x_cnic_sp_queue()
14090 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_cnic_sp_queue()
14092 bp->cnic_kwq_prod++; in bnx2x_cnic_sp_queue()
14095 spin_unlock_bh(&bp->spq_lock); in bnx2x_cnic_sp_queue()
14097 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending) in bnx2x_cnic_sp_queue()
14098 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_sp_queue()
14103 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send() argument
14108 mutex_lock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14109 c_ops = rcu_dereference_protected(bp->cnic_ops, in bnx2x_cnic_ctl_send()
14110 lockdep_is_held(&bp->cnic_mutex)); in bnx2x_cnic_ctl_send()
14112 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send()
14113 mutex_unlock(&bp->cnic_mutex); in bnx2x_cnic_ctl_send()
14118 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl) in bnx2x_cnic_ctl_send_bh() argument
14124 c_ops = rcu_dereference(bp->cnic_ops); in bnx2x_cnic_ctl_send_bh()
14126 rc = c_ops->cnic_ctl(bp->cnic_data, ctl); in bnx2x_cnic_ctl_send_bh()
14135 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd) in bnx2x_cnic_notify() argument
14141 return bnx2x_cnic_ctl_send(bp, &ctl); in bnx2x_cnic_notify()
14144 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err) in bnx2x_cnic_cfc_comp() argument
14153 bnx2x_cnic_ctl_send_bh(bp, &ctl); in bnx2x_cnic_cfc_comp()
14154 bnx2x_cnic_sp_post(bp, 0); in bnx2x_cnic_cfc_comp()
14162 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start) in bnx2x_set_iscsi_eth_rx_mode() argument
14165 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_set_iscsi_eth_rx_mode()
14181 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14186 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14188 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) in bnx2x_set_iscsi_eth_rx_mode()
14189 set_bit(sched_state, &bp->sp_state); in bnx2x_set_iscsi_eth_rx_mode()
14192 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0, in bnx2x_set_iscsi_eth_rx_mode()
14199 struct bnx2x *bp = netdev_priv(dev); in bnx2x_drv_ctl() local
14207 bnx2x_ilt_wr(bp, index, addr); in bnx2x_drv_ctl()
14214 bnx2x_cnic_sp_post(bp, count); in bnx2x_drv_ctl()
14220 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_drv_ctl()
14224 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14226 cp->iscsi_l2_cid, BP_FUNC(bp), in bnx2x_drv_ctl()
14227 bnx2x_sp(bp, mac_rdata), in bnx2x_drv_ctl()
14228 bnx2x_sp_mapping(bp, mac_rdata), in bnx2x_drv_ctl()
14230 &bp->sp_state, BNX2X_OBJ_TYPE_RX, in bnx2x_drv_ctl()
14231 &bp->macs_pool); in bnx2x_drv_ctl()
14234 rc = bnx2x_set_iscsi_eth_mac_addr(bp); in bnx2x_drv_ctl()
14244 bnx2x_set_iscsi_eth_rx_mode(bp, true); in bnx2x_drv_ctl()
14251 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14263 bnx2x_set_iscsi_eth_rx_mode(bp, false); in bnx2x_drv_ctl()
14270 if (!bnx2x_wait_sp_comp(bp, sp_bits)) in bnx2x_drv_ctl()
14277 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj, in bnx2x_drv_ctl()
14285 atomic_add(count, &bp->cq_spq_left); in bnx2x_drv_ctl()
14292 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14293 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14294 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14295 int path = BP_PATH(bp); in bnx2x_drv_ctl()
14296 int port = BP_PORT(bp); in bnx2x_drv_ctl()
14306 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14309 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) || in bnx2x_drv_ctl()
14310 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES))) in bnx2x_drv_ctl()
14314 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr); in bnx2x_drv_ctl()
14323 REG_WR(bp, scratch_offset + i, in bnx2x_drv_ctl()
14326 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14333 if (CHIP_IS_E3(bp)) { in bnx2x_drv_ctl()
14334 int idx = BP_FW_MB_IDX(bp); in bnx2x_drv_ctl()
14337 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]); in bnx2x_drv_ctl()
14342 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap); in bnx2x_drv_ctl()
14344 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_drv_ctl()
14356 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp) in bnx2x_setup_cnic_irq_info() argument
14358 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_irq_info()
14360 if (bp->flags & USING_MSIX_FLAG) { in bnx2x_setup_cnic_irq_info()
14363 cp->irq_arr[0].vector = bp->msix_table[1].vector; in bnx2x_setup_cnic_irq_info()
14368 if (!CHIP_IS_E1x(bp)) in bnx2x_setup_cnic_irq_info()
14369 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb; in bnx2x_setup_cnic_irq_info()
14371 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb; in bnx2x_setup_cnic_irq_info()
14373 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14374 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp); in bnx2x_setup_cnic_irq_info()
14375 cp->irq_arr[1].status_blk = bp->def_status_blk; in bnx2x_setup_cnic_irq_info()
14382 void bnx2x_setup_cnic_info(struct bnx2x *bp) in bnx2x_setup_cnic_info() argument
14384 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_setup_cnic_info()
14386 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_setup_cnic_info()
14387 bnx2x_cid_ilt_lines(bp); in bnx2x_setup_cnic_info()
14388 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_setup_cnic_info()
14389 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_setup_cnic_info()
14390 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_setup_cnic_info()
14393 BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid, in bnx2x_setup_cnic_info()
14396 if (NO_ISCSI_OOO(bp)) in bnx2x_setup_cnic_info()
14403 struct bnx2x *bp = netdev_priv(dev); in bnx2x_register_cnic() local
14404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_register_cnic()
14414 if (!CNIC_SUPPORT(bp)) { in bnx2x_register_cnic()
14419 if (!CNIC_LOADED(bp)) { in bnx2x_register_cnic()
14420 rc = bnx2x_load_cnic(bp); in bnx2x_register_cnic()
14427 bp->cnic_enabled = true; in bnx2x_register_cnic()
14429 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL); in bnx2x_register_cnic()
14430 if (!bp->cnic_kwq) in bnx2x_register_cnic()
14433 bp->cnic_kwq_cons = bp->cnic_kwq; in bnx2x_register_cnic()
14434 bp->cnic_kwq_prod = bp->cnic_kwq; in bnx2x_register_cnic()
14435 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT; in bnx2x_register_cnic()
14437 bp->cnic_spq_pending = 0; in bnx2x_register_cnic()
14438 bp->cnic_kwq_pending = 0; in bnx2x_register_cnic()
14440 bp->cnic_data = data; in bnx2x_register_cnic()
14444 cp->iro_arr = bp->iro_arr; in bnx2x_register_cnic()
14446 bnx2x_setup_cnic_irq_info(bp); in bnx2x_register_cnic()
14448 rcu_assign_pointer(bp->cnic_ops, ops); in bnx2x_register_cnic()
14451 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0); in bnx2x_register_cnic()
14458 struct bnx2x *bp = netdev_priv(dev); in bnx2x_unregister_cnic() local
14459 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_unregister_cnic()
14461 mutex_lock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
14463 RCU_INIT_POINTER(bp->cnic_ops, NULL); in bnx2x_unregister_cnic()
14464 mutex_unlock(&bp->cnic_mutex); in bnx2x_unregister_cnic()
14466 bp->cnic_enabled = false; in bnx2x_unregister_cnic()
14467 kfree(bp->cnic_kwq); in bnx2x_unregister_cnic()
14468 bp->cnic_kwq = NULL; in bnx2x_unregister_cnic()
14475 struct bnx2x *bp = netdev_priv(dev); in bnx2x_cnic_probe() local
14476 struct cnic_eth_dev *cp = &bp->cnic_eth_dev; in bnx2x_cnic_probe()
14482 if (NO_ISCSI(bp) && NO_FCOE(bp)) in bnx2x_cnic_probe()
14486 cp->chip_id = CHIP_ID(bp); in bnx2x_cnic_probe()
14487 cp->pdev = bp->pdev; in bnx2x_cnic_probe()
14488 cp->io_base = bp->regview; in bnx2x_cnic_probe()
14489 cp->io_base2 = bp->doorbells; in bnx2x_cnic_probe()
14492 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) + in bnx2x_cnic_probe()
14493 bnx2x_cid_ilt_lines(bp); in bnx2x_cnic_probe()
14495 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS; in bnx2x_cnic_probe()
14500 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp); in bnx2x_cnic_probe()
14502 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX); in bnx2x_cnic_probe()
14503 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp); in bnx2x_cnic_probe()
14505 if (NO_ISCSI_OOO(bp)) in bnx2x_cnic_probe()
14508 if (NO_ISCSI(bp)) in bnx2x_cnic_probe()
14511 if (NO_FCOE(bp)) in bnx2x_cnic_probe()
14525 struct bnx2x *bp = fp->bp; in bnx2x_rx_ustorm_prods_offset() local
14528 if (IS_VF(bp)) in bnx2x_rx_ustorm_prods_offset()
14529 return bnx2x_vf_ustorm_prods_offset(bp, fp); in bnx2x_rx_ustorm_prods_offset()
14530 else if (!CHIP_IS_E1x(bp)) in bnx2x_rx_ustorm_prods_offset()
14533 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); in bnx2x_rx_ustorm_prods_offset()
14543 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val) in bnx2x_pretend_func() argument
14547 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX) in bnx2x_pretend_func()
14551 pretend_reg = bnx2x_get_pretend_reg(bp); in bnx2x_pretend_func()
14552 REG_WR(bp, pretend_reg, pretend_func_val); in bnx2x_pretend_func()
14553 REG_RD(bp, pretend_reg); in bnx2x_pretend_func()
14559 struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task); in bnx2x_ptp_task() local
14560 int port = BP_PORT(bp); in bnx2x_ptp_task()
14566 val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
14570 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB : in bnx2x_ptp_task()
14573 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB : in bnx2x_ptp_task()
14576 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
14578 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_ptp_task()
14582 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps); in bnx2x_ptp_task()
14583 dev_kfree_skb_any(bp->ptp_tx_skb); in bnx2x_ptp_task()
14584 bp->ptp_tx_skb = NULL; in bnx2x_ptp_task()
14591 schedule_work(&bp->ptp_task); in bnx2x_ptp_task()
14595 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb) in bnx2x_set_rx_ts() argument
14597 int port = BP_PORT(bp); in bnx2x_set_rx_ts()
14600 timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB : in bnx2x_set_rx_ts()
14603 timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB : in bnx2x_set_rx_ts()
14607 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_set_rx_ts()
14610 ns = timecounter_cyc2time(&bp->timecounter, timestamp); in bnx2x_set_rx_ts()
14621 struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter); in bnx2x_cyclecounter_read() local
14622 int port = BP_PORT(bp); in bnx2x_cyclecounter_read()
14626 REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 : in bnx2x_cyclecounter_read()
14636 static void bnx2x_init_cyclecounter(struct bnx2x *bp) in bnx2x_init_cyclecounter() argument
14638 memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter)); in bnx2x_init_cyclecounter()
14639 bp->cyclecounter.read = bnx2x_cyclecounter_read; in bnx2x_init_cyclecounter()
14640 bp->cyclecounter.mask = CYCLECOUNTER_MASK(64); in bnx2x_init_cyclecounter()
14641 bp->cyclecounter.shift = 1; in bnx2x_init_cyclecounter()
14642 bp->cyclecounter.mult = 1; in bnx2x_init_cyclecounter()
14645 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp) in bnx2x_send_reset_timesync_ramrod() argument
14655 func_params.f_obj = &bp->func_obj; in bnx2x_send_reset_timesync_ramrod()
14662 return bnx2x_func_state_change(bp, &func_params); in bnx2x_send_reset_timesync_ramrod()
14665 static int bnx2x_enable_ptp_packets(struct bnx2x *bp) in bnx2x_enable_ptp_packets() argument
14680 for_each_eth_queue(bp, i) { in bnx2x_enable_ptp_packets()
14681 struct bnx2x_fastpath *fp = &bp->fp[i]; in bnx2x_enable_ptp_packets()
14684 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj; in bnx2x_enable_ptp_packets()
14687 rc = bnx2x_queue_state_change(bp, &q_params); in bnx2x_enable_ptp_packets()
14697 int bnx2x_configure_ptp_filters(struct bnx2x *bp) in bnx2x_configure_ptp_filters() argument
14699 int port = BP_PORT(bp); in bnx2x_configure_ptp_filters()
14702 if (!bp->hwtstamp_ioctl_called) in bnx2x_configure_ptp_filters()
14705 switch (bp->tx_type) { in bnx2x_configure_ptp_filters()
14707 bp->flags |= TX_TIMESTAMPING_EN; in bnx2x_configure_ptp_filters()
14708 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14710 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14718 switch (bp->rx_filter) { in bnx2x_configure_ptp_filters()
14723 bp->rx_filter = HWTSTAMP_FILTER_NONE; in bnx2x_configure_ptp_filters()
14728 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; in bnx2x_configure_ptp_filters()
14730 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14732 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14738 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; in bnx2x_configure_ptp_filters()
14740 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14742 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14748 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; in bnx2x_configure_ptp_filters()
14750 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14752 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14759 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; in bnx2x_configure_ptp_filters()
14761 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
14763 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
14769 rc = bnx2x_enable_ptp_packets(bp); in bnx2x_configure_ptp_filters()
14774 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp_filters()
14780 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr) in bnx2x_hwtstamp_ioctl() argument
14798 bp->hwtstamp_ioctl_called = 1; in bnx2x_hwtstamp_ioctl()
14799 bp->tx_type = config.tx_type; in bnx2x_hwtstamp_ioctl()
14800 bp->rx_filter = config.rx_filter; in bnx2x_hwtstamp_ioctl()
14802 rc = bnx2x_configure_ptp_filters(bp); in bnx2x_hwtstamp_ioctl()
14806 config.rx_filter = bp->rx_filter; in bnx2x_hwtstamp_ioctl()
14813 static int bnx2x_configure_ptp(struct bnx2x *bp) in bnx2x_configure_ptp() argument
14815 int rc, port = BP_PORT(bp); in bnx2x_configure_ptp()
14819 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
14821 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
14823 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
14825 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
14829 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp()
14833 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_configure_ptp()
14839 REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2); in bnx2x_configure_ptp()
14842 rc = bnx2x_send_reset_timesync_ramrod(bp); in bnx2x_configure_ptp()
14849 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_configure_ptp()
14851 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_configure_ptp()
14858 void bnx2x_init_ptp(struct bnx2x *bp) in bnx2x_init_ptp() argument
14863 rc = bnx2x_configure_ptp(bp); in bnx2x_init_ptp()
14870 INIT_WORK(&bp->ptp_task, bnx2x_ptp_task); in bnx2x_init_ptp()
14876 if (!bp->timecounter_init_done) { in bnx2x_init_ptp()
14877 bnx2x_init_cyclecounter(bp); in bnx2x_init_ptp()
14878 timecounter_init(&bp->timecounter, &bp->cyclecounter, in bnx2x_init_ptp()
14880 bp->timecounter_init_done = 1; in bnx2x_init_ptp()