13040 #define TG3_FL_NOT_5705	0x2  in tg3_test_registers()  macro
13047 		{ MAC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13051 		{ MAC_STATUS, TG3_FL_NOT_5705,  in tg3_test_registers()
13065 		{ MAC_RX_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13079 		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,  in tg3_test_registers()
13081 		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13083 		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,  in tg3_test_registers()
13085 		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,  in tg3_test_registers()
13097 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13101 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13105 		{ HOSTCC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13109 		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13113 		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13117 		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13121 		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13125 		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13127 		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13129 		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13133 		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13137 		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13139 		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13141 		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13163 		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13165 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,  in tg3_test_registers()
13171 		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13189 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))  in tg3_test_registers()