Lines Matching refs:XGMAC_DMA_CONTROL
99 #define XGMAC_DMA_CONTROL 0x00000f18 /* Ctrl (Operational Mode) */ macro
604 value = readl(ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_enable()
606 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_enable()
611 u32 value = readl(ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_disable()
613 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_disable()
926 reg = readl(priv->base + XGMAC_DMA_CONTROL); in xgmac_tx_timeout_work()
927 writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); in xgmac_tx_timeout_work()
937 writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL); in xgmac_tx_timeout_work()
991 writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL); in xgmac_hw_init()
1893 value = readl(priv->base + XGMAC_DMA_CONTROL); in xgmac_suspend()
1895 writel(value, priv->base + XGMAC_DMA_CONTROL); in xgmac_suspend()