Lines Matching refs:XGMAC_DMA_INTR_ENA
100 #define XGMAC_DMA_INTR_ENA 0x00000f1c /* Interrupt Enable */ macro
922 writel(0, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_tx_timeout_work()
949 writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_tx_timeout_work()
977 writel(0, ioaddr + XGMAC_DMA_INTR_ENA); in xgmac_hw_init()
1047 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); in xgmac_open()
1062 if (readl(priv->base + XGMAC_DMA_INTR_ENA)) in xgmac_stop()
1065 writel(0, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_stop()
1251 __raw_writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_poll()
1412 intr_status &= __raw_readl(priv->base + XGMAC_DMA_INTR_ENA); in xgmac_interrupt()
1445 __raw_writel(DMA_INTR_ABNORMAL, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_interrupt()
1765 writel(0, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_probe()
1889 writel(0, priv->base + XGMAC_DMA_INTR_ENA); in xgmac_suspend()
1918 writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA); in xgmac_resume()