97 static int pmread(struct cmac *cmac, u32 reg, u32 * data32)  in pmread()  argument
99 	t1_tpi_read(cmac->adapter, OFFSET(reg), data32);  in pmread()
103 static int pmwrite(struct cmac *cmac, u32 reg, u32 data32)  in pmwrite()  argument
105 	t1_tpi_write(cmac->adapter, OFFSET(reg), data32);  in pmwrite()
110 static int pm3393_reset(struct cmac *cmac)  in pm3393_reset()  argument
123 static int pm3393_interrupt_enable(struct cmac *cmac)  in pm3393_interrupt_enable()  argument
129 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
130 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
131 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
132 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
135 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);  in pm3393_interrupt_enable()
136 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);  in pm3393_interrupt_enable()
137 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);  in pm3393_interrupt_enable()
138 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);  in pm3393_interrupt_enable()
140 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0xffff);  in pm3393_interrupt_enable()
141 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0xffff);  in pm3393_interrupt_enable()
142 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
143 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0xffff);  in pm3393_interrupt_enable()
144 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0xffff);  in pm3393_interrupt_enable()
145 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0xffff);  in pm3393_interrupt_enable()
146 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0xffff);  in pm3393_interrupt_enable()
147 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0xffff);  in pm3393_interrupt_enable()
148 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0xffff);  in pm3393_interrupt_enable()
153 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE,  in pm3393_interrupt_enable()
157 	pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE);  in pm3393_interrupt_enable()
159 	writel(pl_intr, cmac->adapter->regs + A_PL_ENABLE);  in pm3393_interrupt_enable()
163 static int pm3393_interrupt_disable(struct cmac *cmac)  in pm3393_interrupt_disable()  argument
168 	pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
169 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
170 	pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
171 	pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
172 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0);  in pm3393_interrupt_disable()
173 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0);  in pm3393_interrupt_disable()
174 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_2, 0);  in pm3393_interrupt_disable()
175 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_3, 0);  in pm3393_interrupt_disable()
176 	pmwrite(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_ENABLE, 0);  in pm3393_interrupt_disable()
177 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT_MASK, 0);  in pm3393_interrupt_disable()
178 	pmwrite(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
179 	pmwrite(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
180 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_3, 0);  in pm3393_interrupt_disable()
181 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_MASK, 0);  in pm3393_interrupt_disable()
182 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_3, 0);  in pm3393_interrupt_disable()
183 	pmwrite(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT_MASK, 0);  in pm3393_interrupt_disable()
184 	pmwrite(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_ENABLE, 0);  in pm3393_interrupt_disable()
187 	pmwrite(cmac, SUNI1x10GEXP_REG_GLOBAL_INTERRUPT_ENABLE, 0);  in pm3393_interrupt_disable()
190 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_ENABLE, &elmer);  in pm3393_interrupt_disable()
192 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_ENABLE, elmer);  in pm3393_interrupt_disable()
202 static int pm3393_interrupt_clear(struct cmac *cmac)  in pm3393_interrupt_clear()  argument
211 	pmread(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
212 	pmread(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
213 	pmread(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
214 	pmread(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
215 	pmread(cmac, SUNI1x10GEXP_REG_PL4ODP_INTERRUPT, &val32);  in pm3393_interrupt_clear()
216 	pmread(cmac, SUNI1x10GEXP_REG_XTEF_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
217 	pmread(cmac, SUNI1x10GEXP_REG_IFLX_FIFO_OVERFLOW_INTERRUPT, &val32);  in pm3393_interrupt_clear()
218 	pmread(cmac, SUNI1x10GEXP_REG_TXOAM_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
219 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_INTERRUPT, &val32);  in pm3393_interrupt_clear()
220 	pmread(cmac, SUNI1x10GEXP_REG_TXXG_INTERRUPT, &val32);  in pm3393_interrupt_clear()
221 	pmread(cmac, SUNI1x10GEXP_REG_PL4IDU_INTERRUPT, &val32);  in pm3393_interrupt_clear()
222 	pmread(cmac, SUNI1x10GEXP_REG_EFLX_FIFO_OVERFLOW_ERROR_INDICATION,  in pm3393_interrupt_clear()
224 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_STATUS, &val32);  in pm3393_interrupt_clear()
225 	pmread(cmac, SUNI1x10GEXP_REG_PL4IO_LOCK_DETECT_CHANGE, &val32);  in pm3393_interrupt_clear()
229 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS, &val32);  in pm3393_interrupt_clear()
233 	t1_tpi_read(cmac->adapter, A_ELMER0_INT_CAUSE, &elmer);  in pm3393_interrupt_clear()
235 	t1_tpi_write(cmac->adapter, A_ELMER0_INT_CAUSE, elmer);  in pm3393_interrupt_clear()
239 	pl_intr = readl(cmac->adapter->regs + A_PL_CAUSE);  in pm3393_interrupt_clear()
241 	writel(pl_intr, cmac->adapter->regs + A_PL_CAUSE);  in pm3393_interrupt_clear()
247 static int pm3393_interrupt_handler(struct cmac *cmac)  in pm3393_interrupt_handler()  argument
252 	pmread(cmac, SUNI1x10GEXP_REG_MASTER_INTERRUPT_STATUS,  in pm3393_interrupt_handler()
254 	if (netif_msg_intr(cmac->adapter))  in pm3393_interrupt_handler()
255 		dev_dbg(&cmac->adapter->pdev->dev, "PM3393 intr cause 0x%x\n",  in pm3393_interrupt_handler()
259 	pm3393_interrupt_clear(cmac);  in pm3393_interrupt_handler()
264 static int pm3393_enable(struct cmac *cmac, int which)  in pm3393_enable()  argument
267 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1,  in pm3393_enable()
273 		if (cmac->instance->fc & PAUSE_RX)  in pm3393_enable()
275 		if (cmac->instance->fc & PAUSE_TX)  in pm3393_enable()
277 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, val);  in pm3393_enable()
280 	cmac->instance->enabled |= which;  in pm3393_enable()
284 static int pm3393_enable_port(struct cmac *cmac, int which)  in pm3393_enable_port()  argument
287 	pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_CONTROL,  in pm3393_enable_port()
290 	memset(&cmac->stats, 0, sizeof(struct cmac_statistics));  in pm3393_enable_port()
292 	pm3393_enable(cmac, which);  in pm3393_enable_port()
299 	t1_link_changed(cmac->adapter, 0);  in pm3393_enable_port()
303 static int pm3393_disable(struct cmac *cmac, int which)  in pm3393_disable()  argument
306 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_CONFIG_1, RXXG_CONF1_VAL);  in pm3393_disable()
308 		pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_CONFIG_1, TXXG_CONF1_VAL);  in pm3393_disable()
316 	cmac->instance->enabled &= ~which;  in pm3393_disable()
320 static int pm3393_loopback_enable(struct cmac *cmac)  in pm3393_loopback_enable()  argument
325 static int pm3393_loopback_disable(struct cmac *cmac)  in pm3393_loopback_disable()  argument
330 static int pm3393_set_mtu(struct cmac *cmac, int mtu)  in pm3393_set_mtu()  argument
332 	int enabled = cmac->instance->enabled;  in pm3393_set_mtu()
341 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);  in pm3393_set_mtu()
343 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MAX_FRAME_LENGTH, mtu);  in pm3393_set_mtu()
344 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_MAX_FRAME_SIZE, mtu);  in pm3393_set_mtu()
347 		pm3393_enable(cmac, enabled);  in pm3393_set_mtu()
351 static int pm3393_set_rx_mode(struct cmac *cmac, struct t1_rx_mode *rm)  in pm3393_set_rx_mode()  argument
353 	int enabled = cmac->instance->enabled & MAC_DIRECTION_RX;  in pm3393_set_rx_mode()
358 		pm3393_disable(cmac, MAC_DIRECTION_RX);  in pm3393_set_rx_mode()
360 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, &rx_mode);  in pm3393_set_rx_mode()
363 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2,  in pm3393_set_rx_mode()
372 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, 0xffff);  in pm3393_set_rx_mode()
373 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, 0xffff);  in pm3393_set_rx_mode()
374 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, 0xffff);  in pm3393_set_rx_mode()
375 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, 0xffff);  in pm3393_set_rx_mode()
388 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_LOW, mc_filter[0]);  in pm3393_set_rx_mode()
389 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDLOW, mc_filter[1]);  in pm3393_set_rx_mode()
390 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_MIDHIGH, mc_filter[2]);  in pm3393_set_rx_mode()
391 		pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_MULTICAST_HASH_HIGH, mc_filter[3]);  in pm3393_set_rx_mode()
395 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_2, (u16)rx_mode);  in pm3393_set_rx_mode()
398 		pm3393_enable(cmac, MAC_DIRECTION_RX);  in pm3393_set_rx_mode()
403 static int pm3393_get_speed_duplex_fc(struct cmac *cmac, int *speed,  in pm3393_get_speed_duplex_fc()  argument
411 		*fc = cmac->instance->fc;  in pm3393_get_speed_duplex_fc()
415 static int pm3393_set_speed_duplex_fc(struct cmac *cmac, int speed, int duplex,  in pm3393_set_speed_duplex_fc()  argument
425 	if (fc != cmac->instance->fc) {  in pm3393_set_speed_duplex_fc()
426 		cmac->instance->fc = (u8) fc;  in pm3393_set_speed_duplex_fc()
427 		if (cmac->instance->enabled & MAC_DIRECTION_TX)  in pm3393_set_speed_duplex_fc()
428 			pm3393_enable(cmac, MAC_DIRECTION_TX);  in pm3393_set_speed_duplex_fc()
448 static const struct cmac_statistics *pm3393_update_statistics(struct cmac *mac,  in pm3393_update_statistics()
499 static int pm3393_macaddress_get(struct cmac *cmac, u8 mac_addr[6])  in pm3393_macaddress_get()  argument
501 	memcpy(mac_addr, cmac->instance->mac_addr, ETH_ALEN);  in pm3393_macaddress_get()
505 static int pm3393_macaddress_set(struct cmac *cmac, u8 ma[6])  in pm3393_macaddress_set()  argument
507 	u32 val, lo, mid, hi, enabled = cmac->instance->enabled;  in pm3393_macaddress_set()
528 	memcpy(cmac->instance->mac_addr, ma, ETH_ALEN);  in pm3393_macaddress_set()
536 		pm3393_disable(cmac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);  in pm3393_macaddress_set()
539 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_15_0, lo);  in pm3393_macaddress_set()
540 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_31_16, mid);  in pm3393_macaddress_set()
541 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_SA_47_32, hi);  in pm3393_macaddress_set()
544 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_15_0, lo);  in pm3393_macaddress_set()
545 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_31_16, mid);  in pm3393_macaddress_set()
546 	pmwrite(cmac, SUNI1x10GEXP_REG_TXXG_SA_47_32, hi);  in pm3393_macaddress_set()
552 	pmread(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, &val);  in pm3393_macaddress_set()
554 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);  in pm3393_macaddress_set()
556 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_LOW, lo);  in pm3393_macaddress_set()
557 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_MID, mid);  in pm3393_macaddress_set()
558 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_EXACT_MATCH_ADDR_1_HIGH, hi);  in pm3393_macaddress_set()
561 	pmwrite(cmac, SUNI1x10GEXP_REG_RXXG_ADDRESS_FILTER_CONTROL_0, val);  in pm3393_macaddress_set()
564 		pm3393_enable(cmac, enabled);  in pm3393_macaddress_set()
568 static void pm3393_destroy(struct cmac *cmac)  in pm3393_destroy()  argument
570 	kfree(cmac);  in pm3393_destroy()
593 static struct cmac *pm3393_mac_create(adapter_t *adapter, int index)  in pm3393_mac_create()
595 	struct cmac *cmac;  in pm3393_mac_create()  local
597 	cmac = kzalloc(sizeof(*cmac) + sizeof(cmac_instance), GFP_KERNEL);  in pm3393_mac_create()
598 	if (!cmac)  in pm3393_mac_create()
601 	cmac->ops = &pm3393_ops;  in pm3393_mac_create()
602 	cmac->instance = (cmac_instance *) (cmac + 1);  in pm3393_mac_create()
603 	cmac->adapter = adapter;  in pm3393_mac_create()
604 	cmac->instance->fc = PAUSE_TX | PAUSE_RX;  in pm3393_mac_create()
687 	return cmac;  in pm3393_mac_create()