Lines Matching refs:params
155 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
353 if (is_t4(adap->params.chip)) { in t4_mc_read()
406 if (is_t4(adap->params.chip)) { in t4_edc_read()
515 if (is_t4(adap->params.chip)) in t4_memory_rw()
517 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->fn); in t4_memory_rw()
636 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip); in t4_get_regs_len()
1315 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
1605 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) in t4_read_flash()
1643 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) in t4_write_flash()
1879 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
1880 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
1898 if (end >= adapter->params.sf_nsec) in t4_flash_erase_sectors()
1926 if (adapter->params.sf_size == 0x100000) in t4_flash_cfg_addr()
1943 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
1944 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5)) in t4_fw_matches_chip()
1949 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
1969 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
1970 unsigned int fw_img_start = adap->params.sf_fw_start; in t4_load_fw()
2037 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
2300 if (is_t4(adapter->params.chip)) in pcie_intr_handler()
2649 if (is_t4(adapter->params.chip)) { in mem_intr_handler()
2694 if (is_t5(adap->params.chip)) in ma_intr_handler()
2751 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
2828 if (!is_t4(adapter->params.chip) && (cause & MC1_S)) in t4_slow_intr_handler()
3365 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
3392 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
3467 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
3549 if (is_t4(adap->params.chip)) { in t4_wol_magic_enable()
3591 if (is_t4(adap->params.chip)) in t4_wol_pat_enable()
3604 (is_t4(adap->params.chip) ? \ in t4_wol_pat_enable()
3825 if (is_t4(adapter->params.chip)) { in t4_sge_decode_idma_state()
4226 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
4337 unsigned int vf, unsigned int nparams, const u32 *params, in t4_query_params() argument
4353 *p = htonl(*params++); in t4_query_params()
4378 unsigned int nparams, const u32 *params, in t4_set_params_nosleep() argument
4395 *p++ = cpu_to_be32(*params++); in t4_set_params_nosleep()
4416 unsigned int vf, unsigned int nparams, const u32 *params, in t4_set_params() argument
4431 *p++ = htonl(*params++); in t4_set_params()
4612 unsigned int max_naddr = is_t4(adap->params.chip) ? in t4_alloc_mac_filt()
4674 unsigned int max_mac_addr = is_t4(adap->params.chip) ? in t4_change_mac()
5021 adap->params.sf_size = supported_flash[ret].size_mb; in get_flash_params()
5022 adap->params.sf_nsec = in get_flash_params()
5023 adap->params.sf_size / SF_SEC_SIZE; in get_flash_params()
5031 adap->params.sf_nsec = 1 << (info - 16); in get_flash_params()
5033 adap->params.sf_nsec = 64; in get_flash_params()
5036 adap->params.sf_size = 1 << info; in get_flash_params()
5037 adap->params.sf_fw_start = in get_flash_params()
5040 if (adap->params.sf_size < FLASH_MIN_SIZE) in get_flash_params()
5042 adap->params.sf_size, FLASH_MIN_SIZE); in get_flash_params()
5061 get_pci_mode(adapter, &adapter->params.pci); in t4_prep_adapter()
5074 adapter->params.chip = 0; in t4_prep_adapter()
5077 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); in t4_prep_adapter()
5080 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); in t4_prep_adapter()
5088 adapter->params.cim_la_size = CIMLA_SIZE; in t4_prep_adapter()
5089 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); in t4_prep_adapter()
5094 adapter->params.nports = 1; in t4_prep_adapter()
5095 adapter->params.portvec = 1; in t4_prep_adapter()
5096 adapter->params.vpd.cclk = 50000; in t4_prep_adapter()
5137 if (is_t4(adapter->params.chip)) in cxgb4_t4_bar2_sge_qregs()
5142 page_shift = adapter->params.sge.hps + 10; in cxgb4_t4_bar2_sge_qregs()
5148 ? adapter->params.sge.eq_qpp in cxgb4_t4_bar2_sge_qregs()
5149 : adapter->params.sge.iq_qpp); in cxgb4_t4_bar2_sge_qregs()
5198 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
5250 struct sge_params *sge_params = &adapter->params.sge; in t4_init_sge_params()
5285 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
5286 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
5290 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
5296 &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
5299 &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
5306 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
5307 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
5308 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
5309 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
5315 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
5316 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
5332 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
5390 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
5448 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
5527 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
5647 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
5692 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
5704 val |= adap->params.tp.la_mask; in t4_tp_read_la()
5718 cfg | adap->params.tp.la_mask); in t4_tp_read_la()