Lines Matching refs:lp
16 #define DE4X5_BMR iobase+(0x000 << lp->bus) /* Bus Mode Register */
17 #define DE4X5_TPD iobase+(0x008 << lp->bus) /* Transmit Poll Demand Reg */
18 #define DE4X5_RPD iobase+(0x010 << lp->bus) /* Receive Poll Demand Reg */
19 #define DE4X5_RRBA iobase+(0x018 << lp->bus) /* RX Ring Base Address Reg */
20 #define DE4X5_TRBA iobase+(0x020 << lp->bus) /* TX Ring Base Address Reg */
21 #define DE4X5_STS iobase+(0x028 << lp->bus) /* Status Register */
22 #define DE4X5_OMR iobase+(0x030 << lp->bus) /* Operation Mode Register */
23 #define DE4X5_IMR iobase+(0x038 << lp->bus) /* Interrupt Mask Register */
24 #define DE4X5_MFC iobase+(0x040 << lp->bus) /* Missed Frame Counter */
25 #define DE4X5_APROM iobase+(0x048 << lp->bus) /* Ethernet Address PROM */
26 #define DE4X5_BROM iobase+(0x048 << lp->bus) /* Boot ROM Register */
27 #define DE4X5_SROM iobase+(0x048 << lp->bus) /* Serial ROM Register */
28 #define DE4X5_MII iobase+(0x048 << lp->bus) /* MII Interface Register */
29 #define DE4X5_DDR iobase+(0x050 << lp->bus) /* Data Diagnostic Register */
30 #define DE4X5_FDR iobase+(0x058 << lp->bus) /* Full Duplex Register */
31 #define DE4X5_GPT iobase+(0x058 << lp->bus) /* General Purpose Timer Reg.*/
32 #define DE4X5_GEP iobase+(0x060 << lp->bus) /* General Purpose Register */
33 #define DE4X5_SISR iobase+(0x060 << lp->bus) /* SIA Status Register */
34 #define DE4X5_SICR iobase+(0x068 << lp->bus) /* SIA Connectivity Register */
35 #define DE4X5_STRR iobase+(0x070 << lp->bus) /* SIA TX/RX Register */
36 #define DE4X5_SIGR iobase+(0x078 << lp->bus) /* SIA General Register */
922 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
924 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
925 mii_wr(MII_CR_10|(lp->fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
927 omr |= ((lp->fdx ? OMR_FDX : 0) | OMR_TTM);\
929 if (!lp->useSROM) lp->cache.gep = 0;\
930 } else if (lp->useSROM && !lp->useMII) {\
932 omr |= (lp->fdx ? OMR_FDX : 0);\
933 outl(omr | (lp->infoblock_csr6 & ~(OMR_SCR | OMR_HBD)), DE4X5_OMR);\
936 omr |= (lp->fdx ? OMR_FDX : 0);\
938 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD);\
939 gep_wr(lp->cache.gep, dev);\
944 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
946 if (lp->phy[lp->active].id == NATIONAL_TX) {\
947 mii_wr(mii_rd(0x18, lp->phy[lp->active].addr, DE4X5_MII) & ~0x2000,\
948 0x18, lp->phy[lp->active].addr, DE4X5_MII);\
951 sr = mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);\
952 if (!(sr & MII_ANA_T4AM) && lp->fdx) fdx=1;\
953 if ((lp->tmp != MII_SR_ASSC) || (lp->autosense != AUTO)) {\
954 mii_wr(MII_CR_100|(fdx?MII_CR_FDM:0), MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
958 if (!lp->useSROM) lp->cache.gep = 0;\
959 } else if (lp->useSROM && !lp->useMII) {\
961 omr |= (lp->fdx ? OMR_FDX : 0);\
962 outl(omr | lp->infoblock_csr6, DE4X5_OMR);\
965 omr |= (lp->fdx ? OMR_FDX : 0);\
967 lp->cache.gep = (lp->fdx ? 0 : GEP_FDXD) | GEP_MODE;\
968 gep_wr(lp->cache.gep, dev);\
974 if ((lp->phy[lp->active].id) && (!lp->useSROM || lp->useMII)) {\
975 mii_wr(MII_CR_100|MII_CR_ASSE, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);\
978 } else if (lp->useSROM && !lp->useMII) {\
984 lp->cache.gep = (GEP_FDXD | GEP_MODE);\
985 gep_wr(lp->cache.gep, dev);\
1017 #define MOTO_SROM_BUG (lp->active == 8 && (get_unaligned_le32(dev->dev_addr) & 0x00ffffff) == 0x…