153 #define dw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
628 	dw32(DCR0, DM910X_RESET);	/* RESET MAC */  in dmfe_init_dm910x()
630 	dw32(DCR0, db->cr0_data);  in dmfe_init_dm910x()
641 	dw32(DCR12, 0x180);		/* Let bit 7 output port */  in dmfe_init_dm910x()
643 		dw32(DCR12, 0x80);	/* Issue RESET signal */  in dmfe_init_dm910x()
646 	dw32(DCR12, 0x0);	/* Clear RESET signal */  in dmfe_init_dm910x()
670 	dw32(DCR7, db->cr7_data);  in dmfe_init_dm910x()
673 	dw32(DCR15, db->cr15_data);  in dmfe_init_dm910x()
716 	dw32(DCR7, 0);  in dmfe_start_xmit()
730 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
734 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_start_xmit()
743 	dw32(DCR7, db->cr7_data);  in dmfe_start_xmit()
771 	dw32(DCR0, DM910X_RESET);  in dmfe_stop()
812 	dw32(DCR5, db->cr5_data);  in dmfe_interrupt()
819 	dw32(DCR7, 0);  in dmfe_interrupt()
851 	dw32(DCR7, db->cr7_data);  in dmfe_interrupt()
936 		dw32(DCR1, 0x1);			/* Issue Tx polling */  in dmfe_free_tx_pkt()
1184 		dw32(DCR1, 0x1);   /* Tx polling again */  in dmfe_timer()
1305 	dw32(DCR7, 0);				/* Disable Interrupt */  in dmfe_dynamic_reset()
1306 	dw32(DCR5, dr32(DCR5));  in dmfe_dynamic_reset()
1388 	dw32(DCR4, db->first_tx_desc_dma);     /* TX DESC address */  in dmfe_descriptor_init()
1398 	dw32(DCR3, db->first_rx_desc_dma);		/* RX DESC address */  in dmfe_descriptor_init()
1445 	dw32(DCR6, cr6_tmp);  in update_cr6()
1447 	dw32(DCR6, cr6_data);  in update_cr6()
1546 		dw32(DCR1, 0x1);	/* Issue Tx polling */  in send_filter_frame()
1592 		dw32(DCR9, data | cmd[i]);  in srom_clk_write()
1605 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1607 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1621 	dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1625 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);  in read_srom_word()
1629 		dw32(DCR9, CR9_SROM_READ | CR9_SRCS);  in read_srom_word()
1633 	dw32(DCR9, CR9_SROM_READ);  in read_srom_word()
1891 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1893 	dw32(DCR9, phy_data | MDCLKH);	/* MII Clock High */  in dmfe_phy_write_1bit()
1895 	dw32(DCR9, phy_data);		/* MII Clock Low */  in dmfe_phy_write_1bit()
1908 	dw32(DCR9, 0x50000);  in dmfe_phy_read_1bit()
1911 	dw32(DCR9, 0x40000);  in dmfe_phy_read_1bit()
2125 	dw32(DCR7, 0);  in dmfe_suspend()
2126 	dw32(DCR5, dr32(DCR5));  in dmfe_suspend()