97 			iowrite32(0x01, tp->base_addr + CSR2);  in tulip_refill_rx()
140                iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5);  in tulip_poll()
301                                  iowrite32(mit_table[MIT_TABLE], tp->base_addr + CSR11);  in tulip_poll()
307                                  iowrite32(0, tp->base_addr + CSR11);  in tulip_poll()
323          iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7);  in tulip_poll()
497 		iowrite32(csr12 | 0x02, tp->base_addr + CSR12);  in phy_interrupt()
504 		iowrite32(csr12 & ~0x02, tp->base_addr + CSR12);  in phy_interrupt()
554 			iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7);  in tulip_interrupt()
564 		iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5);  in tulip_interrupt()
568 		iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5);  in tulip_interrupt()
680 				iowrite32(0, ioaddr + CSR1);  in tulip_interrupt()
684 					iowrite32(tp->mc_filter[0], ioaddr + 0xAC);  in tulip_interrupt()
685 					iowrite32(tp->mc_filter[1], ioaddr + 0xB0);  in tulip_interrupt()
718 			iowrite32(0x0800f7ba, ioaddr + CSR5);  in tulip_interrupt()
727 			iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);  in tulip_interrupt()
737                         iowrite32(0x8001ffff, ioaddr + CSR5);  in tulip_interrupt()
741                                 iowrite32(0x8b240000, ioaddr + CSR11);  in tulip_interrupt()
744 				iowrite32(0x00, ioaddr + CSR7);  in tulip_interrupt()
749 …                        iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7);  in tulip_interrupt()
750                                 iowrite32(0x0012, ioaddr + CSR11);  in tulip_interrupt()
787 			iowrite32(0x00, ioaddr + CSR7);
795 				iowrite32(tulip_tbl[tp->chip_id].valid_intrs | TimerInt,
797 				iowrite32(TimerInt, ioaddr + CSR5);
798 				iowrite32(12, ioaddr + CSR11);