43 #define xw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
364 	xw32(CSR5, status);  in xircom_interrupt()
509 	xw32(CSR0, val);  in initialize_card()
515 	xw32(CSR0, val);  in initialize_card()
520 	xw32(CSR0, val);  in initialize_card()
540 	xw32(CSR1, 0);  in trigger_transmit()
554 	xw32(CSR2, 0);  in trigger_receive()
593 	xw32(CSR3, address);	/* Receive descr list address */  in setup_descriptors()
618 	xw32(CSR4, address);	/* xmit descr list address */  in setup_descriptors()
631 	xw32(CSR3, val);	/* Receive descriptor address */  in remove_descriptors()
632 	xw32(CSR4, val);	/* Send descriptor address */  in remove_descriptors()
653 	xw32(CSR5, val);  in link_status_changed()
712 	xw32(CSR6, val);  in activate_receiver()
728 	xw32(CSR6, val);  in activate_receiver()
759 	xw32(CSR6, val);  in deactivate_receiver()
798 	xw32(CSR6, val);  in activate_transmitter()
815 	xw32(CSR6, val);  in activate_transmitter()
846 	xw32(CSR6, val);  in deactivate_transmitter()
874 	xw32(CSR7, val);  in enable_transmit_interrupt()
890 	xw32(CSR7, val);  in enable_receive_interrupt()
905 	xw32(CSR7, val);  in enable_link_interrupt()
919 	xw32(CSR7, 0);  in disable_all_interrupts()
941 	xw32(CSR7, val);  in enable_common_interrupts()
956 	xw32(CSR6, val);  in enable_promisc()
1006 	xw32(CSR9, 1 << 12);	/* enable boot rom access */  in read_mac_address()
1010 		xw32(CSR10, i);  in read_mac_address()
1012 		xw32(CSR10, i + 1);  in read_mac_address()
1014 		xw32(CSR10, i + 2);  in read_mac_address()
1016 		xw32(CSR10, i + 3);  in read_mac_address()
1022 				xw32(CSR10, i + j + 4);  in read_mac_address()
1052 	xw32(CSR15, 0x0008);  in transceiver_voodoo()
1054 	xw32(CSR15, 0xa8050000);  in transceiver_voodoo()
1056 	xw32(CSR15, 0xa00f0000);  in transceiver_voodoo()