Lines Matching refs:priv
236 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_config_port() local
239 priv->speed = speed; in hix5hd2_config_port()
240 priv->duplex = duplex; in hix5hd2_config_port()
242 switch (priv->phy_mode) { in hix5hd2_config_port()
265 writel_relaxed(val, priv->ctrl_base); in hix5hd2_config_port()
267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
274 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port()
275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port()
276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port()
279 static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx) in hix5hd2_set_desc_depth() argument
281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth()
283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth()
285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
286 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth()
287 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth()
289 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
290 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); in hix5hd2_set_desc_depth()
291 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_desc_depth()
293 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
294 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); in hix5hd2_set_desc_depth()
295 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_desc_depth()
298 static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) in hix5hd2_set_rx_fq() argument
300 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
301 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); in hix5hd2_set_rx_fq()
302 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_rx_fq()
305 static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) in hix5hd2_set_rx_bq() argument
307 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
308 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); in hix5hd2_set_rx_bq()
309 writel_relaxed(0, priv->base + RX_BQ_REG_EN); in hix5hd2_set_rx_bq()
312 static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) in hix5hd2_set_tx_bq() argument
314 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
315 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); in hix5hd2_set_tx_bq()
316 writel_relaxed(0, priv->base + TX_BQ_REG_EN); in hix5hd2_set_tx_bq()
319 static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) in hix5hd2_set_tx_rq() argument
321 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
322 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); in hix5hd2_set_tx_rq()
323 writel_relaxed(0, priv->base + TX_RQ_REG_EN); in hix5hd2_set_tx_rq()
326 static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv) in hix5hd2_set_desc_addr() argument
328 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr); in hix5hd2_set_desc_addr()
329 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr); in hix5hd2_set_desc_addr()
330 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr); in hix5hd2_set_desc_addr()
331 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr); in hix5hd2_set_desc_addr()
334 static void hix5hd2_hw_init(struct hix5hd2_priv *priv) in hix5hd2_hw_init() argument
339 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_hw_init()
340 writel_relaxed(~0, priv->base + RAW_PMU_INT); in hix5hd2_hw_init()
342 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); in hix5hd2_hw_init()
343 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); in hix5hd2_hw_init()
344 writel_relaxed(0, priv->base + COL_SLOT_TIME); in hix5hd2_hw_init()
347 writel_relaxed(val, priv->base + IN_QUEUE_TH); in hix5hd2_hw_init()
349 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
350 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); in hix5hd2_hw_init()
352 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); in hix5hd2_hw_init()
353 hix5hd2_set_desc_addr(priv); in hix5hd2_hw_init()
356 static void hix5hd2_irq_enable(struct hix5hd2_priv *priv) in hix5hd2_irq_enable() argument
358 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); in hix5hd2_irq_enable()
361 static void hix5hd2_irq_disable(struct hix5hd2_priv *priv) in hix5hd2_irq_disable() argument
363 writel_relaxed(0, priv->base + ENA_PMU_INT); in hix5hd2_irq_disable()
366 static void hix5hd2_port_enable(struct hix5hd2_priv *priv) in hix5hd2_port_enable() argument
368 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_enable()
369 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); in hix5hd2_port_enable()
372 static void hix5hd2_port_disable(struct hix5hd2_priv *priv) in hix5hd2_port_disable() argument
374 writel_relaxed(~(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); in hix5hd2_port_disable()
375 writel_relaxed(0, priv->base + DESC_WR_RD_ENA); in hix5hd2_port_disable()
380 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_hw_set_mac_addr() local
385 writel_relaxed(val, priv->base + STATION_ADDR_HIGH); in hix5hd2_hw_set_mac_addr()
388 writel_relaxed(val, priv->base + STATION_ADDR_LOW); in hix5hd2_hw_set_mac_addr()
404 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_adjust_link() local
405 struct phy_device *phy = priv->phy; in hix5hd2_adjust_link()
407 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) { in hix5hd2_adjust_link()
413 static void hix5hd2_rx_refill(struct hix5hd2_priv *priv) in hix5hd2_rx_refill() argument
422 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); in hix5hd2_rx_refill()
424 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); in hix5hd2_rx_refill()
428 if (priv->rx_skb[pos]) { in hix5hd2_rx_refill()
431 skb = netdev_alloc_skb_ip_align(priv->netdev, len); in hix5hd2_rx_refill()
436 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE); in hix5hd2_rx_refill()
437 if (dma_mapping_error(priv->dev, addr)) { in hix5hd2_rx_refill()
442 desc = priv->rx_fq.desc + pos; in hix5hd2_rx_refill()
444 priv->rx_skb[pos] = skb; in hix5hd2_rx_refill()
454 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); in hix5hd2_rx_refill()
459 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_rx() local
466 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); in hix5hd2_rx()
468 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); in hix5hd2_rx()
476 skb = priv->rx_skb[pos]; in hix5hd2_rx()
481 priv->rx_skb[pos] = NULL; in hix5hd2_rx()
483 desc = priv->rx_bq.desc + pos; in hix5hd2_rx()
487 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE, in hix5hd2_rx()
500 napi_gro_receive(&priv->napi, skb); in hix5hd2_rx()
509 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); in hix5hd2_rx()
511 hix5hd2_rx_refill(priv); in hix5hd2_rx()
520 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_xmit_reclaim() local
528 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); in hix5hd2_xmit_reclaim()
530 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); in hix5hd2_xmit_reclaim()
534 skb = priv->tx_skb[pos]; in hix5hd2_xmit_reclaim()
542 desc = priv->tx_rq.desc + pos; in hix5hd2_xmit_reclaim()
544 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); in hix5hd2_xmit_reclaim()
545 priv->tx_skb[pos] = NULL; in hix5hd2_xmit_reclaim()
551 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); in hix5hd2_xmit_reclaim()
558 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) in hix5hd2_xmit_reclaim()
559 netif_wake_queue(priv->netdev); in hix5hd2_xmit_reclaim()
564 struct hix5hd2_priv *priv = container_of(napi, in hix5hd2_poll() local
566 struct net_device *dev = priv->netdev; in hix5hd2_poll()
578 ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_poll()
579 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_poll()
584 hix5hd2_irq_enable(priv); in hix5hd2_poll()
593 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_interrupt() local
594 int ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
596 writel_relaxed(ints, priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
598 hix5hd2_irq_disable(priv); in hix5hd2_interrupt()
599 napi_schedule(&priv->napi); in hix5hd2_interrupt()
607 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_net_xmit() local
613 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); in hix5hd2_net_xmit()
614 if (unlikely(priv->tx_skb[pos])) { in hix5hd2_net_xmit()
621 addr = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE); in hix5hd2_net_xmit()
622 if (dma_mapping_error(priv->dev, addr)) { in hix5hd2_net_xmit()
627 desc = priv->tx_bq.desc + pos; in hix5hd2_net_xmit()
629 priv->tx_skb[pos] = skb; in hix5hd2_net_xmit()
638 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); in hix5hd2_net_xmit()
648 static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv) in hix5hd2_free_dma_desc_rings() argument
655 struct sk_buff *skb = priv->rx_skb[i]; in hix5hd2_free_dma_desc_rings()
659 desc = priv->rx_fq.desc + i; in hix5hd2_free_dma_desc_rings()
661 dma_unmap_single(priv->dev, addr, in hix5hd2_free_dma_desc_rings()
664 priv->rx_skb[i] = NULL; in hix5hd2_free_dma_desc_rings()
668 struct sk_buff *skb = priv->tx_skb[i]; in hix5hd2_free_dma_desc_rings()
672 desc = priv->tx_rq.desc + i; in hix5hd2_free_dma_desc_rings()
674 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); in hix5hd2_free_dma_desc_rings()
676 priv->tx_skb[i] = NULL; in hix5hd2_free_dma_desc_rings()
682 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_net_open() local
685 ret = clk_prepare_enable(priv->clk); in hix5hd2_net_open()
691 priv->phy = of_phy_connect(dev, priv->phy_node, in hix5hd2_net_open()
692 &hix5hd2_adjust_link, 0, priv->phy_mode); in hix5hd2_net_open()
693 if (!priv->phy) in hix5hd2_net_open()
696 phy_start(priv->phy); in hix5hd2_net_open()
697 hix5hd2_hw_init(priv); in hix5hd2_net_open()
698 hix5hd2_rx_refill(priv); in hix5hd2_net_open()
702 napi_enable(&priv->napi); in hix5hd2_net_open()
704 hix5hd2_port_enable(priv); in hix5hd2_net_open()
705 hix5hd2_irq_enable(priv); in hix5hd2_net_open()
712 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_net_close() local
714 hix5hd2_port_disable(priv); in hix5hd2_net_close()
715 hix5hd2_irq_disable(priv); in hix5hd2_net_close()
716 napi_disable(&priv->napi); in hix5hd2_net_close()
718 hix5hd2_free_dma_desc_rings(priv); in hix5hd2_net_close()
720 if (priv->phy) { in hix5hd2_net_close()
721 phy_stop(priv->phy); in hix5hd2_net_close()
722 phy_disconnect(priv->phy); in hix5hd2_net_close()
725 clk_disable_unprepare(priv->clk); in hix5hd2_net_close()
732 struct hix5hd2_priv *priv; in hix5hd2_tx_timeout_task() local
734 priv = container_of(work, struct hix5hd2_priv, tx_timeout_task); in hix5hd2_tx_timeout_task()
735 hix5hd2_net_close(priv->netdev); in hix5hd2_tx_timeout_task()
736 hix5hd2_net_open(priv->netdev); in hix5hd2_tx_timeout_task()
741 struct hix5hd2_priv *priv = netdev_priv(dev); in hix5hd2_net_timeout() local
743 schedule_work(&priv->tx_timeout_task); in hix5hd2_net_timeout()
757 struct hix5hd2_priv *priv = netdev_priv(net_dev); in hix5hd2_get_settings() local
759 if (!priv->phy) in hix5hd2_get_settings()
762 return phy_ethtool_gset(priv->phy, cmd); in hix5hd2_get_settings()
768 struct hix5hd2_priv *priv = netdev_priv(net_dev); in hix5hd2_set_settings() local
770 if (!priv->phy) in hix5hd2_set_settings()
773 return phy_ethtool_sset(priv->phy, cmd); in hix5hd2_set_settings()
784 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_wait_ready() local
785 void __iomem *base = priv->base; in hix5hd2_mdio_wait_ready()
799 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_read() local
800 void __iomem *base = priv->base; in hix5hd2_mdio_read()
819 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); in hix5hd2_mdio_read()
827 struct hix5hd2_priv *priv = bus->priv; in hix5hd2_mdio_write() local
828 void __iomem *base = priv->base; in hix5hd2_mdio_write()
842 static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv) in hix5hd2_destroy_hw_desc_queue() argument
847 if (priv->pool[i].desc) { in hix5hd2_destroy_hw_desc_queue()
848 dma_free_coherent(priv->dev, priv->pool[i].size, in hix5hd2_destroy_hw_desc_queue()
849 priv->pool[i].desc, in hix5hd2_destroy_hw_desc_queue()
850 priv->pool[i].phys_addr); in hix5hd2_destroy_hw_desc_queue()
851 priv->pool[i].desc = NULL; in hix5hd2_destroy_hw_desc_queue()
856 static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv) in hix5hd2_init_hw_desc_queue() argument
858 struct device *dev = priv->dev; in hix5hd2_init_hw_desc_queue()
863 priv->rx_fq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
864 priv->rx_bq.count = RX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
865 priv->tx_bq.count = TX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
866 priv->tx_rq.count = TX_DESC_NUM; in hix5hd2_init_hw_desc_queue()
869 size = priv->pool[i].count * sizeof(struct hix5hd2_desc); in hix5hd2_init_hw_desc_queue()
876 priv->pool[i].size = size; in hix5hd2_init_hw_desc_queue()
877 priv->pool[i].desc = virt_addr; in hix5hd2_init_hw_desc_queue()
878 priv->pool[i].phys_addr = phys_addr; in hix5hd2_init_hw_desc_queue()
883 hix5hd2_destroy_hw_desc_queue(priv); in hix5hd2_init_hw_desc_queue()
893 struct hix5hd2_priv *priv; in hix5hd2_dev_probe() local
905 priv = netdev_priv(ndev); in hix5hd2_dev_probe()
906 priv->dev = dev; in hix5hd2_dev_probe()
907 priv->netdev = ndev; in hix5hd2_dev_probe()
910 priv->base = devm_ioremap_resource(dev, res); in hix5hd2_dev_probe()
911 if (IS_ERR(priv->base)) { in hix5hd2_dev_probe()
912 ret = PTR_ERR(priv->base); in hix5hd2_dev_probe()
917 priv->ctrl_base = devm_ioremap_resource(dev, res); in hix5hd2_dev_probe()
918 if (IS_ERR(priv->ctrl_base)) { in hix5hd2_dev_probe()
919 ret = PTR_ERR(priv->ctrl_base); in hix5hd2_dev_probe()
923 priv->clk = devm_clk_get(&pdev->dev, NULL); in hix5hd2_dev_probe()
924 if (IS_ERR(priv->clk)) { in hix5hd2_dev_probe()
930 ret = clk_prepare_enable(priv->clk); in hix5hd2_dev_probe()
942 bus->priv = priv; in hix5hd2_dev_probe()
948 priv->bus = bus; in hix5hd2_dev_probe()
954 priv->phy_mode = of_get_phy_mode(node); in hix5hd2_dev_probe()
955 if (priv->phy_mode < 0) { in hix5hd2_dev_probe()
961 priv->phy_node = of_parse_phandle(node, "phy-handle", 0); in hix5hd2_dev_probe()
962 if (!priv->phy_node) { in hix5hd2_dev_probe()
991 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task); in hix5hd2_dev_probe()
998 ret = hix5hd2_init_hw_desc_queue(priv); in hix5hd2_dev_probe()
1002 netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT); in hix5hd2_dev_probe()
1003 ret = register_netdev(priv->netdev); in hix5hd2_dev_probe()
1009 clk_disable_unprepare(priv->clk); in hix5hd2_dev_probe()
1014 netif_napi_del(&priv->napi); in hix5hd2_dev_probe()
1015 hix5hd2_destroy_hw_desc_queue(priv); in hix5hd2_dev_probe()
1017 of_node_put(priv->phy_node); in hix5hd2_dev_probe()
1031 struct hix5hd2_priv *priv = netdev_priv(ndev); in hix5hd2_dev_remove() local
1033 netif_napi_del(&priv->napi); in hix5hd2_dev_remove()
1035 mdiobus_unregister(priv->bus); in hix5hd2_dev_remove()
1036 mdiobus_free(priv->bus); in hix5hd2_dev_remove()
1038 hix5hd2_destroy_hw_desc_queue(priv); in hix5hd2_dev_remove()
1039 of_node_put(priv->phy_node); in hix5hd2_dev_remove()
1040 cancel_work_sync(&priv->tx_timeout_task); in hix5hd2_dev_remove()