753 	ew32(STATUS, toggle);  in e1000_reg_test()
762 	ew32(STATUS, before);  in e1000_reg_test()
872 	ew32(IMC, 0xFFFFFFFF);  in e1000_intr_test()
889 			ew32(IMC, mask);  in e1000_intr_test()
890 			ew32(ICS, mask);  in e1000_intr_test()
907 		ew32(IMS, mask);  in e1000_intr_test()
908 		ew32(ICS, mask);  in e1000_intr_test()
925 			ew32(IMC, ~mask & 0x00007FFF);  in e1000_intr_test()
926 			ew32(ICS, ~mask & 0x00007FFF);  in e1000_intr_test()
938 	ew32(IMC, 0xFFFFFFFF);  in e1000_intr_test()
1026 	ew32(TDBAL, ((u64)txdr->dma & 0x00000000FFFFFFFF));  in e1000_setup_desc_rings()
1027 	ew32(TDBAH, ((u64)txdr->dma >> 32));  in e1000_setup_desc_rings()
1028 	ew32(TDLEN, txdr->count * sizeof(struct e1000_tx_desc));  in e1000_setup_desc_rings()
1029 	ew32(TDH, 0);  in e1000_setup_desc_rings()
1030 	ew32(TDT, 0);  in e1000_setup_desc_rings()
1031 	ew32(TCTL, E1000_TCTL_PSP | E1000_TCTL_EN |  in e1000_setup_desc_rings()
1085 	ew32(RCTL, rctl & ~E1000_RCTL_EN);  in e1000_setup_desc_rings()
1086 	ew32(RDBAL, ((u64)rxdr->dma & 0xFFFFFFFF));  in e1000_setup_desc_rings()
1087 	ew32(RDBAH, ((u64)rxdr->dma >> 32));  in e1000_setup_desc_rings()
1088 	ew32(RDLEN, rxdr->size);  in e1000_setup_desc_rings()
1089 	ew32(RDH, 0);  in e1000_setup_desc_rings()
1090 	ew32(RDT, 0);  in e1000_setup_desc_rings()
1094 	ew32(RCTL, rctl);  in e1000_setup_desc_rings()
1174 	ew32(CTRL, ctrl_reg);  in e1000_nonintegrated_phy_loopback()
1269 	ew32(CTRL, ctrl_reg);  in e1000_integrated_phy_loopback()
1342 			ew32(RCTL, rctl);  in e1000_setup_loopback_test()
1360 	ew32(RCTL, rctl);  in e1000_loopback_cleanup()
1411 	ew32(RDT, rxdr->count - 1);  in e1000_run_loopback_test()
1435 		ew32(TDT, k);  in e1000_run_loopback_test()
1809 		ew32(ITR, 1000000000 / (adapter->itr * 256));  in e1000_set_coalesce()
1811 		ew32(ITR, 0);  in e1000_set_coalesce()