2522 	wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);  in i40e_configure_tx_ring()
2814 		wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),  in i40e_vsi_configure_msix()
2818 		wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),  in i40e_vsi_configure_msix()
2822 		wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);  in i40e_vsi_configure_msix()
2831 			wr32(hw, I40E_QINT_RQCTL(qp), val);  in i40e_vsi_configure_msix()
2845 			wr32(hw, I40E_QINT_TQCTL(qp), val);  in i40e_vsi_configure_msix()
2863 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);  /* disable all */  in i40e_enable_misc_int_causes()
2878 	wr32(hw, I40E_PFINT_ICR0_ENA, val);  in i40e_enable_misc_int_causes()
2881 	wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |  in i40e_enable_misc_int_causes()
2885 	wr32(hw, I40E_PFINT_STAT_CTL0, 0);  in i40e_enable_misc_int_causes()
2902 	wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);  in i40e_configure_msi_and_legacy()
2905 	wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);  in i40e_configure_msi_and_legacy()
2910 	wr32(hw, I40E_PFINT_LNKLST0, 0);  in i40e_configure_msi_and_legacy()
2917 	wr32(hw, I40E_QINT_RQCTL(0), val);  in i40e_configure_msi_and_legacy()
2923 	wr32(hw, I40E_QINT_TQCTL(0), val);  in i40e_configure_msi_and_legacy()
2935 	wr32(hw, I40E_PFINT_DYN_CTL0,  in i40e_irq_dynamic_disable_icr0()
2953 	wr32(hw, I40E_PFINT_DYN_CTL0, val);  in i40e_irq_dynamic_enable_icr0()
2971 	wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);  in i40e_irq_dynamic_enable()
2987 	wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);  in i40e_irq_dynamic_disable()
3083 		wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);  in i40e_vsi_disable_irq()
3084 		wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);  in i40e_vsi_disable_irq()
3090 			wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);  in i40e_vsi_disable_irq()
3097 		wr32(hw, I40E_PFINT_ICR0_ENA, 0);  in i40e_vsi_disable_irq()
3098 		wr32(hw, I40E_PFINT_DYN_CTL0, 0);  in i40e_vsi_disable_irq()
3132 	wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);  in i40e_stop_misc_vector()
3171 		wr32(hw, I40E_QINT_RQCTL(0), qval);  in i40e_intr()
3175 		wr32(hw, I40E_QINT_TQCTL(0), qval);  in i40e_intr()
3251 	wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);  in i40e_intr()
3553 			wr32(hw, I40E_QTX_HEAD(pf_q), 0);  in i40e_vsi_control_tx()
3559 		wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);  in i40e_vsi_control_tx()
3640 		wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);  in i40e_vsi_control_rx()
3726 			wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);  in i40e_vsi_free_irq()
3741 				wr32(hw, I40E_QINT_RQCTL(qp), val);  in i40e_vsi_free_irq()
3756 				wr32(hw, I40E_QINT_TQCTL(qp), val);  in i40e_vsi_free_irq()
3768 		wr32(hw, I40E_PFINT_LNKLST0, val);  in i40e_vsi_free_irq()
3779 		wr32(hw, I40E_QINT_RQCTL(qp), val);  in i40e_vsi_free_irq()
3791 		wr32(hw, I40E_QINT_TQCTL(qp), val);  in i40e_vsi_free_irq()
4911 	wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |  in i40e_open()
4913 	wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |  in i40e_open()
4916 	wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);  in i40e_open()
5076 		wr32(&pf->hw, I40E_GLGEN_RTRIG, val);  in i40e_do_reset()
5087 		wr32(&pf->hw, I40E_GLGEN_RTRIG, val);  in i40e_do_reset()
5479 		wr32(&pf->hw, I40E_PFQF_CTL_1,  in i40e_fdir_flush_and_replay()
5685 				wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,  in i40e_check_hang_subtask()
5699 					wr32(&vsi->back->hw,  in i40e_check_hang_subtask()
5857 		wr32(&pf->hw, pf->hw.aq.arq.len, val);  in i40e_clean_adminq_subtask()
5874 		wr32(&pf->hw, pf->hw.aq.asq.len, val);  in i40e_clean_adminq_subtask()
5935 	wr32(hw, I40E_PFINT_ICR0_ENA, val);  in i40e_clean_adminq_subtask()
6226 			wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);  in i40e_fdir_sb_setup()
6547 		wr32(hw, I40E_GL_MDET_TX, 0xffffffff);  in i40e_handle_mdd_event()
6562 		wr32(hw, I40E_GL_MDET_RX, 0xffffffff);  in i40e_handle_mdd_event()
6569 			wr32(hw, I40E_PF_MDET_TX, 0xFFFF);  in i40e_handle_mdd_event()
6575 			wr32(hw, I40E_PF_MDET_RX, 0xFFFF);  in i40e_handle_mdd_event()
6591 			wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);  in i40e_handle_mdd_event()
6599 			wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);  in i40e_handle_mdd_event()
6618 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);  in i40e_handle_mdd_event()
7393 	wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);  in i40e_setup_misc_vector()
7394 	wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);  in i40e_setup_misc_vector()
7419 		wr32(hw, I40E_PFQF_HKEY(i), rss_key[i]);  in i40e_config_rss()
7425 	wr32(hw, I40E_PFQF_HENA(0), (u32)hena);  in i40e_config_rss()
7426 	wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));  in i40e_config_rss()
7436 	wr32(hw, I40E_PFQF_CTL_0, reg_val);  in i40e_config_rss()
7455 			wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);  in i40e_config_rss()
9710 		wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);  in i40e_probe()
9946 		wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);  in i40e_probe()
10240 	wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));  in i40e_shutdown()
10241 	wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));  in i40e_shutdown()
10271 	wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));  in i40e_suspend()
10272 	wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));  in i40e_suspend()