1775 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,  in ixgbe_set_rar_generic()  argument
1788 	hw->mac.ops.set_vmdq(hw, index, vmdq);  in ixgbe_set_rar_generic()
2860 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_clear_vmdq_generic()  argument
2880 	if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {  in ixgbe_clear_vmdq_generic()
2889 	} else if (vmdq < 32) {  in ixgbe_clear_vmdq_generic()
2890 		mpsar_lo &= ~(1 << vmdq);  in ixgbe_clear_vmdq_generic()
2893 		mpsar_hi &= ~(1 << (vmdq - 32));  in ixgbe_clear_vmdq_generic()
2909 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_set_vmdq_generic()  argument
2920 	if (vmdq < 32) {  in ixgbe_set_vmdq_generic()
2922 		mpsar |= 1 << vmdq;  in ixgbe_set_vmdq_generic()
2926 		mpsar |= 1 << (vmdq - 32);  in ixgbe_set_vmdq_generic()
2942 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)  in ixgbe_set_vmdq_san_mac_generic()  argument
2946 	if (vmdq < 32) {  in ixgbe_set_vmdq_san_mac_generic()
2947 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);  in ixgbe_set_vmdq_san_mac_generic()
2951 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));  in ixgbe_set_vmdq_san_mac_generic()