77 #define ADAPTER_UDPI(val)                  vBIT(val,36,4)  argument
96 #define	GET_PCI_MODE(val)		((val & vBIT(0xF, 0, 4)) >> 60)  argument
224 #define SCHED_INT_CTRL_INT2MSI(val)		vBIT(val,10,6)  argument
228 #define TXREQTO_VAL(val)						vBIT(val,0,32)  argument
266 #define	SET_UPDT_CLICKS(val)		   vBIT(val, 32, 32)  argument
272 #define MDIO_MMD_INDX_ADDR(val)		vBIT(val, 0, 16)  argument
273 #define MDIO_MMD_DEV_ADDR(val)		vBIT(val, 19, 5)  argument
274 #define MDIO_MMS_PRT_ADDR(val)		vBIT(val, 27, 5)  argument
275 #define MDIO_CTRL_START_TRANS(val)	vBIT(val, 56, 4)  argument
276 #define MDIO_OP(val)			vBIT(val, 60, 2)  argument
281 #define MDIO_MDIO_DATA(val)		vBIT(val, 32, 16)  argument
292 #define	I2C_CONTROL_CNTL_END(val)	(val & vBIT(0x1,28,4))  argument
293 #define	I2C_CONTROL_GET_DATA(val)	(u32)(val & 0xFFFFFFFF)  argument
294 #define	I2C_CONTROL_SET_DATA(val)	vBIT(val,32,32)  argument
301 #define MISC_LINK_STABILITY_PRD(val)   vBIT(val,29,3)  argument
309 #define	WREQ_SPLIT_MASK_SET_MASK(val)	vBIT(val, 52, 12)  argument
397 #define TX_FIFO_PARTITION_0_PRI(val)       vBIT(val,5,3)  argument
398 #define TX_FIFO_PARTITION_0_LEN(val)       vBIT(val,19,13)  argument
399 #define TX_FIFO_PARTITION_1_PRI(val)       vBIT(val,37,3)  argument
400 #define TX_FIFO_PARTITION_1_LEN(val)       vBIT(val,51,13  )  argument
403 #define TX_FIFO_PARTITION_2_PRI(val)       vBIT(val,5,3)  argument
404 #define TX_FIFO_PARTITION_2_LEN(val)       vBIT(val,19,13)  argument
405 #define TX_FIFO_PARTITION_3_PRI(val)       vBIT(val,37,3)  argument
406 #define TX_FIFO_PARTITION_3_LEN(val)       vBIT(val,51,13)  argument
409 #define TX_FIFO_PARTITION_4_PRI(val)       vBIT(val,5,3)  argument
410 #define TX_FIFO_PARTITION_4_LEN(val)       vBIT(val,19,13)  argument
411 #define TX_FIFO_PARTITION_5_PRI(val)       vBIT(val,37,3)  argument
412 #define TX_FIFO_PARTITION_5_LEN(val)       vBIT(val,51,13)  argument
415 #define TX_FIFO_PARTITION_6_PRI(val)       vBIT(val,5,3)  argument
416 #define TX_FIFO_PARTITION_6_LEN(val)       vBIT(val,19,13)  argument
417 #define TX_FIFO_PARTITION_7_PRI(val)       vBIT(val,37,3)  argument
418 #define TX_FIFO_PARTITION_7_LEN(val)       vBIT(val,51,13)  argument
535 #define RX_QUEUE_0_PRIORITY(val)       vBIT(val,5,3)  argument
536 #define RX_QUEUE_1_PRIORITY(val)       vBIT(val,13,3)  argument
537 #define RX_QUEUE_2_PRIORITY(val)       vBIT(val,21,3)  argument
538 #define RX_QUEUE_3_PRIORITY(val)       vBIT(val,29,3)  argument
539 #define RX_QUEUE_4_PRIORITY(val)       vBIT(val,37,3)  argument
540 #define RX_QUEUE_5_PRIORITY(val)       vBIT(val,45,3)  argument
541 #define RX_QUEUE_6_PRIORITY(val)       vBIT(val,53,3)  argument
542 #define RX_QUEUE_7_PRIORITY(val)       vBIT(val,61,3)  argument
578 #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val)     vBIT(val,40,24)  argument
698 #define MAC_RMAC_INVLD_IPG_THR(val)     vBIT(val,16,8)  argument
701 #define TMAC_AVG_IPG(val)           vBIT(val,0,8)  argument
704 #define RMAC_MAX_PYLD_LEN(val)      vBIT(val,2,14)  argument
719 #define RMAC_CFG_KEY(val)               vBIT(val,0,16)  argument
763 #define RMAC_PAUSE_HG_PTIME(val)    vBIT(val,16,16)  argument
791 #define RTS_DIX_MAP_ETYPE(val)             vBIT(val,0,16)  argument
792 #define RTS_DIX_MAP_SCW(val)               s2BIT(val,21)  argument
808 #define RTS_PN_CAM_DATA_PORT(val)          vBIT(val,8,16)  argument
809 #define RTS_PN_CAM_DATA_SCW(val)           vBIT(val,24,8)  argument
897 #define	MC_RLDRAM_SET_REF_PERIOD(val)	vBIT(val, 0, 16)  argument