Lines Matching refs:mix_ctl
516 union cvmx_mixx_ctl mix_ctl; in octeon_mgmt_reset_hw() local
520 mix_ctl.u64 = 0; in octeon_mgmt_reset_hw()
521 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
523 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_reset_hw()
524 } while (mix_ctl.s.busy); in octeon_mgmt_reset_hw()
525 mix_ctl.s.reset = 1; in octeon_mgmt_reset_hw()
526 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_reset_hw()
972 union cvmx_mixx_ctl mix_ctl; in octeon_mgmt_open() local
1011 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_open()
1014 if (mix_ctl.s.reset) { in octeon_mgmt_open()
1015 mix_ctl.s.reset = 0; in octeon_mgmt_open()
1016 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_open()
1018 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); in octeon_mgmt_open()
1019 } while (mix_ctl.s.reset); in octeon_mgmt_open()
1065 mix_ctl.u64 = 0; in octeon_mgmt_open()
1066 mix_ctl.s.crc_strip = 1; /* Strip the ending CRC */ in octeon_mgmt_open()
1067 mix_ctl.s.en = 1; /* Enable the port */ in octeon_mgmt_open()
1068 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ in octeon_mgmt_open()
1070 mix_ctl.s.mrq_hwm = 1; in octeon_mgmt_open()
1072 mix_ctl.s.lendian = 1; in octeon_mgmt_open()
1074 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); in octeon_mgmt_open()