Lines Matching refs:u32
42 u32 high;
43 u32 low;
49 u32 INT_ST;
50 u32 INT_EN;
51 u32 MODE;
52 u32 RESET;
53 u32 TCPIP_ACC;
54 u32 EX_LIST;
55 u32 INT_ST_HOLD;
56 u32 PHY_INT_CTRL;
57 u32 MAC_RX_EN;
58 u32 RX_FCTRL;
59 u32 PAUSE_REQ;
60 u32 RX_MODE;
61 u32 TX_MODE;
62 u32 RX_FIFO_ST;
63 u32 TX_FIFO_ST;
64 u32 TX_FID;
65 u32 TX_RESULT;
66 u32 PAUSE_PKT1;
67 u32 PAUSE_PKT2;
68 u32 PAUSE_PKT3;
69 u32 PAUSE_PKT4;
70 u32 PAUSE_PKT5;
71 u32 reserve[2];
73 u32 ADDR_MASK;
74 u32 MIIM;
75 u32 MAC_ADDR_LOAD;
76 u32 RGMII_ST;
77 u32 RGMII_CTRL;
78 u32 reserve3[3];
79 u32 DMA_CTRL;
80 u32 reserve4[3];
81 u32 RX_DSC_BASE;
82 u32 RX_DSC_SIZE;
83 u32 RX_DSC_HW_P;
84 u32 RX_DSC_HW_P_HLD;
85 u32 RX_DSC_SW_P;
86 u32 reserve5[3];
87 u32 TX_DSC_BASE;
88 u32 TX_DSC_SIZE;
89 u32 TX_DSC_HW_P;
90 u32 TX_DSC_HW_P_HLD;
91 u32 TX_DSC_SW_P;
92 u32 reserve6[3];
93 u32 RX_DMA_ST;
94 u32 TX_DMA_ST;
95 u32 reserve7[2];
96 u32 WOL_ST;
97 u32 WOL_CTRL;
98 u32 WOL_ADDR_MASK;
319 #define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
320 #define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
346 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
347 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
372 u32 max_frame_size;
373 u32 min_frame_size;
388 u32 addr;
389 u32 id;
390 u32 revision;
391 u32 reset_delay_us;
434 u32 buffer_addr;
435 u32 tcp_ip_status;
455 u32 buffer_addr;
556 u32 rx_packets;
557 u32 tx_packets;
558 u32 rx_bytes;
559 u32 tx_bytes;
560 u32 rx_errors;
561 u32 tx_errors;
562 u32 rx_dropped;
563 u32 tx_dropped;
564 u32 multicast;
565 u32 collisions;
566 u32 rx_crc_errors;
567 u32 rx_frame_errors;
568 u32 rx_alloc_buff_failed;
569 u32 tx_length_errors;
570 u32 tx_aborted_errors;
571 u32 tx_carrier_errors;
572 u32 tx_timeout_count;
573 u32 tx_restart_count;
574 u32 intr_rx_dsc_empty_count;
575 u32 intr_rx_frame_err_count;
576 u32 intr_rx_fifo_err_count;
577 u32 intr_rx_dma_err_count;
578 u32 intr_tx_fifo_err_count;
579 u32 intr_tx_dma_err_count;
580 u32 intr_tcpip_err_count;
635 u32 wake_up_evt;
636 u32 *config_space;
668 u32 pch_ch_control_read(struct pci_dev *pdev);
669 void pch_ch_control_write(struct pci_dev *pdev, u32 val);
670 u32 pch_ch_event_read(struct pci_dev *pdev);
671 void pch_ch_event_write(struct pci_dev *pdev, u32 val);
672 u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
673 u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
687 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,