Lines Matching refs:reg_val
26 u32 reg_val; in sxgbe_dma_init() local
28 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
36 reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; in sxgbe_dma_init()
39 reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); in sxgbe_dma_init()
41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
50 u32 reg_val; in sxgbe_dma_channel_init() local
53 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val |= SXGBE_DMA_PBL_X8MODE; in sxgbe_dma_channel_init()
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
59 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val |= (pbl << SXGBE_DMA_TXPBL_LSHIFT); in sxgbe_dma_channel_init()
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
63 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
64 reg_val |= (pbl << SXGBE_DMA_RXPBL_LSHIFT); in sxgbe_dma_channel_init()
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()