26 	u32 reg_val;  in sxgbe_mtl_init()  local
28 	reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
29 	reg_val &= ETS_RST;  in sxgbe_mtl_init()
34 		reg_val &= ETS_WRR;  in sxgbe_mtl_init()
37 		reg_val |= ETS_WFQ;  in sxgbe_mtl_init()
40 		reg_val |= ETS_DWRR;  in sxgbe_mtl_init()
43 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
47 		reg_val &= RAA_SP;  in sxgbe_mtl_init()
50 		reg_val |= RAA_WSP;  in sxgbe_mtl_init()
53 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
67 	u32 fifo_bits, reg_val;  in sxgbe_mtl_set_txfifosize()  local
71 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_txfifosize()
72 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);  in sxgbe_mtl_set_txfifosize()
73 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_txfifosize()
79 	u32 fifo_bits, reg_val;  in sxgbe_mtl_set_rxfifosize()  local
83 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_rxfifosize()
84 	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);  in sxgbe_mtl_set_rxfifosize()
85 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_rxfifosize()
90 	u32 reg_val;  in sxgbe_mtl_enable_txqueue()  local
92 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_enable_txqueue()
93 	reg_val |= SXGBE_MTL_ENABLE_QUEUE;  in sxgbe_mtl_enable_txqueue()
94 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_enable_txqueue()
99 	u32 reg_val;  in sxgbe_mtl_disable_txqueue()  local
101 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_disable_txqueue()
102 	reg_val &= ~SXGBE_MTL_ENABLE_QUEUE;  in sxgbe_mtl_disable_txqueue()
103 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_disable_txqueue()
109 	u32 reg_val;  in sxgbe_mtl_fc_active()  local
111 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_active()
112 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_ACTIVE);  in sxgbe_mtl_fc_active()
113 	reg_val |= (threshold << RX_FC_ACTIVE);  in sxgbe_mtl_fc_active()
115 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_active()
120 	u32 reg_val;  in sxgbe_mtl_fc_enable()  local
122 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_enable()
123 	reg_val |= SXGBE_MTL_ENABLE_FC;  in sxgbe_mtl_fc_enable()
124 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_enable()
130 	u32 reg_val;  in sxgbe_mtl_fc_deactive()  local
132 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_deactive()
133 	reg_val &= ~(SXGBE_MTL_FCMASK << RX_FC_DEACTIVE);  in sxgbe_mtl_fc_deactive()
134 	reg_val |= (threshold << RX_FC_DEACTIVE);  in sxgbe_mtl_fc_deactive()
136 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_deactive()
141 	u32 reg_val;  in sxgbe_mtl_fep_enable()  local
143 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_enable()
144 	reg_val |= SXGBE_MTL_RXQ_OP_FEP;  in sxgbe_mtl_fep_enable()
146 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_enable()
151 	u32 reg_val;  in sxgbe_mtl_fep_disable()  local
153 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_disable()
154 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FEP);  in sxgbe_mtl_fep_disable()
156 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_disable()
161 	u32 reg_val;  in sxgbe_mtl_fup_enable()  local
163 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_enable()
164 	reg_val |= SXGBE_MTL_RXQ_OP_FUP;  in sxgbe_mtl_fup_enable()
166 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_enable()
171 	u32 reg_val;  in sxgbe_mtl_fup_disable()  local
173 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_disable()
174 	reg_val &= ~(SXGBE_MTL_RXQ_OP_FUP);  in sxgbe_mtl_fup_disable()
176 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_disable()
183 	u32 reg_val;  in sxgbe_set_tx_mtl_mode()  local
185 	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_set_tx_mtl_mode()
188 		reg_val |= SXGBE_MTL_SFMODE;  in sxgbe_set_tx_mtl_mode()
192 			reg_val |= MTL_CONTROL_TTC_64;  in sxgbe_set_tx_mtl_mode()
194 			reg_val |= MTL_CONTROL_TTC_96;  in sxgbe_set_tx_mtl_mode()
196 			reg_val |= MTL_CONTROL_TTC_128;  in sxgbe_set_tx_mtl_mode()
198 			reg_val |= MTL_CONTROL_TTC_192;  in sxgbe_set_tx_mtl_mode()
200 			reg_val |= MTL_CONTROL_TTC_256;  in sxgbe_set_tx_mtl_mode()
202 			reg_val |= MTL_CONTROL_TTC_384;  in sxgbe_set_tx_mtl_mode()
204 			reg_val |= MTL_CONTROL_TTC_512;  in sxgbe_set_tx_mtl_mode()
208 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_set_tx_mtl_mode()
214 	u32 reg_val;  in sxgbe_set_rx_mtl_mode()  local
216 	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_set_rx_mtl_mode()
219 		reg_val |= SXGBE_RX_MTL_SFMODE;  in sxgbe_set_rx_mtl_mode()
222 			reg_val |= MTL_CONTROL_RTC_64;  in sxgbe_set_rx_mtl_mode()
224 			reg_val |= MTL_CONTROL_RTC_96;  in sxgbe_set_rx_mtl_mode()
226 			reg_val |= MTL_CONTROL_RTC_128;  in sxgbe_set_rx_mtl_mode()
230 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_set_rx_mtl_mode()