362         outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),  in register_bank()
758 	outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);  in smsc_ircc_init_chip()
759 	outb(0x00, iobase + IRCC_MASTER);  in smsc_ircc_init_chip()
762 	outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),  in smsc_ircc_init_chip()
766 	outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),  in smsc_ircc_init_chip()
769 	outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),  in smsc_ircc_init_chip()
773 	outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);  in smsc_ircc_init_chip()
776 	outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);  in smsc_ircc_init_chip()
779 	outb(0, iobase + IRCC_LCR_A);  in smsc_ircc_init_chip()
784 	outb(0x00, iobase + IRCC_MASTER);  in smsc_ircc_init_chip()
930 	outb(UART_IER_THRI, self->io.sir_base + UART_IER);  in smsc_ircc_hard_xmit_sir()
981 	outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);  in smsc_ircc_set_fir_speed()
985 …outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + …  in smsc_ircc_set_fir_speed()
988 	outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);  in smsc_ircc_set_fir_speed()
1013 	outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);  in smsc_ircc_fir_start()
1022 	outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),  in smsc_ircc_fir_start()
1025 	outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),  in smsc_ircc_fir_start()
1031 	outb(0, fir_base + IRCC_MASTER);  in smsc_ircc_fir_start()
1033 	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);  in smsc_ircc_fir_start()
1034 	outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);  in smsc_ircc_fir_start()
1054 	outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);  in smsc_ircc_fir_stop()
1148 	outb(0, iobase + UART_IER);  in smsc_ircc_set_sir_speed()
1165 	outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */  in smsc_ircc_set_sir_speed()
1166 	outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */  in smsc_ircc_set_sir_speed()
1167 	outb(divisor >> 8,	  iobase + UART_DLM);  in smsc_ircc_set_sir_speed()
1168 	outb(lcr,		  iobase + UART_LCR); /* Set 8N1 */  in smsc_ircc_set_sir_speed()
1169 	outb(fcr,		  iobase + UART_FCR); /* Enable FIFO's */  in smsc_ircc_set_sir_speed()
1172 	outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);  in smsc_ircc_set_sir_speed()
1262 	outb(0x00, iobase + IRCC_LCR_B);  in smsc_ircc_dma_xmit()
1265 	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,  in smsc_ircc_dma_xmit()
1272 	outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);  in smsc_ircc_dma_xmit()
1274 	outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);  in smsc_ircc_dma_xmit()
1277 	outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);  in smsc_ircc_dma_xmit()
1278 	outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);  in smsc_ircc_dma_xmit()
1284 	outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |  in smsc_ircc_dma_xmit()
1294 	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);  in smsc_ircc_dma_xmit()
1295 	outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);  in smsc_ircc_dma_xmit()
1298 	outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);  in smsc_ircc_dma_xmit()
1316 	outb(0x00, iobase + IRCC_LCR_B);  in smsc_ircc_dma_xmit_complete()
1319 	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,  in smsc_ircc_dma_xmit_complete()
1330 		outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);  in smsc_ircc_dma_xmit_complete()
1331 		outb(0x00, iobase + IRCC_MASTER);  in smsc_ircc_dma_xmit_complete()
1359 	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,  in smsc_ircc_dma_receive()
1365 	outb(0x00, iobase + IRCC_LCR_B);  in smsc_ircc_dma_receive()
1369 	outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,  in smsc_ircc_dma_receive()
1377 	outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);  in smsc_ircc_dma_receive()
1378 	outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);  in smsc_ircc_dma_receive()
1386 	outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |  in smsc_ircc_dma_receive()
1391 	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);  in smsc_ircc_dma_receive()
1392 	outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);  in smsc_ircc_dma_receive()
1396 	outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,  in smsc_ircc_dma_receive()
1420 	outb(0x00, iobase + IRCC_LCR_B);  in smsc_ircc_dma_receive_complete()
1423 	outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);  in smsc_ircc_dma_receive_complete()
1535 	outb(0, iobase + IRCC_IER);  in smsc_ircc_interrupt()
1557 	outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);  in smsc_ircc_interrupt()
1680 	outb(0, iobase + IRCC_IER);  in smsc_ircc_stop_interrupts()
1681 	outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);  in smsc_ircc_stop_interrupts()
1682 	outb(0x00, iobase + IRCC_MASTER);  in smsc_ircc_stop_interrupts()
1912 	outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);  in smsc_ircc_sir_start()
1919 …outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A)…  in smsc_ircc_sir_start()
1922 	outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */  in smsc_ircc_sir_start()
1923 	outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);  in smsc_ircc_sir_start()
1926 	outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);  in smsc_ircc_sir_start()
1930 	outb(0x00, fir_base + IRCC_MASTER);  in smsc_ircc_sir_start()
1942 	outb(0, iobase + UART_MCR);  in smsc_ircc_sir_stop()
1945 	outb(0, iobase + UART_IER);  in smsc_ircc_sir_stop()
2005 			outb(fcr, iobase + UART_FCR);  in smsc_ircc_sir_write_wakeup()
2008 			outb(UART_IER_RDI, iobase + UART_IER);  in smsc_ircc_sir_write_wakeup()
2033 		outb(buf[actual], iobase + UART_TX);  in smsc_ircc_sir_write()
2192 	outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);  in smsc_superio_flat()
2200 	outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);  in smsc_superio_flat()
2204 	outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);  in smsc_superio_flat()
2208 	outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);  in smsc_superio_flat()
2212 	outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);  in smsc_superio_flat()
2222 	outb(SMSCSIO_CFGEXITKEY, cfgbase);  in smsc_superio_flat()
2244 	outb(0x07, cfg_base);  in smsc_superio_paged()
2245 	outb(0x05, cfg_base + 1);  in smsc_superio_paged()
2248 	outb(0x60, cfg_base);  in smsc_superio_paged()
2250 	outb(0x61, cfg_base);  in smsc_superio_paged()
2254 	outb(0x62, cfg_base);  in smsc_superio_paged()
2256 	outb(0x63, cfg_base);  in smsc_superio_paged()
2258 	outb(0x2b, cfg_base); /* ??? */  in smsc_superio_paged()
2264 	outb(SMSCSIO_CFGEXITKEY, cfg_base);  in smsc_superio_paged()
2274 	outb(reg, cfg_base);  in smsc_access()
2286 	outb(SMSCSIO_CFGEXITKEY, cfg_base);  in smsc_ircc_probe()
2291 	outb(reg, cfg_base);  in smsc_ircc_probe()
2297 	outb(SMSCSIO_CFGACCESSKEY, cfg_base);  in smsc_ircc_probe()
2534 	outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state  in preconfigure_smsc_chip()
2535 	outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID  in preconfigure_smsc_chip()
2541 	outb(0x24, iobase);  // select CR24 - UART1 base addr  in preconfigure_smsc_chip()
2542 	outb(0x00, iobase + 1); // disable UART1  in preconfigure_smsc_chip()
2543 	outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr  in preconfigure_smsc_chip()
2544 	outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8  in preconfigure_smsc_chip()
2553 	outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select  in preconfigure_smsc_chip()
2557 	outb(tmpbyte, iobase + 1);  in preconfigure_smsc_chip()
2565 	outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr  in preconfigure_smsc_chip()
2566 	outb((conf->fir_io >> 3), iobase + 1);  in preconfigure_smsc_chip()
2574 	outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select  in preconfigure_smsc_chip()
2575 	outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA  in preconfigure_smsc_chip()
2582 	outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode  in preconfigure_smsc_chip()
2586 	outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed  in preconfigure_smsc_chip()
2588 	outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel  in preconfigure_smsc_chip()
2590 	outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down  in preconfigure_smsc_chip()
2593 	outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux  in preconfigure_smsc_chip()
2595 	outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port  in preconfigure_smsc_chip()
2597 	outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power  in preconfigure_smsc_chip()
2599 	outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down  in preconfigure_smsc_chip()
2601 	outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle  in preconfigure_smsc_chip()
2603 	outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done  in preconfigure_smsc_chip()
2605 	outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration  in preconfigure_smsc_chip()
2924 	outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,  in smsc_ircc_set_transceiver_smsc_ircc_atc()
2970 	outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);  in smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select()
3009 	outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);  in smsc_ircc_set_transceiver_toshiba_sat1800()