Lines Matching refs:I_CF_L_0
124 #define I_CF_L_0 0x10 macro
318 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
325 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
326 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
327 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
328 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
811 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetVFIR()
812 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetVFIR()
821 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetFIR()
822 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetFIR()
823 WriteRegBit(BaseAddr, I_CF_L_0, 6, val); in SetFIR()
831 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetMIR()
832 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetMIR()
833 WriteRegBit(BaseAddr, I_CF_L_0, 5, val); in SetMIR()
841 tmp = ReadReg(BaseAddr, I_CF_L_0); in SetSIR()
842 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f); in SetSIR()
843 WriteRegBit(BaseAddr, I_CF_L_0, 4, val); in SetSIR()