Lines Matching refs:iobase
86 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
89 static int w83977af_probe(int iobase, int irq, int dma);
94 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
95 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
149 static int w83977af_open(int i, unsigned int iobase, unsigned int irq, in w83977af_open() argument
157 if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) { in w83977af_open()
159 __func__ , iobase); in w83977af_open()
163 if (w83977af_probe(iobase, irq, dma) == -1) { in w83977af_open()
183 self->io.fir_base = iobase; in w83977af_open()
252 release_region(iobase, CHIP_IO_EXTENT); in w83977af_open()
264 int iobase; in w83977af_close() local
266 iobase = self->io.fir_base; in w83977af_close()
301 static int w83977af_probe(int iobase, int irq, int dma) in w83977af_probe() argument
314 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]); in w83977af_probe()
315 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]); in w83977af_probe()
335 switch_bank(iobase, SET2); in w83977af_probe()
336 outb(iobase+2, 0x00); in w83977af_probe()
339 switch_bank(iobase, SET0); in w83977af_probe()
340 outb(HCR_EN_IRQ, iobase+HCR); in w83977af_probe()
343 switch_bank(iobase, SET2); in w83977af_probe()
344 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1); in w83977af_probe()
347 switch_bank(iobase, SET0); in w83977af_probe()
348 outb(HCR_SIR, iobase+HCR); in w83977af_probe()
351 switch_bank(iobase, SET3); in w83977af_probe()
352 version = inb(iobase+AUID); in w83977af_probe()
359 switch_bank(iobase, SET2); in w83977af_probe()
360 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_probe()
363 switch_bank(iobase, SET0); in w83977af_probe()
365 UFR_EN_FIFO,iobase+UFR); in w83977af_probe()
368 switch_bank(iobase, SET4); in w83977af_probe()
369 outb(2048 & 0xff, iobase+6); in w83977af_probe()
370 outb((2048 >> 8) & 0x1f, iobase+7); in w83977af_probe()
384 switch_bank(iobase, SET7); in w83977af_probe()
385 outb(0x40, iobase+7); in w83977af_probe()
402 int iobase; in w83977af_change_speed() local
405 iobase = self->io.fir_base; in w83977af_change_speed()
411 set = inb(iobase+SSR); in w83977af_change_speed()
414 switch_bank(iobase, SET0); in w83977af_change_speed()
415 outb(0, iobase+ICR); in w83977af_change_speed()
418 switch_bank(iobase, SET2); in w83977af_change_speed()
419 outb(0x00, iobase+ABHL); in w83977af_change_speed()
422 case 9600: outb(0x0c, iobase+ABLL); break; in w83977af_change_speed()
423 case 19200: outb(0x06, iobase+ABLL); break; in w83977af_change_speed()
424 case 38400: outb(0x03, iobase+ABLL); break; in w83977af_change_speed()
425 case 57600: outb(0x02, iobase+ABLL); break; in w83977af_change_speed()
426 case 115200: outb(0x01, iobase+ABLL); break; in w83977af_change_speed()
446 switch_bank(iobase, SET0); in w83977af_change_speed()
447 outb(ir_mode, iobase+HCR); in w83977af_change_speed()
450 switch_bank(iobase, SET2); in w83977af_change_speed()
451 outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2); in w83977af_change_speed()
454 switch_bank(iobase, SET0); in w83977af_change_speed()
455 outb(0x00, iobase+UFR); /* Reset */ in w83977af_change_speed()
456 outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */ in w83977af_change_speed()
457 outb(0xa7, iobase+UFR); in w83977af_change_speed()
462 switch_bank(iobase, SET0); in w83977af_change_speed()
464 outb(ICR_EFSFI, iobase+ICR); in w83977af_change_speed()
467 outb(ICR_ERBRI, iobase+ICR); in w83977af_change_speed()
470 outb(set, iobase+SSR); in w83977af_change_speed()
484 int iobase; in w83977af_hard_xmit() local
490 iobase = self->io.fir_base; in w83977af_hard_xmit()
511 set = inb(iobase+SSR); in w83977af_hard_xmit()
525 switch_bank(iobase, SET0); in w83977af_hard_xmit()
526 outb(ICR_EDMAI, iobase+ICR); in w83977af_hard_xmit()
527 w83977af_dma_write(self, iobase); in w83977af_hard_xmit()
534 switch_bank(iobase, SET0); in w83977af_hard_xmit()
535 outb(ICR_ETXTHI, iobase+ICR); in w83977af_hard_xmit()
540 outb(set, iobase+SSR); in w83977af_hard_xmit()
551 static void w83977af_dma_write(struct w83977af_ir *self, int iobase) in w83977af_dma_write() argument
557 set = inb(iobase+SSR); in w83977af_dma_write()
560 switch_bank(iobase, SET0); in w83977af_dma_write()
561 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_write()
564 switch_bank(iobase, SET2); in w83977af_dma_write()
565 outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1); in w83977af_dma_write()
571 switch_bank(iobase, SET0); in w83977af_dma_write()
572 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); in w83977af_dma_write()
575 outb(set, iobase+SSR); in w83977af_dma_write()
584 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size) in w83977af_pio_write() argument
590 set = inb(iobase+SSR); in w83977af_pio_write()
592 switch_bank(iobase, SET0); in w83977af_pio_write()
593 if (!(inb_p(iobase+USR) & USR_TSRE)) { in w83977af_pio_write()
604 outb(buf[actual++], iobase+TBR); in w83977af_pio_write()
611 outb(set, iobase+SSR); in w83977af_pio_write()
625 int iobase; in w83977af_dma_xmit_complete() local
632 iobase = self->io.fir_base; in w83977af_dma_xmit_complete()
635 set = inb(iobase+SSR); in w83977af_dma_xmit_complete()
638 switch_bank(iobase, SET0); in w83977af_dma_xmit_complete()
639 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_xmit_complete()
642 if (inb(iobase+AUDR) & AUDR_UNDR) { in w83977af_dma_xmit_complete()
649 outb(AUDR_UNDR, iobase+AUDR); in w83977af_dma_xmit_complete()
664 outb(set, iobase+SSR); in w83977af_dma_xmit_complete()
676 int iobase; in w83977af_dma_receive() local
686 iobase= self->io.fir_base; in w83977af_dma_receive()
689 set = inb(iobase+SSR); in w83977af_dma_receive()
692 switch_bank(iobase, SET0); in w83977af_dma_receive()
693 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
696 switch_bank(iobase, SET2); in w83977af_dma_receive()
697 outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL, in w83977af_dma_receive()
698 iobase+ADCR1); in w83977af_dma_receive()
720 switch_bank(iobase, SET0); in w83977af_dma_receive()
721 outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR); in w83977af_dma_receive()
725 switch_bank(iobase, SET0); in w83977af_dma_receive()
727 hcr = inb(iobase+HCR); in w83977af_dma_receive()
728 outb(hcr | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
732 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
735 outb(set, iobase+SSR); in w83977af_dma_receive()
751 int iobase; in w83977af_dma_receive_complete() local
759 iobase = self->io.fir_base; in w83977af_dma_receive_complete()
762 set = inb(iobase+SSR); in w83977af_dma_receive_complete()
764 iobase = self->io.fir_base; in w83977af_dma_receive_complete()
767 switch_bank(iobase, SET5); in w83977af_dma_receive_complete()
768 while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) { in w83977af_dma_receive_complete()
771 st_fifo->entries[st_fifo->tail].len = inb(iobase+RFLFL); in w83977af_dma_receive_complete()
772 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8; in w83977af_dma_receive_complete()
814 switch_bank(iobase, SET0); in w83977af_dma_receive_complete()
815 if (inb(iobase+USR) & USR_RDR) { in w83977af_dma_receive_complete()
824 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
856 outb(set, iobase+SSR); in w83977af_dma_receive_complete()
870 int iobase; in w83977af_pio_receive() local
874 iobase = self->io.fir_base; in w83977af_pio_receive()
878 byte = inb(iobase+RBR); in w83977af_pio_receive()
881 } while (inb(iobase+USR) & USR_RDR); /* Data available */ in w83977af_pio_receive()
895 int iobase; in w83977af_sir_interrupt() local
899 iobase = self->io.fir_base; in w83977af_sir_interrupt()
917 set = inb(iobase+SSR); in w83977af_sir_interrupt()
918 switch_bank(iobase, SET0); in w83977af_sir_interrupt()
919 outb(AUDR_SFEND, iobase+AUDR); in w83977af_sir_interrupt()
920 outb(set, iobase+SSR); in w83977af_sir_interrupt()
963 int iobase; in w83977af_fir_interrupt() local
965 iobase = self->io.fir_base; in w83977af_fir_interrupt()
966 set = inb(iobase+SSR); in w83977af_fir_interrupt()
978 switch_bank(iobase, SET4); in w83977af_fir_interrupt()
979 outb(0x01, iobase+TMRL); /* 1 ms */ in w83977af_fir_interrupt()
980 outb(0x00, iobase+TMRH); in w83977af_fir_interrupt()
983 outb(IR_MSL_EN_TMR, iobase+IR_MSL); in w83977af_fir_interrupt()
991 switch_bank(iobase, SET4); in w83977af_fir_interrupt()
992 outb(0, iobase+IR_MSL); in w83977af_fir_interrupt()
1000 w83977af_dma_write(self, iobase); in w83977af_fir_interrupt()
1027 outb(set, iobase+SSR); in w83977af_fir_interrupt()
1043 int iobase; in w83977af_interrupt() local
1047 iobase = self->io.fir_base; in w83977af_interrupt()
1050 set = inb(iobase+SSR); in w83977af_interrupt()
1051 switch_bank(iobase, SET0); in w83977af_interrupt()
1053 icr = inb(iobase+ICR); in w83977af_interrupt()
1054 isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */ in w83977af_interrupt()
1056 outb(0, iobase+ICR); /* Disable interrupts */ in w83977af_interrupt()
1066 outb(icr, iobase+ICR); /* Restore (new) interrupts */ in w83977af_interrupt()
1067 outb(set, iobase+SSR); /* Restore bank register */ in w83977af_interrupt()
1080 int iobase; in w83977af_is_receiving() local
1086 iobase = self->io.fir_base; in w83977af_is_receiving()
1089 set = inb(iobase+SSR); in w83977af_is_receiving()
1090 switch_bank(iobase, SET2); in w83977af_is_receiving()
1091 if ((inb(iobase+RXFDTH) & 0x3f) != 0) { in w83977af_is_receiving()
1095 outb(set, iobase+SSR); in w83977af_is_receiving()
1111 int iobase; in w83977af_net_open() local
1121 iobase = self->io.fir_base; in w83977af_net_open()
1137 set = inb(iobase+SSR); in w83977af_net_open()
1140 switch_bank(iobase, SET0); in w83977af_net_open()
1142 outb(ICR_EFSFI, iobase+ICR); in w83977af_net_open()
1145 outb(ICR_ERBRI, iobase+ICR); in w83977af_net_open()
1148 outb(set, iobase+SSR); in w83977af_net_open()
1174 int iobase; in w83977af_net_close() local
1183 iobase = self->io.fir_base; in w83977af_net_close()
1196 set = inb(iobase+SSR); in w83977af_net_close()
1199 switch_bank(iobase, SET0); in w83977af_net_close()
1200 outb(0, iobase+ICR); in w83977af_net_close()
1206 outb(set, iobase+SSR); in w83977af_net_close()