447 	int ret;  in amd_xgbe_an_enable_kr_training()  local
449 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);  in amd_xgbe_an_enable_kr_training()
450 	if (ret < 0)  in amd_xgbe_an_enable_kr_training()
451 		return ret;  in amd_xgbe_an_enable_kr_training()
453 	ret |= XGBE_PHY_KR_TRAINING_ENABLE;  in amd_xgbe_an_enable_kr_training()
454 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);  in amd_xgbe_an_enable_kr_training()
461 	int ret;  in amd_xgbe_an_disable_kr_training()  local
463 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);  in amd_xgbe_an_disable_kr_training()
464 	if (ret < 0)  in amd_xgbe_an_disable_kr_training()
465 		return ret;  in amd_xgbe_an_disable_kr_training()
467 	ret &= ~XGBE_PHY_KR_TRAINING_ENABLE;  in amd_xgbe_an_disable_kr_training()
468 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);  in amd_xgbe_an_disable_kr_training()
475 	int ret;  in amd_xgbe_phy_pcs_power_cycle()  local
477 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_pcs_power_cycle()
478 	if (ret < 0)  in amd_xgbe_phy_pcs_power_cycle()
479 		return ret;  in amd_xgbe_phy_pcs_power_cycle()
481 	ret |= MDIO_CTRL1_LPOWER;  in amd_xgbe_phy_pcs_power_cycle()
482 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_pcs_power_cycle()
486 	ret &= ~MDIO_CTRL1_LPOWER;  in amd_xgbe_phy_pcs_power_cycle()
487 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_pcs_power_cycle()
532 	int ret;  in amd_xgbe_phy_xgmii_mode()  local
535 	ret = amd_xgbe_an_enable_kr_training(phydev);  in amd_xgbe_phy_xgmii_mode()
536 	if (ret < 0)  in amd_xgbe_phy_xgmii_mode()
537 		return ret;  in amd_xgbe_phy_xgmii_mode()
540 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);  in amd_xgbe_phy_xgmii_mode()
541 	if (ret < 0)  in amd_xgbe_phy_xgmii_mode()
542 		return ret;  in amd_xgbe_phy_xgmii_mode()
544 	ret &= ~MDIO_PCS_CTRL2_TYPE;  in amd_xgbe_phy_xgmii_mode()
545 	ret |= MDIO_PCS_CTRL2_10GBR;  in amd_xgbe_phy_xgmii_mode()
546 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);  in amd_xgbe_phy_xgmii_mode()
548 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_xgmii_mode()
549 	if (ret < 0)  in amd_xgbe_phy_xgmii_mode()
550 		return ret;  in amd_xgbe_phy_xgmii_mode()
552 	ret &= ~MDIO_CTRL1_SPEEDSEL;  in amd_xgbe_phy_xgmii_mode()
553 	ret |= MDIO_CTRL1_SPEED10G;  in amd_xgbe_phy_xgmii_mode()
554 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_xgmii_mode()
556 	ret = amd_xgbe_phy_pcs_power_cycle(phydev);  in amd_xgbe_phy_xgmii_mode()
557 	if (ret < 0)  in amd_xgbe_phy_xgmii_mode()
558 		return ret;  in amd_xgbe_phy_xgmii_mode()
588 	int ret;  in amd_xgbe_phy_gmii_2500_mode()  local
591 	ret = amd_xgbe_an_disable_kr_training(phydev);  in amd_xgbe_phy_gmii_2500_mode()
592 	if (ret < 0)  in amd_xgbe_phy_gmii_2500_mode()
593 		return ret;  in amd_xgbe_phy_gmii_2500_mode()
596 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);  in amd_xgbe_phy_gmii_2500_mode()
597 	if (ret < 0)  in amd_xgbe_phy_gmii_2500_mode()
598 		return ret;  in amd_xgbe_phy_gmii_2500_mode()
600 	ret &= ~MDIO_PCS_CTRL2_TYPE;  in amd_xgbe_phy_gmii_2500_mode()
601 	ret |= MDIO_PCS_CTRL2_10GBX;  in amd_xgbe_phy_gmii_2500_mode()
602 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);  in amd_xgbe_phy_gmii_2500_mode()
604 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_gmii_2500_mode()
605 	if (ret < 0)  in amd_xgbe_phy_gmii_2500_mode()
606 		return ret;  in amd_xgbe_phy_gmii_2500_mode()
608 	ret &= ~MDIO_CTRL1_SPEEDSEL;  in amd_xgbe_phy_gmii_2500_mode()
609 	ret |= MDIO_CTRL1_SPEED1G;  in amd_xgbe_phy_gmii_2500_mode()
610 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_gmii_2500_mode()
612 	ret = amd_xgbe_phy_pcs_power_cycle(phydev);  in amd_xgbe_phy_gmii_2500_mode()
613 	if (ret < 0)  in amd_xgbe_phy_gmii_2500_mode()
614 		return ret;  in amd_xgbe_phy_gmii_2500_mode()
644 	int ret;  in amd_xgbe_phy_gmii_mode()  local
647 	ret = amd_xgbe_an_disable_kr_training(phydev);  in amd_xgbe_phy_gmii_mode()
648 	if (ret < 0)  in amd_xgbe_phy_gmii_mode()
649 		return ret;  in amd_xgbe_phy_gmii_mode()
652 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);  in amd_xgbe_phy_gmii_mode()
653 	if (ret < 0)  in amd_xgbe_phy_gmii_mode()
654 		return ret;  in amd_xgbe_phy_gmii_mode()
656 	ret &= ~MDIO_PCS_CTRL2_TYPE;  in amd_xgbe_phy_gmii_mode()
657 	ret |= MDIO_PCS_CTRL2_10GBX;  in amd_xgbe_phy_gmii_mode()
658 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);  in amd_xgbe_phy_gmii_mode()
660 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_gmii_mode()
661 	if (ret < 0)  in amd_xgbe_phy_gmii_mode()
662 		return ret;  in amd_xgbe_phy_gmii_mode()
664 	ret &= ~MDIO_CTRL1_SPEEDSEL;  in amd_xgbe_phy_gmii_mode()
665 	ret |= MDIO_CTRL1_SPEED1G;  in amd_xgbe_phy_gmii_mode()
666 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_gmii_mode()
668 	ret = amd_xgbe_phy_pcs_power_cycle(phydev);  in amd_xgbe_phy_gmii_mode()
669 	if (ret < 0)  in amd_xgbe_phy_gmii_mode()
670 		return ret;  in amd_xgbe_phy_gmii_mode()
700 	int ret;  in amd_xgbe_phy_cur_mode()  local
702 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);  in amd_xgbe_phy_cur_mode()
703 	if (ret < 0)  in amd_xgbe_phy_cur_mode()
704 		return ret;  in amd_xgbe_phy_cur_mode()
706 	if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)  in amd_xgbe_phy_cur_mode()
727 	int ret;  in amd_xgbe_phy_switch_mode()  local
732 			ret = amd_xgbe_phy_gmii_mode(phydev);  in amd_xgbe_phy_switch_mode()
734 			ret = amd_xgbe_phy_gmii_2500_mode(phydev);  in amd_xgbe_phy_switch_mode()
736 		ret = amd_xgbe_phy_xgmii_mode(phydev);  in amd_xgbe_phy_switch_mode()
739 	return ret;  in amd_xgbe_phy_switch_mode()
746 	int ret;  in amd_xgbe_phy_set_mode()  local
748 	ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);  in amd_xgbe_phy_set_mode()
749 	if (ret)  in amd_xgbe_phy_set_mode()
750 		return ret;  in amd_xgbe_phy_set_mode()
753 		ret = amd_xgbe_phy_switch_mode(phydev);  in amd_xgbe_phy_set_mode()
755 	return ret;  in amd_xgbe_phy_set_mode()
800 	int ret;  in amd_xgbe_phy_set_an()  local
802 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);  in amd_xgbe_phy_set_an()
803 	if (ret < 0)  in amd_xgbe_phy_set_an()
804 		return ret;  in amd_xgbe_phy_set_an()
806 	ret &= ~MDIO_AN_CTRL1_ENABLE;  in amd_xgbe_phy_set_an()
809 		ret |= MDIO_AN_CTRL1_ENABLE;  in amd_xgbe_phy_set_an()
812 		ret |= MDIO_AN_CTRL1_RESTART;  in amd_xgbe_phy_set_an()
814 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);  in amd_xgbe_phy_set_an()
833 	int ad_reg, lp_reg, ret;  in amd_xgbe_an_tx_training()  local
850 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);  in amd_xgbe_an_tx_training()
851 	if (ret < 0)  in amd_xgbe_an_tx_training()
854 	ret &= ~XGBE_PHY_FEC_MASK;  in amd_xgbe_an_tx_training()
856 		ret |= priv->fec_ability;  in amd_xgbe_an_tx_training()
858 	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);  in amd_xgbe_an_tx_training()
861 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);  in amd_xgbe_an_tx_training()
862 	if (ret < 0)  in amd_xgbe_an_tx_training()
865 	if (ret & XGBE_PHY_KR_TRAINING_ENABLE) {  in amd_xgbe_an_tx_training()
868 		ret |= XGBE_PHY_KR_TRAINING_START;  in amd_xgbe_an_tx_training()
870 			      ret);  in amd_xgbe_an_tx_training()
899 	int ret, ad_reg, lp_reg;  in amd_xgbe_an_rx_bpa()  local
902 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);  in amd_xgbe_an_rx_bpa()
903 	if (ret < 0)  in amd_xgbe_an_rx_bpa()
908 	if (!(ret & link_support))  in amd_xgbe_an_rx_bpa()
949 	int ret;  in amd_xgbe_an_page_received()  local
970 		ret = amd_xgbe_an_rx_bpa(phydev, state);  in amd_xgbe_an_page_received()
974 		ret = amd_xgbe_an_rx_xnp(phydev, state);  in amd_xgbe_an_page_received()
978 		ret = AMD_XGBE_AN_ERROR;  in amd_xgbe_an_page_received()
981 	return ret;  in amd_xgbe_an_page_received()
987 	int ret;  in amd_xgbe_an_incompat_link()  local
1009 	ret = amd_xgbe_phy_disable_an(phydev);  in amd_xgbe_an_incompat_link()
1010 	if (ret)  in amd_xgbe_an_incompat_link()
1013 	ret = amd_xgbe_phy_switch_mode(phydev);  in amd_xgbe_an_incompat_link()
1014 	if (ret)  in amd_xgbe_an_incompat_link()
1017 	ret = amd_xgbe_phy_restart_an(phydev);  in amd_xgbe_an_incompat_link()
1018 	if (ret)  in amd_xgbe_an_incompat_link()
1156 	int ret;  in amd_xgbe_an_init()  local
1159 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);  in amd_xgbe_an_init()
1160 	if (ret < 0)  in amd_xgbe_an_init()
1161 		return ret;  in amd_xgbe_an_init()
1164 		ret |= 0xc000;  in amd_xgbe_an_init()
1166 		ret &= ~0xc000;  in amd_xgbe_an_init()
1168 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);  in amd_xgbe_an_init()
1171 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);  in amd_xgbe_an_init()
1172 	if (ret < 0)  in amd_xgbe_an_init()
1173 		return ret;  in amd_xgbe_an_init()
1176 		ret |= 0x80;  in amd_xgbe_an_init()
1178 		ret &= ~0x80;  in amd_xgbe_an_init()
1182 		ret |= 0x20;  in amd_xgbe_an_init()
1184 		ret &= ~0x20;  in amd_xgbe_an_init()
1186 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);  in amd_xgbe_an_init()
1189 	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);  in amd_xgbe_an_init()
1190 	if (ret < 0)  in amd_xgbe_an_init()
1191 		return ret;  in amd_xgbe_an_init()
1194 		ret |= 0x400;  in amd_xgbe_an_init()
1196 		ret &= ~0x400;  in amd_xgbe_an_init()
1199 		ret |= 0x800;  in amd_xgbe_an_init()
1201 		ret &= ~0x800;  in amd_xgbe_an_init()
1204 	ret &= ~XNP_NP_EXCHANGE;  in amd_xgbe_an_init()
1206 	phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);  in amd_xgbe_an_init()
1213 	int count, ret;  in amd_xgbe_phy_soft_reset()  local
1215 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_soft_reset()
1216 	if (ret < 0)  in amd_xgbe_phy_soft_reset()
1217 		return ret;  in amd_xgbe_phy_soft_reset()
1219 	ret |= MDIO_CTRL1_RESET;  in amd_xgbe_phy_soft_reset()
1220 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_soft_reset()
1225 		ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_soft_reset()
1226 		if (ret < 0)  in amd_xgbe_phy_soft_reset()
1227 			return ret;  in amd_xgbe_phy_soft_reset()
1228 	} while ((ret & MDIO_CTRL1_RESET) && --count);  in amd_xgbe_phy_soft_reset()
1230 	if (ret & MDIO_CTRL1_RESET)  in amd_xgbe_phy_soft_reset()
1234 	ret = amd_xgbe_phy_disable_an(phydev);  in amd_xgbe_phy_soft_reset()
1235 	if (ret < 0)  in amd_xgbe_phy_soft_reset()
1236 		return ret;  in amd_xgbe_phy_soft_reset()
1248 	int ret;  in amd_xgbe_phy_config_init()  local
1262 		ret = devm_request_irq(priv->dev, priv->an_irq,  in amd_xgbe_phy_config_init()
1265 		if (ret) {  in amd_xgbe_phy_config_init()
1268 			return ret;  in amd_xgbe_phy_config_init()
1278 		ret = amd_xgbe_phy_xgmii_mode(phydev);  in amd_xgbe_phy_config_init()
1280 		ret = amd_xgbe_phy_gmii_mode(phydev);  in amd_xgbe_phy_config_init()
1282 		ret = amd_xgbe_phy_gmii_2500_mode(phydev);  in amd_xgbe_phy_config_init()
1284 		ret = -EINVAL;  in amd_xgbe_phy_config_init()
1285 	if (ret < 0)  in amd_xgbe_phy_config_init()
1286 		return ret;  in amd_xgbe_phy_config_init()
1289 	ret = amd_xgbe_an_init(phydev);  in amd_xgbe_phy_config_init()
1290 	if (ret)  in amd_xgbe_phy_config_init()
1291 		return ret;  in amd_xgbe_phy_config_init()
1301 	int ret;  in amd_xgbe_phy_setup_forced()  local
1304 	ret = amd_xgbe_phy_disable_an(phydev);  in amd_xgbe_phy_setup_forced()
1305 	if (ret < 0)  in amd_xgbe_phy_setup_forced()
1306 		return ret;  in amd_xgbe_phy_setup_forced()
1311 		ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);  in amd_xgbe_phy_setup_forced()
1316 		ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);  in amd_xgbe_phy_setup_forced()
1320 		ret = -EINVAL;  in amd_xgbe_phy_setup_forced()
1323 	if (ret < 0)  in amd_xgbe_phy_setup_forced()
1324 		return ret;  in amd_xgbe_phy_setup_forced()
1340 	int ret;  in __amd_xgbe_phy_config_aneg()  local
1354 		ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);  in __amd_xgbe_phy_config_aneg()
1357 		ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);  in __amd_xgbe_phy_config_aneg()
1359 		ret = -EINVAL;  in __amd_xgbe_phy_config_aneg()
1360 	if (ret < 0) {  in __amd_xgbe_phy_config_aneg()
1362 		return ret;  in __amd_xgbe_phy_config_aneg()
1366 	ret = amd_xgbe_phy_disable_an(phydev);  in __amd_xgbe_phy_config_aneg()
1367 	if (ret < 0)  in __amd_xgbe_phy_config_aneg()
1368 		return ret;  in __amd_xgbe_phy_config_aneg()
1382 	ret = amd_xgbe_an_init(phydev);  in __amd_xgbe_phy_config_aneg()
1383 	if (ret)  in __amd_xgbe_phy_config_aneg()
1384 		return ret;  in __amd_xgbe_phy_config_aneg()
1393 	int ret;  in amd_xgbe_phy_config_aneg()  local
1397 	ret = __amd_xgbe_phy_config_aneg(phydev);  in amd_xgbe_phy_config_aneg()
1401 	return ret;  in amd_xgbe_phy_config_aneg()
1414 	int ret;  in amd_xgbe_phy_update_link()  local
1425 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);  in amd_xgbe_phy_update_link()
1426 	if (ret < 0)  in amd_xgbe_phy_update_link()
1427 		return ret;  in amd_xgbe_phy_update_link()
1429 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);  in amd_xgbe_phy_update_link()
1430 	if (ret < 0)  in amd_xgbe_phy_update_link()
1431 		return ret;  in amd_xgbe_phy_update_link()
1433 	phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;  in amd_xgbe_phy_update_link()
1442 	int ret, ad_ret, lp_ret;  in amd_xgbe_phy_read_status()  local
1444 	ret = amd_xgbe_phy_update_link(phydev);  in amd_xgbe_phy_read_status()
1445 	if (ret)  in amd_xgbe_phy_read_status()
1446 		return ret;  in amd_xgbe_phy_read_status()
1480 			ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);  in amd_xgbe_phy_read_status()
1481 			if (ret)  in amd_xgbe_phy_read_status()
1482 				return ret;  in amd_xgbe_phy_read_status()
1494 			ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);  in amd_xgbe_phy_read_status()
1495 			if (ret)  in amd_xgbe_phy_read_status()
1496 				return ret;  in amd_xgbe_phy_read_status()
1525 	int ret;  in amd_xgbe_phy_suspend()  local
1529 	ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);  in amd_xgbe_phy_suspend()
1530 	if (ret < 0)  in amd_xgbe_phy_suspend()
1533 	priv->lpm_ctrl = ret;  in amd_xgbe_phy_suspend()
1535 	ret |= MDIO_CTRL1_LPOWER;  in amd_xgbe_phy_suspend()
1536 	phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);  in amd_xgbe_phy_suspend()
1538 	ret = 0;  in amd_xgbe_phy_suspend()
1543 	return ret;  in amd_xgbe_phy_suspend()
1582 	int ret;  in amd_xgbe_phy_probe()  local
1609 			ret = -EINVAL;  in amd_xgbe_phy_probe()
1618 			ret = -EINVAL;  in amd_xgbe_phy_probe()
1642 		ret = PTR_ERR(priv->rxtx_regs);  in amd_xgbe_phy_probe()
1651 		ret = PTR_ERR(priv->sir0_regs);  in amd_xgbe_phy_probe()
1660 		ret = PTR_ERR(priv->sir1_regs);  in amd_xgbe_phy_probe()
1665 	ret = platform_get_irq(phy_pdev, phy_irqnum);  in amd_xgbe_phy_probe()
1666 	if (ret < 0) {  in amd_xgbe_phy_probe()
1670 	priv->an_irq = ret;  in amd_xgbe_phy_probe()
1673 	ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY,  in amd_xgbe_phy_probe()
1675 	if (ret) {  in amd_xgbe_phy_probe()
1688 		ret = -EINVAL;  in amd_xgbe_phy_probe()
1693 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1697 		if (ret) {  in amd_xgbe_phy_probe()
1708 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1712 		if (ret) {  in amd_xgbe_phy_probe()
1723 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1727 		if (ret) {  in amd_xgbe_phy_probe()
1738 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1742 		if (ret) {  in amd_xgbe_phy_probe()
1753 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1757 		if (ret) {  in amd_xgbe_phy_probe()
1769 		ret = device_property_read_u32_array(phy_dev,  in amd_xgbe_phy_probe()
1773 		if (ret) {  in amd_xgbe_phy_probe()
1798 	ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY);  in amd_xgbe_phy_probe()
1799 	if (ret < 0)  in amd_xgbe_phy_probe()
1800 		return ret;  in amd_xgbe_phy_probe()
1801 	priv->fec_ability = ret & XGBE_PHY_FEC_MASK;  in amd_xgbe_phy_probe()
1836 	return ret;  in amd_xgbe_phy_probe()