51 static void phy_write_exp(struct phy_device *phydev,  in phy_write_exp()  argument
54 	phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);  in phy_write_exp()
55 	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);  in phy_write_exp()
58 static void phy_write_misc(struct phy_device *phydev,  in phy_write_misc()  argument
63 	phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);  in phy_write_misc()
65 	tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);  in phy_write_misc()
67 	phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);  in phy_write_misc()
70 	phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);  in phy_write_misc()
72 	phy_write(phydev, MII_BCM54XX_EXP_DATA, value);  in phy_write_misc()
75 static void r_rc_cal_reset(struct phy_device *phydev)  in r_rc_cal_reset()  argument
78 	phy_write_exp(phydev, 0x00b0, 0x0010);  in r_rc_cal_reset()
81 	phy_write_exp(phydev, 0x00b0, 0x0000);  in r_rc_cal_reset()
84 static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_b0_afe_config_init()  argument
89 	phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);  in bcm7xxx_28nm_b0_afe_config_init()
92 	phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);  in bcm7xxx_28nm_b0_afe_config_init()
97 	phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);  in bcm7xxx_28nm_b0_afe_config_init()
100 	phy_write_misc(phydev, DSP_TAP10, 0x690b);  in bcm7xxx_28nm_b0_afe_config_init()
103 	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);  in bcm7xxx_28nm_b0_afe_config_init()
105 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_b0_afe_config_init()
108 	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);  in bcm7xxx_28nm_b0_afe_config_init()
111 	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);  in bcm7xxx_28nm_b0_afe_config_init()
114 	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_b0_afe_config_init()
117 	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);  in bcm7xxx_28nm_b0_afe_config_init()
120 	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);  in bcm7xxx_28nm_b0_afe_config_init()
125 static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_d0_afe_config_init()  argument
128 	phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);  in bcm7xxx_28nm_d0_afe_config_init()
131 	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_d0_afe_config_init()
134 	phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);  in bcm7xxx_28nm_d0_afe_config_init()
137 	phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);  in bcm7xxx_28nm_d0_afe_config_init()
140 	phy_write_misc(phydev, AFE_TX_CONFIG, 0x0061);  in bcm7xxx_28nm_d0_afe_config_init()
143 	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_d0_afe_config_init()
146 	phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);  in bcm7xxx_28nm_d0_afe_config_init()
151 	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_d0_afe_config_init()
154 	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_d0_afe_config_init()
157 	phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_d0_afe_config_init()
160 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_d0_afe_config_init()
165 static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_e0_plus_afe_config_init()  argument
168 	phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);  in bcm7xxx_28nm_e0_plus_afe_config_init()
171 	phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);  in bcm7xxx_28nm_e0_plus_afe_config_init()
176 	phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);  in bcm7xxx_28nm_e0_plus_afe_config_init()
179 	phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0x0010);  in bcm7xxx_28nm_e0_plus_afe_config_init()
182 	phy_write_misc(phydev, DSP_TAP10, 0x011b);  in bcm7xxx_28nm_e0_plus_afe_config_init()
185 	r_rc_cal_reset(phydev);  in bcm7xxx_28nm_e0_plus_afe_config_init()
190 static int bcm7xxx_apd_enable(struct phy_device *phydev)  in bcm7xxx_apd_enable()  argument
195 	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);  in bcm7xxx_apd_enable()
200 	bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);  in bcm7xxx_apd_enable()
203 	val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);  in bcm7xxx_apd_enable()
208 	return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);  in bcm7xxx_apd_enable()
211 static int bcm7xxx_eee_enable(struct phy_device *phydev)  in bcm7xxx_eee_enable()  argument
215 	val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,  in bcm7xxx_eee_enable()
216 				    MDIO_MMD_AN, phydev->addr);  in bcm7xxx_eee_enable()
223 	phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,  in bcm7xxx_eee_enable()
224 			       MDIO_MMD_AN, phydev->addr, val);  in bcm7xxx_eee_enable()
227 	val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,  in bcm7xxx_eee_enable()
228 				    MDIO_MMD_AN, phydev->addr);  in bcm7xxx_eee_enable()
231 	phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,  in bcm7xxx_eee_enable()
232 			       MDIO_MMD_AN, phydev->addr, val);  in bcm7xxx_eee_enable()
237 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)  in bcm7xxx_28nm_config_init()  argument
239 	u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);  in bcm7xxx_28nm_config_init()
240 	u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);  in bcm7xxx_28nm_config_init()
244 		     dev_name(&phydev->dev), phydev->drv->name, rev, patch);  in bcm7xxx_28nm_config_init()
248 		ret = bcm7xxx_28nm_b0_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
251 		ret = bcm7xxx_28nm_d0_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
257 		ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);  in bcm7xxx_28nm_config_init()
266 	ret = bcm7xxx_eee_enable(phydev);  in bcm7xxx_28nm_config_init()
270 	return bcm7xxx_apd_enable(phydev);  in bcm7xxx_28nm_config_init()
273 static int bcm7xxx_28nm_resume(struct phy_device *phydev)  in bcm7xxx_28nm_resume()  argument
278 	ret = bcm7xxx_28nm_config_init(phydev);  in bcm7xxx_28nm_resume()
287 	return genphy_config_aneg(phydev);  in bcm7xxx_28nm_resume()
309 static int bcm7xxx_config_init(struct phy_device *phydev)  in bcm7xxx_config_init()  argument
314 	phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);  in bcm7xxx_config_init()
315 	phy_read(phydev, MII_BCM7XXX_AUX_MODE);  in bcm7xxx_config_init()
318 	if (phydev->supported & PHY_GBIT_FEATURES)  in bcm7xxx_config_init()
322 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,  in bcm7xxx_config_init()
328 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);  in bcm7xxx_config_init()
332 	phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);  in bcm7xxx_config_init()
334 	phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);  in bcm7xxx_config_init()
337 	ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);  in bcm7xxx_config_init()
347 static int bcm7xxx_suspend(struct phy_device *phydev)  in bcm7xxx_suspend()  argument
364 		ret = phy_write(phydev,  in bcm7xxx_suspend()
374 static int bcm7xxx_dummy_config_init(struct phy_device *phydev)  in bcm7xxx_dummy_config_init()  argument