Lines Matching refs:reg
212 int reg, err; in bcm54xx_config_init() local
214 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm54xx_config_init()
215 if (reg < 0) in bcm54xx_config_init()
216 return reg; in bcm54xx_config_init()
219 reg |= MII_BCM54XX_ECR_IM; in bcm54xx_config_init()
220 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
225 reg = ~(MII_BCM54XX_INT_DUPLEX | in bcm54xx_config_init()
228 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
249 int err, reg; in bcm5482_config_init() local
257 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_SSD); in bcm5482_config_init()
259 reg | in bcm5482_config_init()
266 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD; in bcm5482_config_init()
267 err = bcm54xx_exp_read(phydev, reg); in bcm5482_config_init()
270 err = bcm54xx_exp_write(phydev, reg, err | in bcm5482_config_init()
279 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD; in bcm5482_config_init()
280 err = bcm54xx_exp_read(phydev, reg); in bcm5482_config_init()
283 err = bcm54xx_exp_write(phydev, reg, in bcm5482_config_init()
291 reg = bcm54xx_shadow_read(phydev, BCM5482_SHD_MODE); in bcm5482_config_init()
293 reg | BCM5482_SHD_MODE_1000BX); in bcm5482_config_init()
339 int reg; in bcm54xx_ack_interrupt() local
342 reg = phy_read(phydev, MII_BCM54XX_ISR); in bcm54xx_ack_interrupt()
343 if (reg < 0) in bcm54xx_ack_interrupt()
344 return reg; in bcm54xx_ack_interrupt()
351 int reg, err; in bcm54xx_config_intr() local
353 reg = phy_read(phydev, MII_BCM54XX_ECR); in bcm54xx_config_intr()
354 if (reg < 0) in bcm54xx_config_intr()
355 return reg; in bcm54xx_config_intr()
358 reg &= ~MII_BCM54XX_ECR_IM; in bcm54xx_config_intr()
360 reg |= MII_BCM54XX_ECR_IM; in bcm54xx_config_intr()
362 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_intr()
375 u16 reg; in bcm5481_config_aneg() local
387 reg = 0x7 | (0x7 << 12); in bcm5481_config_aneg()
388 phy_write(phydev, 0x18, reg); in bcm5481_config_aneg()
390 reg = phy_read(phydev, 0x18); in bcm5481_config_aneg()
392 reg |= (1 << 8); in bcm5481_config_aneg()
394 reg |= (1 << 15); in bcm5481_config_aneg()
395 phy_write(phydev, 0x18, reg); in bcm5481_config_aneg()
401 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set) in brcm_phy_setbits() argument
405 val = phy_read(phydev, reg); in brcm_phy_setbits()
409 return phy_write(phydev, reg, val | set); in brcm_phy_setbits()
414 int reg, err, err2, brcmtest; in brcm_fet_config_init() local
421 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_init()
422 if (reg < 0) in brcm_fet_config_init()
423 return reg; in brcm_fet_config_init()
426 reg = MII_BRCM_FET_IR_DUPLEX_EN | in brcm_fet_config_init()
432 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
441 reg = brcmtest | MII_BRCM_FET_BT_SRE; in brcm_fet_config_init()
443 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
448 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4); in brcm_fet_config_init()
449 if (reg < 0) { in brcm_fet_config_init()
450 err = reg; in brcm_fet_config_init()
454 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK; in brcm_fet_config_init()
455 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1; in brcm_fet_config_init()
457 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
484 int reg; in brcm_fet_ack_interrupt() local
487 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_ack_interrupt()
488 if (reg < 0) in brcm_fet_ack_interrupt()
489 return reg; in brcm_fet_ack_interrupt()
496 int reg, err; in brcm_fet_config_intr() local
498 reg = phy_read(phydev, MII_BRCM_FET_INTREG); in brcm_fet_config_intr()
499 if (reg < 0) in brcm_fet_config_intr()
500 return reg; in brcm_fet_config_intr()
503 reg &= ~MII_BRCM_FET_IR_MASK; in brcm_fet_config_intr()
505 reg |= MII_BRCM_FET_IR_MASK; in brcm_fet_config_intr()
507 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_intr()