1256 struct ath5k_hw {  struct
1257 	struct ath_common       common;
1259 	struct pci_dev		*pdev;
1260 	struct device		*dev;		/* for dma mapping */
1261 	int irq;
1262 	u16 devid;
1263 	void __iomem		*iobase;	/* address of the device */
1264 	struct mutex		lock;		/* dev-level lock */
1265 	struct ieee80211_hw	*hw;		/* IEEE 802.11 common */
1266 	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
1267 	struct ieee80211_channel channels[ATH_CHAN_MAX];
1268 	struct ieee80211_rate	rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1269 	s8			rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
1270 	enum nl80211_iftype	opmode;
1273 	struct ath5k_dbg_info	debug;		/* debug info */
1276 	struct ath5k_buf	*bufptr;	/* allocated buffer ptr */
1277 	struct ath5k_desc	*desc;		/* TX/RX descriptors */
1278 	dma_addr_t		desc_daddr;	/* DMA (physical) address */
1279 	size_t			desc_len;	/* size of TX/RX descriptors */
1288 	unsigned int		filter_flags;	/* HW flags, AR5K_RX_FILTER_* */
1289 	unsigned int		fif_filter_flags; /* Current FIF_* filter flags */
1290 	struct ieee80211_channel *curchan;	/* current h/w channel */
1292 	u16			nvifs;
1294 	enum ath5k_int		imask;		/* interrupt mask copy */
1296 	spinlock_t		irqlock;
1297 	bool			rx_pending;	/* rx tasklet pending */
1298 	bool			tx_pending;	/* tx tasklet pending */
1300 	u8			bssidmask[ETH_ALEN];
1302 	unsigned int		led_pin,	/* GPIO pin for driving LED */
1303 				led_on;		/* pin setting for LED on */
1305 	struct work_struct	reset_work;	/* deferred chip reset */
1306 	struct work_struct	calib_work;	/* deferred phy calibration */
1308 	struct list_head	rxbuf;		/* receive buffer */
1309 	spinlock_t		rxbuflock;
1310 	u32			*rxlink;	/* link ptr in last RX desc */
1311 	struct tasklet_struct	rxtq;		/* rx intr tasklet */
1312 	struct ath5k_led	rx_led;		/* rx led */
1314 	struct list_head	txbuf;		/* transmit buffer */
1315 	spinlock_t		txbuflock;
1316 	unsigned int		txbuf_len;	/* buf count in txbuf list */
1317 	struct ath5k_txq	txqs[AR5K_NUM_TX_QUEUES];	/* tx queues */
1318 	struct tasklet_struct	txtq;		/* tx intr tasklet */
1319 	struct ath5k_led	tx_led;		/* tx led */
1321 	struct ath5k_rfkill	rf_kill;
1323 	spinlock_t		block;		/* protects beacon */
1324 	struct tasklet_struct	beacontq;	/* beacon intr tasklet */
1325 	struct list_head	bcbuf;		/* beacon buffer */
1326 	struct ieee80211_vif	*bslot[ATH_BCBUF];
1327 	u16			num_ap_vifs;
1328 	u16			num_adhoc_vifs;
1329 	u16			num_mesh_vifs;
1330 	unsigned int		bhalq,		/* SW q for outgoing beacons */
1331 				bmisscount,	/* missed beacon transmits */
1332 				bintval,	/* beacon interval in TU */
1333 				bsent;
1334 	unsigned int		nexttbtt;	/* next beacon time in TU */
1335 	struct ath5k_txq	*cabq;		/* content after beacon */
1337 	bool			assoc;		/* associate state */
1338 	bool			enable_beacon;	/* true if beacons are on */
1340 	struct ath5k_statistics	stats;
1342 	struct ath5k_ani_state	ani_state;
1343 	struct tasklet_struct	ani_tasklet;	/* ANI calibration */
1345 	struct delayed_work	tx_complete_work;
1347 	struct survey_info	survey;		/* collected survey info */
1349 	enum ath5k_int		ah_imr;
1351 	struct ieee80211_channel *ah_current_channel;
1352 	bool			ah_iq_cal_needed;
1353 	bool			ah_single_chip;
1355 	enum ath5k_version	ah_version;
1356 	enum ath5k_radio	ah_radio;
1357 	u32			ah_mac_srev;
1358 	u16			ah_mac_version;
1359 	u16			ah_phy_revision;
1360 	u16			ah_radio_5ghz_revision;
1361 	u16			ah_radio_2ghz_revision;
1366 	u8			ah_retry_long;
1367 	u8			ah_retry_short;
1369 	u32			ah_use_32khz_clock;
1371 	u8			ah_coverage_class;
1372 	bool			ah_ack_bitrate_high;
1373 	u8			ah_bwmode;
1374 	bool			ah_short_slot;
1377 	u32			ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1378 	u8			ah_ant_mode;
1379 	u8			ah_tx_ant;
1380 	u8			ah_def_ant;
1382 	struct ath5k_capabilities ah_capabilities;
1384 	struct ath5k_txq_info	ah_txq[AR5K_NUM_TX_QUEUES];
1385 	u32			ah_txq_status;
1386 	u32			ah_txq_imr_txok;
1387 	u32			ah_txq_imr_txerr;
1388 	u32			ah_txq_imr_txurn;
1389 	u32			ah_txq_imr_txdesc;
1390 	u32			ah_txq_imr_txeol;
1391 	u32			ah_txq_imr_cbrorn;
1392 	u32			ah_txq_imr_cbrurn;
1393 	u32			ah_txq_imr_qtrig;
1394 	u32			ah_txq_imr_nofrm;
1396 	u32			ah_txq_isr_txok_all;
1397 	u32			ah_txq_isr_txurn;
1398 	u32			ah_txq_isr_qcborn;
1399 	u32			ah_txq_isr_qcburn;
1400 	u32			ah_txq_isr_qtrig;
1402 	u32			*ah_rf_banks;
1403 	size_t			ah_rf_banks_size;
1404 	size_t			ah_rf_regs_count;
1405 	struct ath5k_gain	ah_gain;
1406 	u8			ah_offset[AR5K_MAX_RF_BANKS];
1409 	struct {
1452 	int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument
1456 	int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument
1458 	int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,  argument