113 ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band,  in ath5k_hw_get_frame_duration()  argument
121 	if (!ah->ah_bwmode) {  in ath5k_hw_get_frame_duration()
122 		__le16 raw_dur = ieee80211_generic_frame_duration(ah->hw,  in ath5k_hw_get_frame_duration()
138 	switch (ah->ah_bwmode) {  in ath5k_hw_get_frame_duration()
175 ath5k_hw_get_default_slottime(struct ath5k_hw *ah)  in ath5k_hw_get_default_slottime()  argument
177 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_get_default_slottime()
180 	switch (ah->ah_bwmode) {  in ath5k_hw_get_default_slottime()
193 		if ((channel->hw_value == AR5K_MODE_11B) && !ah->ah_short_slot)  in ath5k_hw_get_default_slottime()
206 ath5k_hw_get_default_sifs(struct ath5k_hw *ah)  in ath5k_hw_get_default_sifs()  argument
208 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_get_default_sifs()
211 	switch (ah->ah_bwmode) {  in ath5k_hw_get_default_sifs()
243 ath5k_hw_update_mib_counters(struct ath5k_hw *ah)  in ath5k_hw_update_mib_counters()  argument
245 	struct ath5k_statistics *stats = &ah->stats;  in ath5k_hw_update_mib_counters()
248 	stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);  in ath5k_hw_update_mib_counters()
249 	stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);  in ath5k_hw_update_mib_counters()
250 	stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);  in ath5k_hw_update_mib_counters()
251 	stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);  in ath5k_hw_update_mib_counters()
252 	stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);  in ath5k_hw_update_mib_counters()
277 ath5k_hw_write_rate_duration(struct ath5k_hw *ah)  in ath5k_hw_write_rate_duration()  argument
285 	for (i = 0; i < ah->sbands[band].n_bitrates; i++) {  in ath5k_hw_write_rate_duration()
289 		if (ah->ah_ack_bitrate_high)  in ath5k_hw_write_rate_duration()
290 			rate = &ah->sbands[band].bitrates[ack_rates_high[i]];  in ath5k_hw_write_rate_duration()
293 			rate = &ah->sbands[band].bitrates[0];  in ath5k_hw_write_rate_duration()
296 			rate = &ah->sbands[band].bitrates[4];  in ath5k_hw_write_rate_duration()
307 		tx_time = ath5k_hw_get_frame_duration(ah, band, 10,  in ath5k_hw_write_rate_duration()
310 		ath5k_hw_reg_write(ah, tx_time, reg);  in ath5k_hw_write_rate_duration()
315 		tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, true);  in ath5k_hw_write_rate_duration()
316 		ath5k_hw_reg_write(ah, tx_time,  in ath5k_hw_write_rate_duration()
327 ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)  in ath5k_hw_set_ack_timeout()  argument
329 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))  in ath5k_hw_set_ack_timeout()
333 	AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,  in ath5k_hw_set_ack_timeout()
334 		ath5k_hw_htoclock(ah, timeout));  in ath5k_hw_set_ack_timeout()
345 ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)  in ath5k_hw_set_cts_timeout()  argument
347 	if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))  in ath5k_hw_set_cts_timeout()
351 	AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,  in ath5k_hw_set_cts_timeout()
352 			ath5k_hw_htoclock(ah, timeout));  in ath5k_hw_set_cts_timeout()
370 ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)  in ath5k_hw_set_lladdr()  argument
372 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_set_lladdr()
379 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;  in ath5k_hw_set_lladdr()
384 	ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);  in ath5k_hw_set_lladdr()
385 	ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);  in ath5k_hw_set_lladdr()
398 ath5k_hw_set_bssid(struct ath5k_hw *ah)  in ath5k_hw_set_bssid()  argument
400 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_set_bssid()
406 	if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_set_bssid()
412 	ath5k_hw_reg_write(ah,  in ath5k_hw_set_bssid()
415 	ath5k_hw_reg_write(ah,  in ath5k_hw_set_bssid()
421 		ath5k_hw_disable_pspoll(ah);  in ath5k_hw_set_bssid()
425 	AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,  in ath5k_hw_set_bssid()
428 	ath5k_hw_enable_pspoll(ah, NULL, 0);  in ath5k_hw_set_bssid()
447 ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)  in ath5k_hw_set_bssid_mask()  argument
449 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_set_bssid_mask()
454 	if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_set_bssid_mask()
465 ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)  in ath5k_hw_set_mcast_filter()  argument
467 	ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);  in ath5k_hw_set_mcast_filter()
468 	ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);  in ath5k_hw_set_mcast_filter()
482 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)  in ath5k_hw_get_rx_filter()  argument
486 	filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);  in ath5k_hw_get_rx_filter()
489 	if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_get_rx_filter()
490 		data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);  in ath5k_hw_get_rx_filter()
511 ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)  in ath5k_hw_set_rx_filter()  argument
516 	if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_set_rx_filter()
526 	if (ah->ah_version == AR5K_AR5210 &&  in ath5k_hw_set_rx_filter()
534 		AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);  in ath5k_hw_set_rx_filter()
536 		AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);  in ath5k_hw_set_rx_filter()
539 	ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);  in ath5k_hw_set_rx_filter()
542 	if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_set_rx_filter()
543 		ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);  in ath5k_hw_set_rx_filter()
561 ath5k_hw_get_tsf64(struct ath5k_hw *ah)  in ath5k_hw_get_tsf64()  argument
582 	tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);  in ath5k_hw_get_tsf64()
584 		tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);  in ath5k_hw_get_tsf64()
585 		tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);  in ath5k_hw_get_tsf64()
608 ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)  in ath5k_hw_set_tsf64()  argument
610 	ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);  in ath5k_hw_set_tsf64()
611 	ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);  in ath5k_hw_set_tsf64()
621 ath5k_hw_reset_tsf(struct ath5k_hw *ah)  in ath5k_hw_reset_tsf()  argument
625 	val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;  in ath5k_hw_reset_tsf()
633 	ath5k_hw_reg_write(ah, val, AR5K_BEACON);  in ath5k_hw_reset_tsf()
634 	ath5k_hw_reg_write(ah, val, AR5K_BEACON);  in ath5k_hw_reset_tsf()
647 ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)  in ath5k_hw_init_beacon_timers()  argument
654 	switch (ah->opmode) {  in ath5k_hw_init_beacon_timers()
661 		if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_init_beacon_timers()
669 		AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);  in ath5k_hw_init_beacon_timers()
672 		AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);  in ath5k_hw_init_beacon_timers()
691 	if (ah->opmode == NL80211_IFTYPE_AP ||  in ath5k_hw_init_beacon_timers()
692 	    ah->opmode == NL80211_IFTYPE_MESH_POINT)  in ath5k_hw_init_beacon_timers()
693 		ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);  in ath5k_hw_init_beacon_timers()
695 	ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);  in ath5k_hw_init_beacon_timers()
696 	ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);  in ath5k_hw_init_beacon_timers()
697 	ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);  in ath5k_hw_init_beacon_timers()
698 	ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);  in ath5k_hw_init_beacon_timers()
702 		ath5k_hw_reset_tsf(ah);  in ath5k_hw_init_beacon_timers()
704 	ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |  in ath5k_hw_init_beacon_timers()
713 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_init_beacon_timers()
714 		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);  in ath5k_hw_init_beacon_timers()
716 		ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);  in ath5k_hw_init_beacon_timers()
721 	AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);  in ath5k_hw_init_beacon_timers()
795 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)  in ath5k_hw_check_beacon_timers()  argument
799 	nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);  in ath5k_hw_check_beacon_timers()
800 	atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);  in ath5k_hw_check_beacon_timers()
801 	dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;  in ath5k_hw_check_beacon_timers()
822 ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)  in ath5k_hw_set_coverage_class()  argument
825 	int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;  in ath5k_hw_set_coverage_class()
826 	int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;  in ath5k_hw_set_coverage_class()
829 	ath5k_hw_set_ifs_intervals(ah, slot_time);  in ath5k_hw_set_coverage_class()
830 	ath5k_hw_set_ack_timeout(ah, ack_timeout);  in ath5k_hw_set_coverage_class()
831 	ath5k_hw_set_cts_timeout(ah, cts_timeout);  in ath5k_hw_set_coverage_class()
833 	ah->ah_coverage_class = coverage_class;  in ath5k_hw_set_coverage_class()
850 ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)  in ath5k_hw_start_rx_pcu()  argument
852 	AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);  in ath5k_hw_start_rx_pcu()
862 ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)  in ath5k_hw_stop_rx_pcu()  argument
864 	AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);  in ath5k_hw_stop_rx_pcu()
875 ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)  in ath5k_hw_set_opmode()  argument
877 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_set_opmode()
880 	ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);  in ath5k_hw_set_opmode()
883 	pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;  in ath5k_hw_set_opmode()
886 			| (ah->ah_version == AR5K_AR5210 ?  in ath5k_hw_set_opmode()
895 		if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_set_opmode()
898 			AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);  in ath5k_hw_set_opmode()
905 		if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_set_opmode()
908 			AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);  in ath5k_hw_set_opmode()
913 			| (ah->ah_version == AR5K_AR5210 ?  in ath5k_hw_set_opmode()
918 			| (ah->ah_version == AR5K_AR5210 ?  in ath5k_hw_set_opmode()
931 	ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);  in ath5k_hw_set_opmode()
932 	ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);  in ath5k_hw_set_opmode()
937 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_set_opmode()
938 		ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);  in ath5k_hw_set_opmode()
953 ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode)  in ath5k_hw_pcu_init()  argument
956 	ath5k_hw_set_bssid(ah);  in ath5k_hw_pcu_init()
959 	ath5k_hw_set_opmode(ah, op_mode);  in ath5k_hw_pcu_init()
965 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_pcu_init()
966 		ah->nvifs)  in ath5k_hw_pcu_init()
967 		ath5k_hw_write_rate_duration(ah);  in ath5k_hw_pcu_init()
977 	ath5k_hw_reg_write(ah, (AR5K_TUNE_RSSI_THRES |  in ath5k_hw_pcu_init()
983 	if (ah->ah_mac_srev >= AR5K_SREV_AR2413) {  in ath5k_hw_pcu_init()
984 		ath5k_hw_reg_write(ah, 0x000100aa, AR5K_MIC_QOS_CTL);  in ath5k_hw_pcu_init()
985 		ath5k_hw_reg_write(ah, 0x00003210, AR5K_MIC_QOS_SEL);  in ath5k_hw_pcu_init()
989 	if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_pcu_init()
990 		ath5k_hw_reg_write(ah,  in ath5k_hw_pcu_init()
998 	if (ah->ah_coverage_class > 0)  in ath5k_hw_pcu_init()
999 		ath5k_hw_set_coverage_class(ah, ah->ah_coverage_class);  in ath5k_hw_pcu_init()
1002 	if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_pcu_init()
1004 		if (ah->ah_ack_bitrate_high)  in ath5k_hw_pcu_init()
1005 			AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);  in ath5k_hw_pcu_init()
1007 			AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);  in ath5k_hw_pcu_init()