Lines Matching refs:ah
84 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band) in ath5k_hw_radio_revision() argument
95 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
98 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
107 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34)); in ath5k_hw_radio_revision()
110 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20)); in ath5k_hw_radio_revision()
112 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_radio_revision()
113 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf; in ath5k_hw_radio_revision()
116 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff; in ath5k_hw_radio_revision()
122 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_radio_revision()
136 ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel) in ath5k_channel_ok() argument
142 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) && in ath5k_channel_ok()
143 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max)) in ath5k_channel_ok()
146 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) && in ath5k_channel_ok()
147 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max)) in ath5k_channel_ok()
159 ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, in ath5k_hw_chan_has_spur_noise() argument
164 if ((ah->ah_radio == AR5K_RF5112) || in ath5k_hw_chan_has_spur_noise()
165 (ah->ah_radio == AR5K_RF5413) || in ath5k_hw_chan_has_spur_noise()
166 (ah->ah_radio == AR5K_RF2413) || in ath5k_hw_chan_has_spur_noise()
167 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) in ath5k_hw_chan_has_spur_noise()
193 ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs, in ath5k_hw_rfb_op() argument
205 rfb = ah->ah_rf_banks; in ath5k_hw_rfb_op()
207 for (i = 0; i < ah->ah_rf_regs_count; i++) { in ath5k_hw_rfb_op()
229 offset = ah->ah_offset[bank]; in ath5k_hw_rfb_op()
285 ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah, in ath5k_hw_write_ofdm_timings() argument
292 BUG_ON(!(ah->ah_version == AR5K_AR5212) || in ath5k_hw_write_ofdm_timings()
299 switch (ah->ah_bwmode) { in ath5k_hw_write_ofdm_timings()
337 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
339 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3, in ath5k_hw_write_ofdm_timings()
349 int ath5k_hw_phy_disable(struct ath5k_hw *ah) in ath5k_hw_phy_disable() argument
352 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_disable()
363 ath5k_hw_wait_for_synth(struct ath5k_hw *ah, in ath5k_hw_wait_for_synth() argument
370 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_wait_for_synth()
372 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) & in ath5k_hw_wait_for_synth()
376 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ) in ath5k_hw_wait_for_synth()
378 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ) in ath5k_hw_wait_for_synth()
420 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah) in ath5k_hw_rfgain_opt_init() argument
423 switch (ah->ah_radio) { in ath5k_hw_rfgain_opt_init()
425 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default; in ath5k_hw_rfgain_opt_init()
426 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
427 ah->ah_gain.g_high = 35; in ath5k_hw_rfgain_opt_init()
428 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
431 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default; in ath5k_hw_rfgain_opt_init()
432 ah->ah_gain.g_low = 20; in ath5k_hw_rfgain_opt_init()
433 ah->ah_gain.g_high = 85; in ath5k_hw_rfgain_opt_init()
434 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfgain_opt_init()
457 ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah) in ath5k_hw_request_rfgain_probe() argument
462 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE) in ath5k_hw_request_rfgain_probe()
467 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4, in ath5k_hw_request_rfgain_probe()
471 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED; in ath5k_hw_request_rfgain_probe()
483 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_corr() argument
492 if ((ah->ah_radio != AR5K_RF5112) || in ath5k_hw_rf_gainf_corr()
493 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A)) in ath5k_hw_rf_gainf_corr()
498 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rf_gainf_corr()
500 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_corr()
502 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_gainf_corr()
505 rf = ah->ah_rf_banks; in ath5k_hw_rf_gainf_corr()
506 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
509 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1) in ath5k_hw_rf_gainf_corr()
513 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false); in ath5k_hw_rf_gainf_corr()
520 ah->ah_gain.g_f_corr = step * 2; in ath5k_hw_rf_gainf_corr()
523 ah->ah_gain.g_f_corr = (step - 5) * 2; in ath5k_hw_rf_gainf_corr()
526 ah->ah_gain.g_f_corr = step; in ath5k_hw_rf_gainf_corr()
529 ah->ah_gain.g_f_corr = 0; in ath5k_hw_rf_gainf_corr()
533 return ah->ah_gain.g_f_corr; in ath5k_hw_rf_gainf_corr()
548 ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah) in ath5k_hw_rf_check_gainf_readback() argument
554 if (ah->ah_rf_banks == NULL) in ath5k_hw_rf_check_gainf_readback()
557 rf = ah->ah_rf_banks; in ath5k_hw_rf_check_gainf_readback()
559 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rf_check_gainf_readback()
562 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rf_check_gainf_readback()
564 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP, in ath5k_hw_rf_check_gainf_readback()
572 ah->ah_gain.g_high = level[3] - in ath5k_hw_rf_check_gainf_readback()
574 ah->ah_gain.g_low = level[0] + in ath5k_hw_rf_check_gainf_readback()
579 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rf_check_gainf_readback()
581 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, in ath5k_hw_rf_check_gainf_readback()
590 ah->ah_gain.g_high = 55; in ath5k_hw_rf_check_gainf_readback()
594 return (ah->ah_gain.g_current >= level[0] && in ath5k_hw_rf_check_gainf_readback()
595 ah->ah_gain.g_current <= level[1]) || in ath5k_hw_rf_check_gainf_readback()
596 (ah->ah_gain.g_current >= level[2] && in ath5k_hw_rf_check_gainf_readback()
597 ah->ah_gain.g_current <= level[3]); in ath5k_hw_rf_check_gainf_readback()
608 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah) in ath5k_hw_rf_gainf_adjust() argument
614 switch (ah->ah_radio) { in ath5k_hw_rf_gainf_adjust()
625 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rf_gainf_adjust()
627 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) { in ath5k_hw_rf_gainf_adjust()
630 if (ah->ah_gain.g_step_idx == 0) in ath5k_hw_rf_gainf_adjust()
633 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
634 ah->ah_gain.g_target >= ah->ah_gain.g_high && in ath5k_hw_rf_gainf_adjust()
635 ah->ah_gain.g_step_idx > 0; in ath5k_hw_rf_gainf_adjust()
636 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
637 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
638 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain - in ath5k_hw_rf_gainf_adjust()
645 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) { in ath5k_hw_rf_gainf_adjust()
648 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1)) in ath5k_hw_rf_gainf_adjust()
651 for (ah->ah_gain.g_target = ah->ah_gain.g_current; in ath5k_hw_rf_gainf_adjust()
652 ah->ah_gain.g_target <= ah->ah_gain.g_low && in ath5k_hw_rf_gainf_adjust()
653 ah->ah_gain.g_step_idx < go->go_steps_count - 1; in ath5k_hw_rf_gainf_adjust()
654 g_step = &go->go_step[ah->ah_gain.g_step_idx]) in ath5k_hw_rf_gainf_adjust()
655 ah->ah_gain.g_target -= 2 * in ath5k_hw_rf_gainf_adjust()
656 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain - in ath5k_hw_rf_gainf_adjust()
664 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf_gainf_adjust()
666 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current, in ath5k_hw_rf_gainf_adjust()
667 ah->ah_gain.g_target); in ath5k_hw_rf_gainf_adjust()
683 ath5k_hw_gainf_calibrate(struct ath5k_hw *ah) in ath5k_hw_gainf_calibrate() argument
686 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_gainf_calibrate()
688 if (ah->ah_rf_banks == NULL || in ath5k_hw_gainf_calibrate()
689 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE) in ath5k_hw_gainf_calibrate()
694 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED) in ath5k_hw_gainf_calibrate()
699 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE); in ath5k_hw_gainf_calibrate()
703 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S; in ath5k_hw_gainf_calibrate()
709 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) in ath5k_hw_gainf_calibrate()
710 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
713 ah->ah_gain.g_current += in ath5k_hw_gainf_calibrate()
719 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_gainf_calibrate()
720 ath5k_hw_rf_gainf_corr(ah); in ath5k_hw_gainf_calibrate()
721 ah->ah_gain.g_current = in ath5k_hw_gainf_calibrate()
722 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ? in ath5k_hw_gainf_calibrate()
723 (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) : in ath5k_hw_gainf_calibrate()
730 if (ath5k_hw_rf_check_gainf_readback(ah) && in ath5k_hw_gainf_calibrate()
731 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) && in ath5k_hw_gainf_calibrate()
732 ath5k_hw_rf_gainf_adjust(ah)) { in ath5k_hw_gainf_calibrate()
733 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE; in ath5k_hw_gainf_calibrate()
735 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_gainf_calibrate()
740 return ah->ah_gain.g_state; in ath5k_hw_gainf_calibrate()
754 ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band) in ath5k_hw_rfgain_init() argument
759 switch (ah->ah_radio) { in ath5k_hw_rfgain_init()
793 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index], in ath5k_hw_rfgain_init()
815 ath5k_hw_rfregs_init(struct ath5k_hw *ah, in ath5k_hw_rfregs_init() argument
823 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_rfregs_init()
828 switch (ah->ah_radio) { in ath5k_hw_rfregs_init()
831 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111); in ath5k_hw_rfregs_init()
833 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111); in ath5k_hw_rfregs_init()
837 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
839 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a); in ath5k_hw_rfregs_init()
841 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a); in ath5k_hw_rfregs_init()
844 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112); in ath5k_hw_rfregs_init()
846 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112); in ath5k_hw_rfregs_init()
852 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413); in ath5k_hw_rfregs_init()
854 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413); in ath5k_hw_rfregs_init()
858 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316); in ath5k_hw_rfregs_init()
860 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316); in ath5k_hw_rfregs_init()
864 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413); in ath5k_hw_rfregs_init()
866 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413); in ath5k_hw_rfregs_init()
870 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
872 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317); in ath5k_hw_rfregs_init()
876 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425); in ath5k_hw_rfregs_init()
877 if (ah->ah_mac_srev < AR5K_SREV_AR2417) { in ath5k_hw_rfregs_init()
879 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425); in ath5k_hw_rfregs_init()
882 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417); in ath5k_hw_rfregs_init()
892 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
893 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size, in ath5k_hw_rfregs_init()
895 if (ah->ah_rf_banks == NULL) { in ath5k_hw_rfregs_init()
896 ATH5K_ERR(ah, "out of memory\n"); in ath5k_hw_rfregs_init()
902 rfb = ah->ah_rf_banks; in ath5k_hw_rfregs_init()
904 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
906 ATH5K_ERR(ah, "invalid bank\n"); in ath5k_hw_rfregs_init()
913 ah->ah_offset[bank] = i; in ath5k_hw_rfregs_init()
934 if ((ah->ah_radio == AR5K_RF5111) || in ath5k_hw_rfregs_init()
935 (ah->ah_radio == AR5K_RF5112)) in ath5k_hw_rfregs_init()
940 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
943 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
948 (ah->ah_radio == AR5K_RF5111)) { in ath5k_hw_rfregs_init()
961 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb], in ath5k_hw_rfregs_init()
964 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb], in ath5k_hw_rfregs_init()
968 g_step = &go->go_step[ah->ah_gain.g_step_idx]; in ath5k_hw_rfregs_init()
971 if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) && in ath5k_hw_rfregs_init()
972 (ah->ah_radio != AR5K_RF5413)) in ath5k_hw_rfregs_init()
973 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false); in ath5k_hw_rfregs_init()
976 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_rfregs_init()
981 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL, in ath5k_hw_rfregs_init()
985 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
988 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
991 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
996 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
1002 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1005 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode], in ath5k_hw_rfregs_init()
1008 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1011 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1015 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1016 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1019 ath5k_hw_rfb_op(ah, rf_regs, 0x1f, in ath5k_hw_rfregs_init()
1022 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1025 ath5k_hw_rfb_op(ah, rf_regs, wait_i, in ath5k_hw_rfregs_init()
1027 ath5k_hw_rfb_op(ah, rf_regs, 3, in ath5k_hw_rfregs_init()
1033 if (ah->ah_radio == AR5K_RF5112) { in ath5k_hw_rfregs_init()
1038 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0], in ath5k_hw_rfregs_init()
1041 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1], in ath5k_hw_rfregs_init()
1044 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2], in ath5k_hw_rfregs_init()
1047 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3], in ath5k_hw_rfregs_init()
1050 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4], in ath5k_hw_rfregs_init()
1053 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5], in ath5k_hw_rfregs_init()
1056 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6], in ath5k_hw_rfregs_init()
1061 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE; in ath5k_hw_rfregs_init()
1066 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode], in ath5k_hw_rfregs_init()
1069 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) { in ath5k_hw_rfregs_init()
1071 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1078 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1081 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1085 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1088 ath5k_hw_rfb_op(ah, rf_regs, in ath5k_hw_rfregs_init()
1094 if (ah->ah_radio == AR5K_RF5112 && in ath5k_hw_rfregs_init()
1095 (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) { in ath5k_hw_rfregs_init()
1096 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1099 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1102 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1105 ath5k_hw_rfb_op(ah, rf_regs, 2, in ath5k_hw_rfregs_init()
1110 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) { in ath5k_hw_rfregs_init()
1111 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1114 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1117 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1120 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1123 ath5k_hw_rfb_op(ah, rf_regs, 1, in ath5k_hw_rfregs_init()
1128 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode], in ath5k_hw_rfregs_init()
1132 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ || in ath5k_hw_rfregs_init()
1133 ah->ah_bwmode == AR5K_BWMODE_10MHZ) { in ath5k_hw_rfregs_init()
1136 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ? in ath5k_hw_rfregs_init()
1139 ath5k_hw_rfb_op(ah, rf_regs, pd_delay, in ath5k_hw_rfregs_init()
1141 ath5k_hw_rfb_op(ah, rf_regs, 0xf, in ath5k_hw_rfregs_init()
1147 if (ah->ah_radio == AR5K_RF5413 && in ath5k_hw_rfregs_init()
1150 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE, in ath5k_hw_rfregs_init()
1154 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 && in ath5k_hw_rfregs_init()
1155 ah->ah_mac_srev < AR5K_SREV_AR5413) in ath5k_hw_rfregs_init()
1156 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3), in ath5k_hw_rfregs_init()
1162 for (i = 0; i < ah->ah_rf_banks_size; i++) { in ath5k_hw_rfregs_init()
1164 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register); in ath5k_hw_rfregs_init()
1200 ath5k_hw_rf5110_channel(struct ath5k_hw *ah, in ath5k_hw_rf5110_channel() argument
1209 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER); in ath5k_hw_rf5110_channel()
1210 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0); in ath5k_hw_rf5110_channel()
1259 ath5k_hw_rf5111_channel(struct ath5k_hw *ah, in ath5k_hw_rf5111_channel() argument
1296 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8), in ath5k_hw_rf5111_channel()
1298 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00), in ath5k_hw_rf5111_channel()
1317 ath5k_hw_rf5112_channel(struct ath5k_hw *ah, in ath5k_hw_rf5112_channel() argument
1376 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf5112_channel()
1377 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf5112_channel()
1391 ath5k_hw_rf2425_channel(struct ath5k_hw *ah, in ath5k_hw_rf2425_channel() argument
1421 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER); in ath5k_hw_rf2425_channel()
1422 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5); in ath5k_hw_rf2425_channel()
1436 ath5k_hw_channel(struct ath5k_hw *ah, in ath5k_hw_channel() argument
1444 if (!ath5k_channel_ok(ah, channel)) { in ath5k_hw_channel()
1445 ATH5K_ERR(ah, in ath5k_hw_channel()
1455 switch (ah->ah_radio) { in ath5k_hw_channel()
1457 ret = ath5k_hw_rf5110_channel(ah, channel); in ath5k_hw_channel()
1460 ret = ath5k_hw_rf5111_channel(ah, channel); in ath5k_hw_channel()
1464 ret = ath5k_hw_rf2425_channel(ah, channel); in ath5k_hw_channel()
1467 ret = ath5k_hw_rf5112_channel(ah, channel); in ath5k_hw_channel()
1476 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1479 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL, in ath5k_hw_channel()
1483 ah->ah_current_channel = channel; in ath5k_hw_channel()
1527 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah) in ath5k_hw_read_measured_noise_floor() argument
1531 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF); in ath5k_hw_read_measured_noise_floor()
1540 ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah) in ath5k_hw_init_nfcal_hist() argument
1544 ah->ah_nfcal_hist.index = 0; in ath5k_hw_init_nfcal_hist()
1546 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE; in ath5k_hw_init_nfcal_hist()
1554 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor) in ath5k_hw_update_nfcal_hist() argument
1556 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist; in ath5k_hw_update_nfcal_hist()
1566 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah) in ath5k_hw_get_median_noise_floor() argument
1572 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort)); in ath5k_hw_get_median_noise_floor()
1583 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_get_median_noise_floor()
1598 ath5k_hw_update_noise_floor(struct ath5k_hw *ah) in ath5k_hw_update_noise_floor() argument
1600 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_update_noise_floor()
1606 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) { in ath5k_hw_update_noise_floor()
1607 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1613 ah->ah_cal_mask |= AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1615 ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel); in ath5k_hw_update_noise_floor()
1618 nf = ath5k_hw_read_measured_noise_floor(ah); in ath5k_hw_update_noise_floor()
1622 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1630 ath5k_hw_update_nfcal_hist(ah, nf); in ath5k_hw_update_noise_floor()
1631 nf = ath5k_hw_get_median_noise_floor(ah); in ath5k_hw_update_noise_floor()
1634 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M; in ath5k_hw_update_noise_floor()
1636 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1638 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1641 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF, in ath5k_hw_update_noise_floor()
1651 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF); in ath5k_hw_update_noise_floor()
1652 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_update_noise_floor()
1657 ah->ah_noise_floor = nf; in ath5k_hw_update_noise_floor()
1659 ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF; in ath5k_hw_update_noise_floor()
1661 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_update_noise_floor()
1673 ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah, in ath5k_hw_rf5110_calibrate() argument
1679 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) in ath5k_hw_rf5110_calibrate()
1685 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1687 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1688 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1695 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1697 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_rf5110_calibrate()
1702 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_rf5110_calibrate()
1705 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1715 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1716 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1717 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1720 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) | in ath5k_hw_rf5110_calibrate()
1723 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI | in ath5k_hw_rf5110_calibrate()
1728 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT | in ath5k_hw_rf5110_calibrate()
1735 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1737 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG); in ath5k_hw_rf5110_calibrate()
1738 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE); in ath5k_hw_rf5110_calibrate()
1745 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL); in ath5k_hw_rf5110_calibrate()
1747 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_rf5110_calibrate()
1751 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG); in ath5k_hw_rf5110_calibrate()
1752 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE); in ath5k_hw_rf5110_calibrate()
1753 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT); in ath5k_hw_rf5110_calibrate()
1756 ATH5K_ERR(ah, "calibration timeout (%uMHz)\n", in ath5k_hw_rf5110_calibrate()
1764 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210, in ath5k_hw_rf5110_calibrate()
1766 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210); in ath5k_hw_rf5110_calibrate()
1776 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah) in ath5k_hw_rf511x_iq_calibrate() argument
1783 if (!ah->ah_iq_cal_needed) in ath5k_hw_rf511x_iq_calibrate()
1785 else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) { in ath5k_hw_rf511x_iq_calibrate()
1786 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1796 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR); in ath5k_hw_rf511x_iq_calibrate()
1797 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I); in ath5k_hw_rf511x_iq_calibrate()
1798 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q); in ath5k_hw_rf511x_iq_calibrate()
1799 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1807 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1823 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_rf511x_iq_calibrate()
1829 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_rf511x_iq_calibrate()
1834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff); in ath5k_hw_rf511x_iq_calibrate()
1835 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff); in ath5k_hw_rf511x_iq_calibrate()
1836 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE); in ath5k_hw_rf511x_iq_calibrate()
1840 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_rf511x_iq_calibrate()
1842 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN); in ath5k_hw_rf511x_iq_calibrate()
1857 ath5k_hw_phy_calibrate(struct ath5k_hw *ah, in ath5k_hw_phy_calibrate() argument
1862 if (ah->ah_radio == AR5K_RF5110) in ath5k_hw_phy_calibrate()
1863 return ath5k_hw_rf5110_calibrate(ah, channel); in ath5k_hw_phy_calibrate()
1865 ret = ath5k_hw_rf511x_iq_calibrate(ah); in ath5k_hw_phy_calibrate()
1867 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE, in ath5k_hw_phy_calibrate()
1878 if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && in ath5k_hw_phy_calibrate()
1879 (ah->ah_radio == AR5K_RF5111 || in ath5k_hw_phy_calibrate()
1880 ah->ah_radio == AR5K_RF5112) && in ath5k_hw_phy_calibrate()
1882 ath5k_hw_request_rfgain_probe(ah); in ath5k_hw_phy_calibrate()
1885 if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF)) in ath5k_hw_phy_calibrate()
1886 ath5k_hw_update_noise_floor(ah); in ath5k_hw_phy_calibrate()
1907 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah, in ath5k_hw_set_spur_mitigation_filter() argument
1910 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_set_spur_mitigation_filter()
1935 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_hw_set_spur_mitigation_filter()
1966 switch (ah->ah_bwmode) { in ath5k_hw_set_spur_mitigation_filter()
2060 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2063 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2069 ath5k_hw_reg_write(ah, in ath5k_hw_set_spur_mitigation_filter()
2078 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2079 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2083 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2084 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2089 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2090 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2091 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2092 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2096 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2097 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2098 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2099 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2103 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & in ath5k_hw_set_spur_mitigation_filter()
2106 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2108 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_set_spur_mitigation_filter()
2112 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11); in ath5k_hw_set_spur_mitigation_filter()
2115 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7); in ath5k_hw_set_spur_mitigation_filter()
2116 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8, in ath5k_hw_set_spur_mitigation_filter()
2120 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9); in ath5k_hw_set_spur_mitigation_filter()
2121 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10, in ath5k_hw_set_spur_mitigation_filter()
2126 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1); in ath5k_hw_set_spur_mitigation_filter()
2127 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2); in ath5k_hw_set_spur_mitigation_filter()
2128 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3); in ath5k_hw_set_spur_mitigation_filter()
2129 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL, in ath5k_hw_set_spur_mitigation_filter()
2133 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1); in ath5k_hw_set_spur_mitigation_filter()
2134 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2); in ath5k_hw_set_spur_mitigation_filter()
2135 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3); in ath5k_hw_set_spur_mitigation_filter()
2136 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4, in ath5k_hw_set_spur_mitigation_filter()
2203 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant) in ath5k_hw_set_def_antenna() argument
2205 if (ah->ah_version != AR5K_AR5210) in ath5k_hw_set_def_antenna()
2206 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA); in ath5k_hw_set_def_antenna()
2216 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable) in ath5k_hw_set_fast_div() argument
2224 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2227 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2231 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_set_fast_div()
2239 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2242 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2245 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART, in ath5k_hw_set_fast_div()
2248 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV, in ath5k_hw_set_fast_div()
2262 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode) in ath5k_hw_set_antenna_switch() argument
2270 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A) in ath5k_hw_set_antenna_switch()
2272 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B) in ath5k_hw_set_antenna_switch()
2280 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL, in ath5k_hw_set_antenna_switch()
2282 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] | in ath5k_hw_set_antenna_switch()
2286 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0], in ath5k_hw_set_antenna_switch()
2288 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1], in ath5k_hw_set_antenna_switch()
2298 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode) in ath5k_hw_set_antenna_mode() argument
2300 struct ieee80211_channel *channel = ah->ah_current_channel; in ath5k_hw_set_antenna_mode()
2310 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2314 def_ant = ah->ah_def_ant; in ath5k_hw_set_antenna_mode()
2316 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_set_antenna_mode()
2383 ah->ah_tx_ant = tx_ant; in ath5k_hw_set_antenna_mode()
2384 ah->ah_ant_mode = ant_mode; in ath5k_hw_set_antenna_mode()
2385 ah->ah_def_ant = def_ant; in ath5k_hw_set_antenna_mode()
2392 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS); in ath5k_hw_set_antenna_mode()
2395 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1); in ath5k_hw_set_antenna_mode()
2397 ath5k_hw_set_antenna_switch(ah, ee_mode); in ath5k_hw_set_antenna_mode()
2400 ath5k_hw_set_fast_div(ah, ee_mode, fast_div); in ath5k_hw_set_antenna_mode()
2401 ath5k_hw_set_def_antenna(ah, def_ant); in ath5k_hw_set_antenna_mode()
2584 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah, in ath5k_get_chan_pcal_surrounding_piers() argument
2589 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_chan_pcal_surrounding_piers()
2673 ath5k_get_rate_pcal_data(struct ath5k_hw *ah, in ath5k_get_rate_pcal_data() argument
2677 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_rate_pcal_data()
2768 ath5k_get_max_ctl_power(struct ath5k_hw *ah, in ath5k_get_max_ctl_power() argument
2771 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); in ath5k_get_max_ctl_power()
2772 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_get_max_ctl_power()
2775 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4; in ath5k_get_max_ctl_power()
2786 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2792 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) in ath5k_get_max_ctl_power()
2834 ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr); in ath5k_get_max_ctl_power()
2881 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min, in ath5k_fill_pwr_to_pcdac_table() argument
2884 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_fill_pwr_to_pcdac_table()
2885 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0]; in ath5k_fill_pwr_to_pcdac_table()
2931 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min, in ath5k_combine_linear_pcdac_curves() argument
2934 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_linear_pcdac_curves()
2956 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; in ath5k_combine_linear_pcdac_curves()
2957 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2975 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */ in ath5k_combine_linear_pcdac_curves()
2976 pcdac_high_pwr = ah->ah_txpower.tmpL[0]; in ath5k_combine_linear_pcdac_curves()
2984 ah->ah_txpower.txp_min_idx = min_pwr_idx / 2; in ath5k_combine_linear_pcdac_curves()
3029 ath5k_write_pcdac_table(struct ath5k_hw *ah) in ath5k_write_pcdac_table() argument
3031 u8 *pcdac_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pcdac_table()
3038 ath5k_hw_reg_write(ah, in ath5k_write_pcdac_table()
3081 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah, in ath5k_combine_pwr_to_pdadc_curves() argument
3085 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_combine_pwr_to_pdadc_curves()
3094 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) & in ath5k_combine_pwr_to_pdadc_curves()
3099 pdadc_tmp = ah->ah_txpower.tmpL[pdg]; in ath5k_combine_pwr_to_pdadc_curves()
3181 ath5k_hw_reg_write(ah, in ath5k_combine_pwr_to_pdadc_curves()
3195 ah->ah_txpower.txp_min_idx = pwr_min[0]; in ath5k_combine_pwr_to_pdadc_curves()
3205 ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode) in ath5k_write_pwr_to_pdadc_table() argument
3207 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_write_pwr_to_pdadc_table()
3208 u8 *pdadc_out = ah->ah_txpower.txp_pd_table; in ath5k_write_pwr_to_pdadc_table()
3217 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3244 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1); in ath5k_write_pwr_to_pdadc_table()
3251 ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i)); in ath5k_write_pwr_to_pdadc_table()
3274 ath5k_setup_channel_powertable(struct ath5k_hw *ah, in ath5k_setup_channel_powertable() argument
3281 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_setup_channel_powertable()
3291 ath5k_get_chan_pcal_surrounding_piers(ah, channel, in ath5k_setup_channel_powertable()
3310 tmpL = ah->ah_txpower.tmpL[pdg]; in ath5k_setup_channel_powertable()
3311 tmpR = ah->ah_txpower.tmpR[pdg]; in ath5k_setup_channel_powertable()
3412 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3417 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target, in ath5k_setup_channel_powertable()
3428 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3434 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2); in ath5k_setup_channel_powertable()
3439 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max); in ath5k_setup_channel_powertable()
3442 ah->ah_txpower.txp_min_idx = 0; in ath5k_setup_channel_powertable()
3443 ah->ah_txpower.txp_offset = 0; in ath5k_setup_channel_powertable()
3448 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max, in ath5k_setup_channel_powertable()
3453 ah->ah_txpower.txp_offset = table_min[0]; in ath5k_setup_channel_powertable()
3459 ah->ah_txpower.txp_setup = true; in ath5k_setup_channel_powertable()
3471 ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type) in ath5k_write_channel_powertable() argument
3474 ath5k_write_pwr_to_pdadc_table(ah, ee_mode); in ath5k_write_channel_powertable()
3476 ath5k_write_pcdac_table(ah); in ath5k_write_channel_powertable()
3510 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr, in ath5k_setup_rate_powertable() argument
3521 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2; in ath5k_setup_rate_powertable()
3524 rates = ah->ah_txpower.txp_rates_power_table; in ath5k_setup_rate_powertable()
3559 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A)) in ath5k_setup_rate_powertable()
3561 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta; in ath5k_setup_rate_powertable()
3569 ah->ah_txpower.txp_min_pwr = 2 * rates[7]; in ath5k_setup_rate_powertable()
3570 ah->ah_txpower.txp_cur_pwr = 2 * rates[0]; in ath5k_setup_rate_powertable()
3575 ah->ah_txpower.txp_ofdm = rates[7]; in ath5k_setup_rate_powertable()
3581 rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset; in ath5k_setup_rate_powertable()
3602 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_txpower() argument
3606 struct ieee80211_channel *curr_channel = ah->ah_current_channel; in ath5k_hw_txpower()
3612 ATH5K_ERR(ah, "invalid tx power: %u\n", txpower); in ath5k_hw_txpower()
3616 ee_mode = ath5k_eeprom_mode_from_channel(ah, channel); in ath5k_hw_txpower()
3619 switch (ah->ah_radio) { in ath5k_hw_txpower()
3644 if (!ah->ah_txpower.txp_setup || in ath5k_hw_txpower()
3649 int requested_txpower = ah->ah_txpower.txp_requested; in ath5k_hw_txpower()
3651 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower)); in ath5k_hw_txpower()
3654 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; in ath5k_hw_txpower()
3656 ah->ah_txpower.txp_requested = requested_txpower; in ath5k_hw_txpower()
3659 ret = ath5k_setup_channel_powertable(ah, channel, in ath5k_hw_txpower()
3666 ath5k_write_channel_powertable(ah, ee_mode, type); in ath5k_hw_txpower()
3669 ath5k_get_max_ctl_power(ah, channel); in ath5k_hw_txpower()
3679 ath5k_get_rate_pcal_data(ah, channel, &rate_info); in ath5k_hw_txpower()
3682 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode); in ath5k_hw_txpower()
3685 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) | in ath5k_hw_txpower()
3689 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) | in ath5k_hw_txpower()
3693 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) | in ath5k_hw_txpower()
3697 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) | in ath5k_hw_txpower()
3702 if (ah->ah_txpower.txp_tpc) { in ath5k_hw_txpower()
3703 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE | in ath5k_hw_txpower()
3706 ath5k_hw_reg_write(ah, in ath5k_hw_txpower()
3712 ath5k_hw_reg_write(ah, AR5K_TUNE_MAX_TXPOWER, in ath5k_hw_txpower()
3728 ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower) in ath5k_hw_set_txpower_limit() argument
3730 ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER, in ath5k_hw_set_txpower_limit()
3733 return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower); in ath5k_hw_set_txpower_limit()
3755 ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, in ath5k_hw_phy_init() argument
3769 curr_channel = ah->ah_current_channel; in ath5k_hw_phy_init()
3778 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3781 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT)) in ath5k_hw_phy_init()
3790 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3794 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3804 ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ? in ath5k_hw_phy_init()
3805 ah->ah_txpower.txp_requested * 2 : in ath5k_hw_phy_init()
3811 if (ah->ah_version == AR5K_AR5212 && in ath5k_hw_phy_init()
3814 ret = ath5k_hw_write_ofdm_timings(ah, channel); in ath5k_hw_phy_init()
3821 if (ah->ah_mac_srev >= AR5K_SREV_AR5424) in ath5k_hw_phy_init()
3822 ath5k_hw_set_spur_mitigation_filter(ah, in ath5k_hw_phy_init()
3838 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ, in ath5k_hw_phy_init()
3844 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3856 if (ah->ah_version != AR5K_AR5210) { in ath5k_hw_phy_init()
3862 ret = ath5k_hw_rfgain_init(ah, channel->band); in ath5k_hw_phy_init()
3871 ret = ath5k_hw_rfregs_init(ah, channel, mode); in ath5k_hw_phy_init()
3877 if (ah->ah_radio == AR5K_RF5111) { in ath5k_hw_phy_init()
3879 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3882 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG, in ath5k_hw_phy_init()
3886 } else if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_phy_init()
3889 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3894 ret = ath5k_hw_channel(ah, channel); in ath5k_hw_phy_init()
3903 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT); in ath5k_hw_phy_init()
3905 ath5k_hw_wait_for_synth(ah, channel); in ath5k_hw_phy_init()
3911 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3912 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3914 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10)) in ath5k_hw_phy_init()
3918 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1); in ath5k_hw_phy_init()
3939 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3944 ah->ah_iq_cal_needed = false; in ath5k_hw_phy_init()
3946 ah->ah_iq_cal_needed = true; in ath5k_hw_phy_init()
3947 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3949 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, in ath5k_hw_phy_init()
3955 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, in ath5k_hw_phy_init()
3957 ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n", in ath5k_hw_phy_init()
3962 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode); in ath5k_hw_phy_init()