63 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_num_tx_pending()  argument
66 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_num_tx_pending()
69 	if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)  in ath5k_hw_num_tx_pending()
73 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_num_tx_pending()
76 	pending = ath5k_hw_reg_read(ah, AR5K_QUEUE_STATUS(queue));  in ath5k_hw_num_tx_pending()
82 	if (!pending && AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))  in ath5k_hw_num_tx_pending()
94 ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_release_tx_queue()  argument
96 	if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))  in ath5k_hw_release_tx_queue()
100 	ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;  in ath5k_hw_release_tx_queue()
102 	AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);  in ath5k_hw_release_tx_queue()
138 ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,  in ath5k_hw_get_tx_queueprops()  argument
141 	memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));  in ath5k_hw_get_tx_queueprops()
154 ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,  in ath5k_hw_set_tx_queueprops()  argument
159 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_set_tx_queueprops()
161 	qi = &ah->ah_txq[queue];  in ath5k_hw_set_tx_queueprops()
203 ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,  in ath5k_hw_setup_tx_queue()  argument
213 	if (ah->ah_capabilities.cap_queues.q_tx_num == 2) {  in ath5k_hw_setup_tx_queue()
247 	memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));  in ath5k_hw_setup_tx_queue()
248 	ah->ah_txq[queue].tqi_type = queue_type;  in ath5k_hw_setup_tx_queue()
252 		ret = ath5k_hw_set_tx_queueprops(ah, queue, queue_info);  in ath5k_hw_setup_tx_queue()
262 	AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);  in ath5k_hw_setup_tx_queue()
281 ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,  in ath5k_hw_set_tx_retry_limits()  argument
285 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_set_tx_retry_limits()
286 		struct ath5k_txq_info *tq = &ah->ah_txq[queue];  in ath5k_hw_set_tx_retry_limits()
291 		ath5k_hw_reg_write(ah,  in ath5k_hw_set_tx_retry_limits()
293 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
295 			| AR5K_REG_SM(ah->ah_retry_short,  in ath5k_hw_set_tx_retry_limits()
297 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
299 			| AR5K_REG_SM(ah->ah_retry_short,  in ath5k_hw_set_tx_retry_limits()
304 		ath5k_hw_reg_write(ah,  in ath5k_hw_set_tx_retry_limits()
305 			AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
307 			| AR5K_REG_SM(ah->ah_retry_long,  in ath5k_hw_set_tx_retry_limits()
309 			| AR5K_REG_SM(max(ah->ah_retry_long, ah->ah_retry_short),  in ath5k_hw_set_tx_retry_limits()
324 ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)  in ath5k_hw_reset_tx_queue()  argument
326 	struct ath5k_txq_info *tq = &ah->ah_txq[queue];  in ath5k_hw_reset_tx_queue()
328 	AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);  in ath5k_hw_reset_tx_queue()
330 	tq = &ah->ah_txq[queue];  in ath5k_hw_reset_tx_queue()
334 	if ((ah->ah_version == AR5K_AR5210) ||  in ath5k_hw_reset_tx_queue()
342 	ath5k_hw_reg_write(ah,  in ath5k_hw_reset_tx_queue()
351 	ath5k_hw_set_tx_retry_limits(ah, queue);  in ath5k_hw_reset_tx_queue()
359 	AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),  in ath5k_hw_reset_tx_queue()
363 	if (ah->ah_mac_version < AR5K_SREV_AR5211)  in ath5k_hw_reset_tx_queue()
364 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),  in ath5k_hw_reset_tx_queue()
369 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,  in ath5k_hw_reset_tx_queue()
375 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
379 			AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
385 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,  in ath5k_hw_reset_tx_queue()
391 		ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,  in ath5k_hw_reset_tx_queue()
397 			AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
403 		ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,  in ath5k_hw_reset_tx_queue()
408 		ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,  in ath5k_hw_reset_tx_queue()
416 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
421 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),  in ath5k_hw_reset_tx_queue()
431 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
436 		ath5k_hw_reg_write(ah, ((tq->tqi_ready_time -  in ath5k_hw_reset_tx_queue()
443 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),  in ath5k_hw_reset_tx_queue()
449 		AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),  in ath5k_hw_reset_tx_queue()
465 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);  in ath5k_hw_reset_tx_queue()
468 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);  in ath5k_hw_reset_tx_queue()
471 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);  in ath5k_hw_reset_tx_queue()
474 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);  in ath5k_hw_reset_tx_queue()
477 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);  in ath5k_hw_reset_tx_queue()
480 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrorn, queue);  in ath5k_hw_reset_tx_queue()
483 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_cbrurn, queue);  in ath5k_hw_reset_tx_queue()
486 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_qtrig, queue);  in ath5k_hw_reset_tx_queue()
489 		AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_nofrm, queue);  in ath5k_hw_reset_tx_queue()
494 	ah->ah_txq_imr_txok &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
495 	ah->ah_txq_imr_txerr &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
496 	ah->ah_txq_imr_txurn &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
497 	ah->ah_txq_imr_txdesc &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
498 	ah->ah_txq_imr_txeol &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
499 	ah->ah_txq_imr_cbrorn &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
500 	ah->ah_txq_imr_cbrurn &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
501 	ah->ah_txq_imr_qtrig &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
502 	ah->ah_txq_imr_nofrm &= ah->ah_txq_status;  in ath5k_hw_reset_tx_queue()
504 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,  in ath5k_hw_reset_tx_queue()
506 					AR5K_REG_SM(ah->ah_txq_imr_txdesc,  in ath5k_hw_reset_tx_queue()
510 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,  in ath5k_hw_reset_tx_queue()
512 					AR5K_REG_SM(ah->ah_txq_imr_txeol,  in ath5k_hw_reset_tx_queue()
517 	AR5K_REG_DISABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_QCU_TXURN);  in ath5k_hw_reset_tx_queue()
518 	AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2,  in ath5k_hw_reset_tx_queue()
519 				AR5K_REG_SM(ah->ah_txq_imr_txurn,  in ath5k_hw_reset_tx_queue()
522 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_cbrorn,  in ath5k_hw_reset_tx_queue()
524 				AR5K_REG_SM(ah->ah_txq_imr_cbrurn,  in ath5k_hw_reset_tx_queue()
528 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_qtrig,  in ath5k_hw_reset_tx_queue()
532 	ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_nofrm,  in ath5k_hw_reset_tx_queue()
537 	if (ah->ah_txq_imr_nofrm == 0)  in ath5k_hw_reset_tx_queue()
538 		ath5k_hw_reg_write(ah, 0, AR5K_TXNOFRM);  in ath5k_hw_reset_tx_queue()
541 	AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(queue), queue);  in ath5k_hw_reset_tx_queue()
559 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time)  in ath5k_hw_set_ifs_intervals()  argument
561 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_set_ifs_intervals()
566 	u32 slot_time_clock = ath5k_hw_htoclock(ah, slot_time);  in ath5k_hw_set_ifs_intervals()
572 	sifs = ath5k_hw_get_default_sifs(ah);  in ath5k_hw_set_ifs_intervals()
573 	sifs_clock = ath5k_hw_htoclock(ah, sifs - 2);  in ath5k_hw_set_ifs_intervals()
604 	switch (ah->ah_bwmode) {  in ath5k_hw_set_ifs_intervals()
615 	sband = &ah->sbands[band];  in ath5k_hw_set_ifs_intervals()
626 	ack_tx_time = ath5k_hw_get_frame_duration(ah, band, 10, rate, false);  in ath5k_hw_set_ifs_intervals()
630 	eifs_clock = ath5k_hw_htoclock(ah, eifs);  in ath5k_hw_set_ifs_intervals()
633 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_set_ifs_intervals()
637 		ath5k_hw_reg_write(ah, slot_time_clock, AR5K_SLOT_TIME);  in ath5k_hw_set_ifs_intervals()
644 		pifs_clock = ath5k_hw_htoclock(ah, pifs);  in ath5k_hw_set_ifs_intervals()
649 		difs_clock = ath5k_hw_htoclock(ah, difs);  in ath5k_hw_set_ifs_intervals()
652 		ath5k_hw_reg_write(ah, (difs_clock <<  in ath5k_hw_set_ifs_intervals()
657 		ath5k_hw_reg_write(ah, pifs_clock | eifs_clock |  in ath5k_hw_set_ifs_intervals()
665 	ath5k_hw_reg_write(ah, slot_time_clock, AR5K_DCU_GBL_IFS_SLOT);  in ath5k_hw_set_ifs_intervals()
668 	ath5k_hw_reg_write(ah, eifs_clock, AR5K_DCU_GBL_IFS_EIFS);  in ath5k_hw_set_ifs_intervals()
671 	AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,  in ath5k_hw_set_ifs_intervals()
676 	ath5k_hw_reg_write(ah, sifs_clock, AR5K_DCU_GBL_IFS_SIFS);  in ath5k_hw_set_ifs_intervals()
690 ath5k_hw_init_queues(struct ath5k_hw *ah)  in ath5k_hw_init_queues()  argument
702 	if (ah->ah_version != AR5K_AR5210)  in ath5k_hw_init_queues()
703 		for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {  in ath5k_hw_init_queues()
704 			ret = ath5k_hw_reset_tx_queue(ah, i);  in ath5k_hw_init_queues()
706 				ATH5K_ERR(ah,  in ath5k_hw_init_queues()
715 		ath5k_hw_set_tx_retry_limits(ah, 0);  in ath5k_hw_init_queues()
718 	if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_hw_init_queues()
719 		AR5K_REG_ENABLE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,  in ath5k_hw_init_queues()
725 	if (!ah->ah_coverage_class) {  in ath5k_hw_init_queues()
726 		unsigned int slot_time = ath5k_hw_get_default_slottime(ah);  in ath5k_hw_init_queues()
727 		ath5k_hw_set_ifs_intervals(ah, slot_time);  in ath5k_hw_init_queues()