67 ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,  in ath5k_hw_register_timeout()  argument
74 		data = ath5k_hw_reg_read(ah, reg);  in ath5k_hw_register_timeout()
101 ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)  in ath5k_hw_htoclock()  argument
103 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_htoclock()
118 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)  in ath5k_hw_clocktoh()  argument
120 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_clocktoh()
132 ath5k_hw_init_core_clock(struct ath5k_hw *ah)  in ath5k_hw_init_core_clock()  argument
134 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_init_core_clock()
135 	struct ath_common *common = ath5k_hw_common(ah);  in ath5k_hw_init_core_clock()
156 	switch (ah->ah_bwmode) {  in ath5k_hw_init_core_clock()
180 	if (ah->ah_version != AR5K_AR5210)  in ath5k_hw_init_core_clock()
181 		AR5K_REG_WRITE_BITS(ah, AR5K_DCU_GBL_IFS_MISC,  in ath5k_hw_init_core_clock()
186 	if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_init_core_clock()
187 	    (ah->ah_radio == AR5K_RF2413) ||  in ath5k_hw_init_core_clock()
188 	    (ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_init_core_clock()
189 	    (ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_init_core_clock()
190 	    (ah->ah_radio == AR5K_RF2317))  in ath5k_hw_init_core_clock()
200 	usec_reg = ath5k_hw_reg_read(ah, AR5K_USEC_5211);  in ath5k_hw_init_core_clock()
214 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_init_core_clock()
220 	if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_init_core_clock()
231 	switch (ah->ah_bwmode) {  in ath5k_hw_init_core_clock()
257 	ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC);  in ath5k_hw_init_core_clock()
260 	if (ah->ah_radio == AR5K_RF5112) {  in ath5k_hw_init_core_clock()
261 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL2,  in ath5k_hw_init_core_clock()
281 ath5k_hw_set_sleep_clock(struct ath5k_hw *ah, bool enable)  in ath5k_hw_set_sleep_clock()  argument
283 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_set_sleep_clock()
293 		AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, 1);  in ath5k_hw_set_sleep_clock()
295 		AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 61);  in ath5k_hw_set_sleep_clock()
299 		ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);  in ath5k_hw_set_sleep_clock()
301 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
302 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
303 		(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
304 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))  in ath5k_hw_set_sleep_clock()
308 		ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);  in ath5k_hw_set_sleep_clock()
310 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
311 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
312 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {  in ath5k_hw_set_sleep_clock()
313 			ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT);  in ath5k_hw_set_sleep_clock()
314 			ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL);  in ath5k_hw_set_sleep_clock()
315 			ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK);  in ath5k_hw_set_sleep_clock()
316 			ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY);  in ath5k_hw_set_sleep_clock()
317 			AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,  in ath5k_hw_set_sleep_clock()
320 			ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT);  in ath5k_hw_set_sleep_clock()
321 			ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL);  in ath5k_hw_set_sleep_clock()
322 			ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK);  in ath5k_hw_set_sleep_clock()
323 			ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY);  in ath5k_hw_set_sleep_clock()
324 			AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,  in ath5k_hw_set_sleep_clock()
329 		AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG,  in ath5k_hw_set_sleep_clock()
336 		AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,  in ath5k_hw_set_sleep_clock()
339 		AR5K_REG_WRITE_BITS(ah, AR5K_PCICFG,  in ath5k_hw_set_sleep_clock()
343 		ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR);  in ath5k_hw_set_sleep_clock()
344 		ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);  in ath5k_hw_set_sleep_clock()
346 		if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))  in ath5k_hw_set_sleep_clock()
352 		ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL);  in ath5k_hw_set_sleep_clock()
354 		ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);  in ath5k_hw_set_sleep_clock()
355 		ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);  in ath5k_hw_set_sleep_clock()
357 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
358 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
359 		(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
360 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))  in ath5k_hw_set_sleep_clock()
364 		ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING);  in ath5k_hw_set_sleep_clock()
367 		AR5K_REG_WRITE_BITS(ah, AR5K_TSF_PARM, AR5K_TSF_PARM_INC, 1);  in ath5k_hw_set_sleep_clock()
369 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
370 			(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
371 			(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
372 			(ah->ah_radio == AR5K_RF2317))  in ath5k_hw_set_sleep_clock()
376 		AR5K_REG_WRITE_BITS(ah, AR5K_USEC_5211, AR5K_USEC_32, sclock);  in ath5k_hw_set_sleep_clock()
397 ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)  in ath5k_hw_nic_reset()  argument
403 	ath5k_hw_reg_read(ah, AR5K_RXDP);  in ath5k_hw_nic_reset()
408 	ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);  in ath5k_hw_nic_reset()
413 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_nic_reset()
423 	ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);  in ath5k_hw_nic_reset()
431 		ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);  in ath5k_hw_nic_reset()
446 ath5k_hw_wisoc_reset(struct ath5k_hw *ah, u32 flags)  in ath5k_hw_wisoc_reset()  argument
454 	if (ah->devid >= AR5K_SREV_AR2315_R6) {  in ath5k_hw_wisoc_reset()
462 		if (to_platform_device(ah->dev)->id == 0) {  in ath5k_hw_wisoc_reset()
493 		ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);  in ath5k_hw_wisoc_reset()
514 ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,  in ath5k_hw_set_power_mode()  argument
520 	staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);  in ath5k_hw_set_power_mode()
528 			ath5k_hw_reg_write(ah,  in ath5k_hw_set_power_mode()
538 			ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,  in ath5k_hw_set_power_mode()
551 		data = ath5k_hw_reg_read(ah, AR5K_SLEEP_CTL);  in ath5k_hw_set_power_mode()
562 		ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,  in ath5k_hw_set_power_mode()
568 			if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &  in ath5k_hw_set_power_mode()
574 			ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE,  in ath5k_hw_set_power_mode()
589 	ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);  in ath5k_hw_set_power_mode()
607 ath5k_hw_on_hold(struct ath5k_hw *ah)  in ath5k_hw_on_hold()  argument
609 	struct pci_dev *pdev = ah->pdev;  in ath5k_hw_on_hold()
613 	if (ath5k_get_bus_type(ah) == ATH_AHB)  in ath5k_hw_on_hold()
617 	ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);  in ath5k_hw_on_hold()
619 		ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");  in ath5k_hw_on_hold()
633 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_on_hold()
634 		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |  in ath5k_hw_on_hold()
639 		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |  in ath5k_hw_on_hold()
644 		ATH5K_ERR(ah, "failed to put device on warm reset\n");  in ath5k_hw_on_hold()
649 	ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);  in ath5k_hw_on_hold()
651 		ATH5K_ERR(ah, "failed to put device on hold\n");  in ath5k_hw_on_hold()
669 ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel)  in ath5k_hw_nic_wakeup()  argument
671 	struct pci_dev *pdev = ah->pdev;  in ath5k_hw_nic_wakeup()
679 	if ((ath5k_get_bus_type(ah) != ATH_AHB) || channel) {  in ath5k_hw_nic_wakeup()
681 		ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);  in ath5k_hw_nic_wakeup()
683 			ATH5K_ERR(ah, "failed to wakeup the MAC Chip\n");  in ath5k_hw_nic_wakeup()
698 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
699 		ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |  in ath5k_hw_nic_wakeup()
704 		if (ath5k_get_bus_type(ah) == ATH_AHB)  in ath5k_hw_nic_wakeup()
705 			ret = ath5k_hw_wisoc_reset(ah, AR5K_RESET_CTL_PCU |  in ath5k_hw_nic_wakeup()
708 			ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |  in ath5k_hw_nic_wakeup()
713 		ATH5K_ERR(ah, "failed to reset the MAC Chip\n");  in ath5k_hw_nic_wakeup()
718 	ret = ath5k_hw_set_power_mode(ah, AR5K_PM_AWAKE, true, 0);  in ath5k_hw_nic_wakeup()
720 		ATH5K_ERR(ah, "failed to resume the MAC Chip\n");  in ath5k_hw_nic_wakeup()
727 	if (ath5k_get_bus_type(ah) == ATH_AHB)  in ath5k_hw_nic_wakeup()
728 		ret = ath5k_hw_wisoc_reset(ah, 0);  in ath5k_hw_nic_wakeup()
730 		ret = ath5k_hw_nic_reset(ah, 0);  in ath5k_hw_nic_wakeup()
733 		ATH5K_ERR(ah, "failed to warm reset the MAC Chip\n");  in ath5k_hw_nic_wakeup()
742 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
747 		if (ah->ah_radio >= AR5K_RF5112) {  in ath5k_hw_nic_wakeup()
769 				if (ah->ah_version == AR5K_AR5211)  in ath5k_hw_nic_wakeup()
779 			if (ah->ah_radio == AR5K_RF5413)  in ath5k_hw_nic_wakeup()
784 			ATH5K_ERR(ah, "invalid radio frequency mode\n");  in ath5k_hw_nic_wakeup()
791 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {  in ath5k_hw_nic_wakeup()
793 			if (ah->ah_radio != AR5K_RF2425)  in ath5k_hw_nic_wakeup()
795 		} else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {  in ath5k_hw_nic_wakeup()
796 			if (ah->ah_radio == AR5K_RF5413) {  in ath5k_hw_nic_wakeup()
797 				mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?  in ath5k_hw_nic_wakeup()
800 			} else if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_nic_wakeup()
801 				clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?  in ath5k_hw_nic_wakeup()
810 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_hw_nic_wakeup()
811 			ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,  in ath5k_hw_nic_wakeup()
815 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
818 		if (ath5k_hw_reg_read(ah, AR5K_PHY_PLL) != clock) {  in ath5k_hw_nic_wakeup()
819 			ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);  in ath5k_hw_nic_wakeup()
824 		ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);  in ath5k_hw_nic_wakeup()
825 		ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);  in ath5k_hw_nic_wakeup()
848 ath5k_hw_tweak_initval_settings(struct ath5k_hw *ah,  in ath5k_hw_tweak_initval_settings()  argument
851 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_tweak_initval_settings()
852 	    ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {  in ath5k_hw_tweak_initval_settings()
855 		ath5k_hw_reg_write(ah,  in ath5k_hw_tweak_initval_settings()
867 		AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,  in ath5k_hw_tweak_initval_settings()
870 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DAG_CCK_CTL,  in ath5k_hw_tweak_initval_settings()
874 		ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK);  in ath5k_hw_tweak_initval_settings()
878 	if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)  in ath5k_hw_tweak_initval_settings()
879 		ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH);  in ath5k_hw_tweak_initval_settings()
882 	if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)  in ath5k_hw_tweak_initval_settings()
883 		AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,  in ath5k_hw_tweak_initval_settings()
887 	if ((ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_tweak_initval_settings()
888 		(ah->ah_radio == AR5K_RF2317) ||  in ath5k_hw_tweak_initval_settings()
889 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {  in ath5k_hw_tweak_initval_settings()
897 		if (ath5k_hw_reg_read(ah, AR5K_PHY_FAST_ADC) != fast_adc)  in ath5k_hw_tweak_initval_settings()
898 				ath5k_hw_reg_write(ah, fast_adc,  in ath5k_hw_tweak_initval_settings()
903 	if (ah->ah_radio == AR5K_RF5112 &&  in ath5k_hw_tweak_initval_settings()
904 			ah->ah_radio_5ghz_revision <  in ath5k_hw_tweak_initval_settings()
907 		ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,  in ath5k_hw_tweak_initval_settings()
913 		ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);  in ath5k_hw_tweak_initval_settings()
916 	if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_tweak_initval_settings()
918 		ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT);  in ath5k_hw_tweak_initval_settings()
920 		ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311,  in ath5k_hw_tweak_initval_settings()
923 		AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5211,  in ath5k_hw_tweak_initval_settings()
927 	if (ah->ah_bwmode) {  in ath5k_hw_tweak_initval_settings()
931 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {  in ath5k_hw_tweak_initval_settings()
933 			AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,  in ath5k_hw_tweak_initval_settings()
940 			if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_tweak_initval_settings()
941 				AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,  in ath5k_hw_tweak_initval_settings()
945 			if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_tweak_initval_settings()
947 				ath5k_hw_reg_write(ah,  in ath5k_hw_tweak_initval_settings()
954 		} else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&  in ath5k_hw_tweak_initval_settings()
955 		(ah->ah_mac_srev <= AR5K_SREV_AR5414)) {  in ath5k_hw_tweak_initval_settings()
956 			AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL_5211,  in ath5k_hw_tweak_initval_settings()
960 	} else if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_tweak_initval_settings()
962 		ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020),  in ath5k_hw_tweak_initval_settings()
976 ath5k_hw_commit_eeprom_settings(struct ath5k_hw *ah,  in ath5k_hw_commit_eeprom_settings()  argument
979 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_commit_eeprom_settings()
984 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_commit_eeprom_settings()
987 	ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);  in ath5k_hw_commit_eeprom_settings()
1000 	if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {  in ath5k_hw_commit_eeprom_settings()
1002 			ath5k_hw_reg_write(ah,  in ath5k_hw_commit_eeprom_settings()
1009 			ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ);  in ath5k_hw_commit_eeprom_settings()
1013 		ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;  in ath5k_hw_commit_eeprom_settings()
1014 		ah->ah_txpower.txp_cck_ofdm_gainf_delta =  in ath5k_hw_commit_eeprom_settings()
1020 	ath5k_hw_set_antenna_switch(ah, ee_mode);  in ath5k_hw_commit_eeprom_settings()
1023 	ath5k_hw_reg_write(ah,  in ath5k_hw_commit_eeprom_settings()
1027 	if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&  in ath5k_hw_commit_eeprom_settings()
1028 	(ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {  in ath5k_hw_commit_eeprom_settings()
1030 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,  in ath5k_hw_commit_eeprom_settings()
1035 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,  in ath5k_hw_commit_eeprom_settings()
1040 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,  in ath5k_hw_commit_eeprom_settings()
1044 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,  in ath5k_hw_commit_eeprom_settings()
1049 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,  in ath5k_hw_commit_eeprom_settings()
1055 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SETTLING,  in ath5k_hw_commit_eeprom_settings()
1060 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN,  in ath5k_hw_commit_eeprom_settings()
1065 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,  in ath5k_hw_commit_eeprom_settings()
1069 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE,  in ath5k_hw_commit_eeprom_settings()
1074 		if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)  in ath5k_hw_commit_eeprom_settings()
1075 			AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,  in ath5k_hw_commit_eeprom_settings()
1081 	ath5k_hw_reg_write(ah,  in ath5k_hw_commit_eeprom_settings()
1088 	AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RF_CTL3,  in ath5k_hw_commit_eeprom_settings()
1093 	AR5K_REG_WRITE_BITS(ah, AR5K_PHY_NF,  in ath5k_hw_commit_eeprom_settings()
1100 	if (ath5k_hw_chan_has_spur_noise(ah, channel))  in ath5k_hw_commit_eeprom_settings()
1101 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,  in ath5k_hw_commit_eeprom_settings()
1106 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR,  in ath5k_hw_commit_eeprom_settings()
1112 	if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {  in ath5k_hw_commit_eeprom_settings()
1113 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF,  in ath5k_hw_commit_eeprom_settings()
1115 		AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF,  in ath5k_hw_commit_eeprom_settings()
1117 		AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);  in ath5k_hw_commit_eeprom_settings()
1121 	if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)  in ath5k_hw_commit_eeprom_settings()
1122 		ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE);  in ath5k_hw_commit_eeprom_settings()
1146 ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,  in ath5k_hw_reset()  argument
1162 	if (fast && (ah->ah_radio != AR5K_RF2413) &&  in ath5k_hw_reset()
1163 	(ah->ah_radio != AR5K_RF5413))  in ath5k_hw_reset()
1169 	if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_reset()
1170 		ath5k_hw_set_sleep_clock(ah, false);  in ath5k_hw_reset()
1177 		if (ah->ah_version <= AR5K_AR5211) {  in ath5k_hw_reset()
1178 			ATH5K_ERR(ah,  in ath5k_hw_reset()
1184 		if (ah->ah_version < AR5K_AR5211) {  in ath5k_hw_reset()
1185 			ATH5K_ERR(ah,  in ath5k_hw_reset()
1191 		ATH5K_ERR(ah,  in ath5k_hw_reset()
1201 		ret = ath5k_hw_phy_init(ah, channel, mode, true);  in ath5k_hw_reset()
1203 			ATH5K_DBG(ah, ATH5K_DEBUG_RESET,  in ath5k_hw_reset()
1209 			ATH5K_DBG(ah, ATH5K_DEBUG_RESET,  in ath5k_hw_reset()
1218 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_reset()
1224 		if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_reset()
1227 				s_seq[i] = ath5k_hw_reg_read(ah,  in ath5k_hw_reset()
1231 			s_seq[0] = ath5k_hw_reg_read(ah,  in ath5k_hw_reset()
1248 		if (ah->ah_version == AR5K_AR5211) {  in ath5k_hw_reset()
1249 			tsf_up = ath5k_hw_reg_read(ah, AR5K_TSF_U32);  in ath5k_hw_reset()
1250 			tsf_lo = ath5k_hw_reg_read(ah, AR5K_TSF_L32);  in ath5k_hw_reset()
1256 	s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) &  in ath5k_hw_reset()
1258 	s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);  in ath5k_hw_reset()
1259 	s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);  in ath5k_hw_reset()
1267 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_reset()
1268 	(ah->ah_radio <= AR5K_RF5112)) {  in ath5k_hw_reset()
1269 		if (!fast && ah->ah_rf_banks != NULL)  in ath5k_hw_reset()
1270 				ath5k_hw_gainf_calibrate(ah);  in ath5k_hw_reset()
1274 	ret = ath5k_hw_nic_wakeup(ah, channel);  in ath5k_hw_reset()
1279 	if (ah->ah_mac_srev >= AR5K_SREV_AR5211)  in ath5k_hw_reset()
1280 		ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));  in ath5k_hw_reset()
1282 		ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40,  in ath5k_hw_reset()
1286 	ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);  in ath5k_hw_reset()
1291 	ath5k_hw_init_core_clock(ah);  in ath5k_hw_reset()
1298 	ath5k_hw_tweak_initval_settings(ah, channel);  in ath5k_hw_reset()
1301 	ath5k_hw_commit_eeprom_settings(ah, channel);  in ath5k_hw_reset()
1309 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_reset()
1310 		if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_reset()
1312 				ath5k_hw_reg_write(ah, s_seq[i],  in ath5k_hw_reset()
1315 			ath5k_hw_reg_write(ah, s_seq[0],  in ath5k_hw_reset()
1319 		if (ah->ah_version == AR5K_AR5211) {  in ath5k_hw_reset()
1320 			ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32);  in ath5k_hw_reset()
1321 			ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32);  in ath5k_hw_reset()
1326 	AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);  in ath5k_hw_reset()
1329 	ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);  in ath5k_hw_reset()
1330 	ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);  in ath5k_hw_reset()
1335 	ath5k_hw_pcu_init(ah, op_mode);  in ath5k_hw_reset()
1340 	ret = ath5k_hw_phy_init(ah, channel, mode, false);  in ath5k_hw_reset()
1342 		ATH5K_ERR(ah,  in ath5k_hw_reset()
1350 	ret = ath5k_hw_init_queues(ah);  in ath5k_hw_reset()
1358 	ath5k_hw_dma_init(ah);  in ath5k_hw_reset()
1370 	if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_reset()
1372 		ath5k_hw_set_sleep_clock(ah, true);  in ath5k_hw_reset()
1377 	AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);  in ath5k_hw_reset()
1378 	ath5k_hw_reset_tsf(ah);  in ath5k_hw_reset()