Lines Matching refs:ah
29 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah, in ar9002_hw_is_cal_supported() argument
34 switch (ah->supp_cals & cal_type) { in ar9002_hw_is_cal_supported()
41 if (!((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) && in ar9002_hw_is_cal_supported()
49 static void ar9002_hw_setup_calibration(struct ath_hw *ah, in ar9002_hw_setup_calibration() argument
52 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_setup_calibration()
54 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
60 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9002_hw_setup_calibration()
65 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); in ar9002_hw_setup_calibration()
69 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); in ar9002_hw_setup_calibration()
74 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
78 static bool ar9002_hw_per_calibration(struct ath_hw *ah, in ar9002_hw_per_calibration() argument
83 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9002_hw_per_calibration()
87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
90 currCal->calData->calCollect(ah); in ar9002_hw_per_calibration()
91 ah->cal_samples++; in ar9002_hw_per_calibration()
93 if (ah->cal_samples >= in ar9002_hw_per_calibration()
101 currCal->calData->calPostProc(ah, numChains); in ar9002_hw_per_calibration()
106 ar9002_hw_setup_calibration(ah, currCal); in ar9002_hw_per_calibration()
110 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_per_calibration()
116 static void ar9002_hw_iqcal_collect(struct ath_hw *ah) in ar9002_hw_iqcal_collect() argument
121 ah->totalPowerMeasI[i] += in ar9002_hw_iqcal_collect()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
123 ah->totalPowerMeasQ[i] += in ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
125 ah->totalIqCorrMeas[i] += in ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
127 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_iqcal_collect()
129 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9002_hw_iqcal_collect()
130 ah->totalPowerMeasQ[i], in ar9002_hw_iqcal_collect()
131 ah->totalIqCorrMeas[i]); in ar9002_hw_iqcal_collect()
135 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah) in ar9002_hw_adc_gaincal_collect() argument
140 ah->totalAdcIOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
142 ah->totalAdcIEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
144 ah->totalAdcQOddPhase[i] += in ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
146 ah->totalAdcQEvenPhase[i] += in ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
149 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_adc_gaincal_collect()
151 ah->cal_samples, i, in ar9002_hw_adc_gaincal_collect()
152 ah->totalAdcIOddPhase[i], in ar9002_hw_adc_gaincal_collect()
153 ah->totalAdcIEvenPhase[i], in ar9002_hw_adc_gaincal_collect()
154 ah->totalAdcQOddPhase[i], in ar9002_hw_adc_gaincal_collect()
155 ah->totalAdcQEvenPhase[i]); in ar9002_hw_adc_gaincal_collect()
159 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah) in ar9002_hw_adc_dccal_collect() argument
164 ah->totalAdcDcOffsetIOddPhase[i] += in ar9002_hw_adc_dccal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
166 ah->totalAdcDcOffsetIEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
168 ah->totalAdcDcOffsetQOddPhase[i] += in ar9002_hw_adc_dccal_collect()
169 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_dccal_collect()
170 ah->totalAdcDcOffsetQEvenPhase[i] += in ar9002_hw_adc_dccal_collect()
171 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_dccal_collect()
173 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9002_hw_adc_dccal_collect()
175 ah->cal_samples, i, in ar9002_hw_adc_dccal_collect()
176 ah->totalAdcDcOffsetIOddPhase[i], in ar9002_hw_adc_dccal_collect()
177 ah->totalAdcDcOffsetIEvenPhase[i], in ar9002_hw_adc_dccal_collect()
178 ah->totalAdcDcOffsetQOddPhase[i], in ar9002_hw_adc_dccal_collect()
179 ah->totalAdcDcOffsetQEvenPhase[i]); in ar9002_hw_adc_dccal_collect()
183 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_iqcalibrate() argument
185 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_iqcalibrate()
192 powerMeasI = ah->totalPowerMeasI[i]; in ar9002_hw_iqcalibrate()
193 powerMeasQ = ah->totalPowerMeasQ[i]; in ar9002_hw_iqcalibrate()
194 iqCorrMeas = ah->totalIqCorrMeas[i]; in ar9002_hw_iqcalibrate()
202 i, ah->totalIqCorrMeas[i]); in ar9002_hw_iqcalibrate()
244 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
247 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
256 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
260 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_gaincal_calibrate() argument
262 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_adc_gaincal_calibrate()
267 iOddMeasOffset = ah->totalAdcIOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
268 iEvenMeasOffset = ah->totalAdcIEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
269 qOddMeasOffset = ah->totalAdcQOddPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
270 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; in ar9002_hw_adc_gaincal_calibrate()
299 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_gaincal_calibrate()
302 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_gaincal_calibrate()
309 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_gaincal_calibrate()
310 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_gaincal_calibrate()
314 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains) in ar9002_hw_adc_dccal_calibrate() argument
316 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_adc_dccal_calibrate()
320 ah->cal_list_curr->calData; in ar9002_hw_adc_dccal_calibrate()
325 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
326 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
327 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; in ar9002_hw_adc_dccal_calibrate()
328 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; in ar9002_hw_adc_dccal_calibrate()
354 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); in ar9002_hw_adc_dccal_calibrate()
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); in ar9002_hw_adc_dccal_calibrate()
363 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0), in ar9002_hw_adc_dccal_calibrate()
364 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | in ar9002_hw_adc_dccal_calibrate()
368 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah) in ar9287_hw_olc_temp_compensation() argument
373 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9287_hw_olc_temp_compensation()
376 if (ah->initPDADC == 0 || currPDADC == 0) { in ar9287_hw_olc_temp_compensation()
384 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE); in ar9287_hw_olc_temp_compensation()
389 delta = ((currPDADC - ah->initPDADC)*4) / slope; in ar9287_hw_olc_temp_compensation()
391 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
393 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11, in ar9287_hw_olc_temp_compensation()
398 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah) in ar9280_hw_olc_temp_compensation() argument
403 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); in ar9280_hw_olc_temp_compensation()
406 if (ah->initPDADC == 0 || currPDADC == 0) in ar9280_hw_olc_temp_compensation()
409 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G)) in ar9280_hw_olc_temp_compensation()
410 delta = (currPDADC - ah->initPDADC + 4) / 8; in ar9280_hw_olc_temp_compensation()
412 delta = (currPDADC - ah->initPDADC + 5) / 10; in ar9280_hw_olc_temp_compensation()
414 if (delta != ah->PDADCdelta) { in ar9280_hw_olc_temp_compensation()
415 ah->PDADCdelta = delta; in ar9280_hw_olc_temp_compensation()
417 regval = ah->originalGain[i] - delta; in ar9280_hw_olc_temp_compensation()
421 REG_RMW_FIELD(ah, in ar9280_hw_olc_temp_compensation()
428 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9271_hw_pa_cal() argument
443 REG_READ_ARRAY(ah, regList, ARRAY_SIZE(regList)); in ar9271_hw_pa_cal()
445 ENABLE_REG_RMW_BUFFER(ah); in ar9271_hw_pa_cal()
447 REG_CLR_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
449 REG_SET_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
451 REG_SET_BIT(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC); in ar9271_hw_pa_cal()
453 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1); in ar9271_hw_pa_cal()
455 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I); in ar9271_hw_pa_cal()
457 REG_SET_BIT(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF); in ar9271_hw_pa_cal()
459 REG_CLR_BIT(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL); in ar9271_hw_pa_cal()
461 REG_CLR_BIT(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB); in ar9271_hw_pa_cal()
463 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL); in ar9271_hw_pa_cal()
465 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1); in ar9271_hw_pa_cal()
467 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2); in ar9271_hw_pa_cal()
469 REG_CLR_BIT(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT); in ar9271_hw_pa_cal()
471 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9271_hw_pa_cal()
476 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9271_hw_pa_cal()
478 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff); in ar9271_hw_pa_cal()
479 REG_RMW_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
485 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9271_hw_pa_cal()
487 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0); in ar9271_hw_pa_cal()
491 regVal = REG_READ(ah, AR9285_AN_RF2G6); in ar9271_hw_pa_cal()
493 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
497 regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9), in ar9271_hw_pa_cal()
500 REG_WRITE(ah, AR9285_AN_RF2G6, regVal); in ar9271_hw_pa_cal()
506 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) { in ar9271_hw_pa_cal()
507 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9271_hw_pa_cal()
508 ah->pacal_info.max_skipcount = in ar9271_hw_pa_cal()
509 2 * ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
510 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9271_hw_pa_cal()
512 ah->pacal_info.max_skipcount = 1; in ar9271_hw_pa_cal()
513 ah->pacal_info.skipcount = 0; in ar9271_hw_pa_cal()
514 ah->pacal_info.prev_offset = regVal; in ar9271_hw_pa_cal()
518 ENABLE_REG_RMW_BUFFER(ah); in ar9271_hw_pa_cal()
520 REG_SET_BIT(ah, AR9285_AN_RF2G6, 1 << 0); in ar9271_hw_pa_cal()
522 REG_CLR_BIT(ah, 0x9808, 1 << 27); in ar9271_hw_pa_cal()
523 REG_RMW_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
525 ENABLE_REGWRITE_BUFFER(ah); in ar9271_hw_pa_cal()
527 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9271_hw_pa_cal()
529 REGWRITE_BUFFER_FLUSH(ah); in ar9271_hw_pa_cal()
532 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9285_hw_pa_cal() argument
534 struct ath_common *common = ath9k_hw_common(ah); in ar9285_hw_pa_cal()
551 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == in ar9285_hw_pa_cal()
556 regList[i][1] = REG_READ(ah, regList[i][0]); in ar9285_hw_pa_cal()
558 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
560 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
561 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
563 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
565 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1); in ar9285_hw_pa_cal()
566 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1); in ar9285_hw_pa_cal()
567 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1); in ar9285_hw_pa_cal()
568 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1); in ar9285_hw_pa_cal()
569 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0); in ar9285_hw_pa_cal()
570 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0); in ar9285_hw_pa_cal()
571 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0); in ar9285_hw_pa_cal()
572 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0); in ar9285_hw_pa_cal()
573 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0); in ar9285_hw_pa_cal()
574 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0); in ar9285_hw_pa_cal()
575 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7); in ar9285_hw_pa_cal()
576 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0); in ar9285_hw_pa_cal()
577 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); in ar9285_hw_pa_cal()
578 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf); in ar9285_hw_pa_cal()
580 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ar9285_hw_pa_cal()
582 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0); in ar9285_hw_pa_cal()
583 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0); in ar9285_hw_pa_cal()
586 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
588 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
590 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
592 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
594 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
597 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1); in ar9285_hw_pa_cal()
599 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
600 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field); in ar9285_hw_pa_cal()
601 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); in ar9285_hw_pa_cal()
602 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); in ar9285_hw_pa_cal()
609 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) { in ar9285_hw_pa_cal()
610 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT) in ar9285_hw_pa_cal()
611 ah->pacal_info.max_skipcount = in ar9285_hw_pa_cal()
612 2 * ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
613 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount; in ar9285_hw_pa_cal()
615 ah->pacal_info.max_skipcount = 1; in ar9285_hw_pa_cal()
616 ah->pacal_info.skipcount = 0; in ar9285_hw_pa_cal()
617 ah->pacal_info.prev_offset = offset; in ar9285_hw_pa_cal()
620 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1); in ar9285_hw_pa_cal()
621 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0); in ar9285_hw_pa_cal()
623 regVal = REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
625 REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
626 regVal = REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
628 REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
631 REG_WRITE(ah, regList[i][0], regList[i][1]); in ar9285_hw_pa_cal()
633 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org); in ar9285_hw_pa_cal()
636 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset) in ar9002_hw_pa_cal() argument
638 if (AR_SREV_9271(ah)) { in ar9002_hw_pa_cal()
639 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
640 ar9271_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
642 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
643 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_pa_cal()
644 if (is_reset || !ah->pacal_info.skipcount) in ar9002_hw_pa_cal()
645 ar9285_hw_pa_cal(ah, is_reset); in ar9002_hw_pa_cal()
647 ah->pacal_info.skipcount--; in ar9002_hw_pa_cal()
651 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah) in ar9002_hw_olc_temp_compensation() argument
654 ar9287_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
656 ar9280_hw_olc_temp_compensation(ah); in ar9002_hw_olc_temp_compensation()
659 static int ar9002_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, in ar9002_hw_calibrate() argument
662 struct ath9k_cal_list *currCal = ah->cal_list_curr; in ar9002_hw_calibrate()
666 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF); in ar9002_hw_calibrate()
667 if (ah->caldata) in ar9002_hw_calibrate()
668 nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags); in ar9002_hw_calibrate()
675 if (!ar9002_hw_per_calibration(ah, chan, rxchainmask, currCal)) in ar9002_hw_calibrate()
678 ah->cal_list_curr = currCal = currCal->calNext; in ar9002_hw_calibrate()
680 ath9k_hw_reset_calibration(ah, currCal); in ar9002_hw_calibrate()
691 if (ath9k_hw_getnf(ah, chan)) { in ar9002_hw_calibrate()
698 ret = ath9k_hw_loadnf(ah, ah->curchan); in ar9002_hw_calibrate()
704 ath9k_hw_start_nfcal(ah, false); in ar9002_hw_calibrate()
706 ar9002_hw_pa_cal(ah, false); in ar9002_hw_calibrate()
707 ar9002_hw_olc_temp_compensation(ah); in ar9002_hw_calibrate()
715 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_cl_cal() argument
717 struct ath_common *common = ath9k_hw_common(ah); in ar9285_hw_cl_cal()
719 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
721 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
722 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
723 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
725 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
726 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
727 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9285_hw_cl_cal()
734 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
735 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
736 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
738 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
739 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
740 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
741 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
742 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, in ar9285_hw_cl_cal()
750 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
751 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
752 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
757 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan) in ar9285_hw_clc() argument
769 if (!(ar9285_hw_cl_cal(ah, chan))) in ar9285_hw_clc()
772 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), in ar9285_hw_clc()
776 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & in ar9285_hw_clc()
785 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
787 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) in ar9285_hw_clc()
797 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5); in ar9285_hw_clc()
798 if (AR_SREV_9285E_20(ah)) { in ar9285_hw_clc()
799 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
803 REG_WRITE(ah, AR9285_RF2G5, in ar9285_hw_clc()
807 retv = ar9285_hw_cl_cal(ah, chan); in ar9285_hw_clc()
808 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org); in ar9285_hw_clc()
813 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_init_cal() argument
815 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_init_cal()
817 if (AR_SREV_9271(ah)) { in ar9002_hw_init_cal()
818 if (!ar9285_hw_cl_cal(ah, chan)) in ar9002_hw_init_cal()
820 } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_cal()
821 if (!ar9285_hw_clc(ah, chan)) in ar9002_hw_init_cal()
824 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
825 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
826 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
828 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
833 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
834 REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar9002_hw_init_cal()
838 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
847 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal()
848 if (!AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_cal()
849 REG_SET_BIT(ah, AR_PHY_ADC_CTL, in ar9002_hw_init_cal()
851 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9002_hw_init_cal()
857 ar9002_hw_pa_cal(ah, true); in ar9002_hw_init_cal()
858 ath9k_hw_loadnf(ah, chan); in ar9002_hw_init_cal()
859 ath9k_hw_start_nfcal(ah, true); in ar9002_hw_init_cal()
861 if (ah->caldata) in ar9002_hw_init_cal()
862 set_bit(NFCAL_PENDING, &ah->caldata->cal_flags); in ar9002_hw_init_cal()
864 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9002_hw_init_cal()
867 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal()
868 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal()
870 if (AR_SREV_9160_10_OR_LATER(ah)) in ar9002_hw_init_cal()
871 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL; in ar9002_hw_init_cal()
873 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal()
874 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal()
876 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) { in ar9002_hw_init_cal()
877 INIT_CAL(&ah->adcgain_caldata); in ar9002_hw_init_cal()
878 INSERT_CAL(ah, &ah->adcgain_caldata); in ar9002_hw_init_cal()
883 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) { in ar9002_hw_init_cal()
884 INIT_CAL(&ah->adcdc_caldata); in ar9002_hw_init_cal()
885 INSERT_CAL(ah, &ah->adcdc_caldata); in ar9002_hw_init_cal()
890 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) { in ar9002_hw_init_cal()
891 INIT_CAL(&ah->iq_caldata); in ar9002_hw_init_cal()
892 INSERT_CAL(ah, &ah->iq_caldata); in ar9002_hw_init_cal()
896 ah->cal_list_curr = ah->cal_list; in ar9002_hw_init_cal()
898 if (ah->cal_list_curr) in ar9002_hw_init_cal()
899 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); in ar9002_hw_init_cal()
902 if (ah->caldata) in ar9002_hw_init_cal()
903 ah->caldata->CalValid = 0; in ar9002_hw_init_cal()
951 static void ar9002_hw_init_cal_settings(struct ath_hw *ah) in ar9002_hw_init_cal_settings() argument
953 if (AR_SREV_9100(ah)) { in ar9002_hw_init_cal_settings()
954 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
955 ah->supp_cals = IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
959 if (AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
960 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_cal_settings()
961 ah->iq_caldata.calData = &iq_cal_single_sample; in ar9002_hw_init_cal_settings()
962 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
964 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
967 ah->iq_caldata.calData = &iq_cal_multi_sample; in ar9002_hw_init_cal_settings()
968 ah->adcgain_caldata.calData = in ar9002_hw_init_cal_settings()
970 ah->adcdc_caldata.calData = in ar9002_hw_init_cal_settings()
973 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; in ar9002_hw_init_cal_settings()
975 if (AR_SREV_9287(ah)) in ar9002_hw_init_cal_settings()
976 ah->supp_cals &= ~ADC_GAIN_CAL; in ar9002_hw_init_cal_settings()
980 void ar9002_hw_attach_calib_ops(struct ath_hw *ah) in ar9002_hw_attach_calib_ops() argument
982 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_calib_ops()
983 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_calib_ops()