Lines Matching refs:ah
26 static int ar9002_hw_init_mode_regs(struct ath_hw *ah) in ar9002_hw_init_mode_regs() argument
28 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_regs()
29 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271); in ar9002_hw_init_mode_regs()
30 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271); in ar9002_hw_init_mode_regs()
31 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg); in ar9002_hw_init_mode_regs()
35 INIT_INI_ARRAY(&ah->iniPcieSerdes, in ar9002_hw_init_mode_regs()
38 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
39 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1); in ar9002_hw_init_mode_regs()
40 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1); in ar9002_hw_init_mode_regs()
41 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
42 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2); in ar9002_hw_init_mode_regs()
43 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2); in ar9002_hw_init_mode_regs()
44 } else if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
45 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2); in ar9002_hw_init_mode_regs()
46 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2); in ar9002_hw_init_mode_regs()
48 INIT_INI_ARRAY(&ah->iniModesFastClock, in ar9002_hw_init_mode_regs()
50 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
51 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160); in ar9002_hw_init_mode_regs()
52 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160); in ar9002_hw_init_mode_regs()
53 if (AR_SREV_9160_11(ah)) { in ar9002_hw_init_mode_regs()
54 INIT_INI_ARRAY(&ah->iniAddac, in ar9002_hw_init_mode_regs()
57 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160); in ar9002_hw_init_mode_regs()
59 } else if (AR_SREV_9100_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
60 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100); in ar9002_hw_init_mode_regs()
61 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100); in ar9002_hw_init_mode_regs()
62 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100); in ar9002_hw_init_mode_regs()
64 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes); in ar9002_hw_init_mode_regs()
65 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common); in ar9002_hw_init_mode_regs()
66 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac); in ar9002_hw_init_mode_regs()
69 if (!AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
71 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain); in ar9002_hw_init_mode_regs()
74 if (!AR_SREV_5416(ah)) in ar9002_hw_init_mode_regs()
75 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC_9100); in ar9002_hw_init_mode_regs()
77 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6TPC); in ar9002_hw_init_mode_regs()
81 if (AR_SREV_9160(ah) || !AR_SREV_5416_22_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
82 struct ar5416IniArray *addac = &ah->iniAddac; in ar9002_hw_init_mode_regs()
86 data = devm_kzalloc(ah->dev, size, GFP_KERNEL); in ar9002_hw_init_mode_regs()
93 if (!AR_SREV_5416_22_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
98 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_regs()
99 INIT_INI_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_init_mode_regs()
101 INIT_INI_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_init_mode_regs()
107 static void ar9280_20_hw_init_rxgain_ini(struct ath_hw *ah) in ar9280_20_hw_init_rxgain_ini() argument
111 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= in ar9280_20_hw_init_rxgain_ini()
113 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE); in ar9280_20_hw_init_rxgain_ini()
116 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
119 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
122 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
125 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9280_20_hw_init_rxgain_ini()
130 static void ar9280_20_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) in ar9280_20_hw_init_txgain_ini() argument
132 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= in ar9280_20_hw_init_txgain_ini()
135 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
138 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
141 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9280_20_hw_init_txgain_ini()
146 static void ar9271_hw_init_txgain_ini(struct ath_hw *ah, u32 txgain_type) in ar9271_hw_init_txgain_ini() argument
149 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
152 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9271_hw_init_txgain_ini()
156 static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah) in ar9002_hw_init_mode_gain_regs() argument
158 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE); in ar9002_hw_init_mode_gain_regs()
160 if (AR_SREV_9287_11_OR_LATER(ah)) in ar9002_hw_init_mode_gain_regs()
161 INIT_INI_ARRAY(&ah->iniModesRxGain, in ar9002_hw_init_mode_gain_regs()
163 else if (AR_SREV_9280_20(ah)) in ar9002_hw_init_mode_gain_regs()
164 ar9280_20_hw_init_rxgain_ini(ah); in ar9002_hw_init_mode_gain_regs()
166 if (AR_SREV_9271(ah)) { in ar9002_hw_init_mode_gain_regs()
167 ar9271_hw_init_txgain_ini(ah, txgain_type); in ar9002_hw_init_mode_gain_regs()
168 } else if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_init_mode_gain_regs()
169 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
171 } else if (AR_SREV_9280_20(ah)) { in ar9002_hw_init_mode_gain_regs()
172 ar9280_20_hw_init_txgain_ini(ah, txgain_type); in ar9002_hw_init_mode_gain_regs()
173 } else if (AR_SREV_9285_12_OR_LATER(ah)) { in ar9002_hw_init_mode_gain_regs()
176 if (AR_SREV_9285E_20(ah)) { in ar9002_hw_init_mode_gain_regs()
177 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
180 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
184 if (AR_SREV_9285E_20(ah)) { in ar9002_hw_init_mode_gain_regs()
185 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
188 INIT_INI_ARRAY(&ah->iniModesTxGain, in ar9002_hw_init_mode_gain_regs()
204 static void ar9002_hw_configpcipowersave(struct ath_hw *ah, in ar9002_hw_configpcipowersave() argument
212 if (AR_SREV_9280_20_OR_LATER(ah)) { in ar9002_hw_configpcipowersave()
218 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) { in ar9002_hw_configpcipowersave()
219 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), in ar9002_hw_configpcipowersave()
220 INI_RA(&ah->iniPcieSerdes, i, 1)); in ar9002_hw_configpcipowersave()
223 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_configpcipowersave()
225 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ar9002_hw_configpcipowersave()
226 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ar9002_hw_configpcipowersave()
229 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); in ar9002_hw_configpcipowersave()
230 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); in ar9002_hw_configpcipowersave()
231 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); in ar9002_hw_configpcipowersave()
237 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); in ar9002_hw_configpcipowersave()
239 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ar9002_hw_configpcipowersave()
240 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ar9002_hw_configpcipowersave()
241 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007); in ar9002_hw_configpcipowersave()
244 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ar9002_hw_configpcipowersave()
246 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_configpcipowersave()
254 REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
256 val = REG_READ(ah, AR_WA); in ar9002_hw_configpcipowersave()
264 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
265 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE) in ar9002_hw_configpcipowersave()
268 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
271 } else if (AR_SREV_9280(ah)) { in ar9002_hw_configpcipowersave()
277 if (AR_SREV_9280(ah) || AR_SREV_9285(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
285 if (AR_SREV_9280(ah)) in ar9002_hw_configpcipowersave()
288 if (AR_SREV_9285E_20(ah)) in ar9002_hw_configpcipowersave()
291 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
293 if (ah->config.pcie_waen) { in ar9002_hw_configpcipowersave()
294 val = ah->config.pcie_waen; in ar9002_hw_configpcipowersave()
297 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) || AR_SREV_9287(ah)) { in ar9002_hw_configpcipowersave()
300 } else if (AR_SREV_9280(ah)) { in ar9002_hw_configpcipowersave()
313 if (AR_SREV_9285(ah) || AR_SREV_9287(ah)) in ar9002_hw_configpcipowersave()
316 if (AR_SREV_9285E_20(ah)) in ar9002_hw_configpcipowersave()
319 REG_WRITE(ah, AR_WA, val); in ar9002_hw_configpcipowersave()
322 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
326 static int ar9002_hw_get_radiorev(struct ath_hw *ah) in ar9002_hw_get_radiorev() argument
331 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_get_radiorev()
333 REG_WRITE(ah, AR_PHY(0x36), 0x00007058); in ar9002_hw_get_radiorev()
335 REG_WRITE(ah, AR_PHY(0x20), 0x00010000); in ar9002_hw_get_radiorev()
337 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_get_radiorev()
339 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; in ar9002_hw_get_radiorev()
345 int ar9002_hw_rf_claim(struct ath_hw *ah) in ar9002_hw_rf_claim() argument
349 REG_WRITE(ah, AR_PHY(0), 0x00000007); in ar9002_hw_rf_claim()
351 val = ar9002_hw_get_radiorev(ah); in ar9002_hw_rf_claim()
362 ath_err(ath9k_hw_common(ah), in ar9002_hw_rf_claim()
368 ah->hw_version.analog5GhzRev = val; in ar9002_hw_rf_claim()
373 void ar9002_hw_enable_async_fifo(struct ath_hw *ah) in ar9002_hw_enable_async_fifo() argument
375 if (AR_SREV_9287_13_OR_LATER(ah)) { in ar9002_hw_enable_async_fifo()
376 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
378 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
379 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
381 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
386 static void ar9002_hw_init_hang_checks(struct ath_hw *ah) in ar9002_hw_init_hang_checks() argument
388 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) { in ar9002_hw_init_hang_checks()
389 ah->config.hw_hang_checks |= HW_BB_RIFS_HANG; in ar9002_hw_init_hang_checks()
390 ah->config.hw_hang_checks |= HW_BB_DFS_HANG; in ar9002_hw_init_hang_checks()
393 if (AR_SREV_9280(ah)) in ar9002_hw_init_hang_checks()
394 ah->config.hw_hang_checks |= HW_BB_RX_CLEAR_STUCK_HANG; in ar9002_hw_init_hang_checks()
396 if (AR_SREV_5416(ah) || AR_SREV_9100(ah) || AR_SREV_9160(ah)) in ar9002_hw_init_hang_checks()
397 ah->config.hw_hang_checks |= HW_MAC_HANG; in ar9002_hw_init_hang_checks()
401 int ar9002_hw_attach_ops(struct ath_hw *ah) in ar9002_hw_attach_ops() argument
403 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_ops()
404 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_ops()
407 ret = ar9002_hw_init_mode_regs(ah); in ar9002_hw_attach_ops()
416 ret = ar5008_hw_attach_phy_ops(ah); in ar9002_hw_attach_ops()
420 if (AR_SREV_9280_20_OR_LATER(ah)) in ar9002_hw_attach_ops()
421 ar9002_hw_attach_phy_ops(ah); in ar9002_hw_attach_ops()
423 ar9002_hw_attach_calib_ops(ah); in ar9002_hw_attach_ops()
424 ar9002_hw_attach_mac_ops(ah); in ar9002_hw_attach_ops()
428 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_load_ani_reg() argument
438 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_load_ani_reg()
440 for (i = 0; i < ah->iniModes_9271_ANI_reg.ia_rows; i++) { in ar9002_hw_load_ani_reg()
441 u32 reg = INI_RA(&ah->iniModes_9271_ANI_reg, i, 0); in ar9002_hw_load_ani_reg()
442 u32 val = INI_RA(&ah->iniModes_9271_ANI_reg, i, modesIndex); in ar9002_hw_load_ani_reg()
446 val_orig = REG_READ(ah, reg); in ar9002_hw_load_ani_reg()
450 REG_WRITE(ah, reg, val|val_orig); in ar9002_hw_load_ani_reg()
452 REG_WRITE(ah, reg, val); in ar9002_hw_load_ani_reg()
455 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_load_ani_reg()