Lines Matching refs:ah
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9002_hw_set_channel() argument
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9002_hw_set_channel()
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
88 if (AR_SREV_9287_11_OR_LATER(ah)) { in ar9002_hw_set_channel()
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484, in ar9002_hw_set_channel()
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal, in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ar9002_hw_set_channel()
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) { in ar9002_hw_set_channel()
134 ath9k_hw_analog_shift_rmw(ah, AR_AN_SYNTH9, in ar9002_hw_set_channel()
152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
154 ah->curchan = chan; in ar9002_hw_set_channel()
167 static void ar9002_hw_spur_mitigate(struct ath_hw *ah, in ar9002_hw_spur_mitigate() argument
201 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9002_hw_spur_mitigate()
205 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz); in ar9002_hw_spur_mitigate()
231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
235 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, in ar9002_hw_spur_mitigate()
241 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
243 ENABLE_REGWRITE_BUFFER(ah); in ar9002_hw_spur_mitigate()
249 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
256 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); in ar9002_hw_spur_mitigate()
286 REG_WRITE(ah, AR_PHY_TIMING11, newVal); in ar9002_hw_spur_mitigate()
289 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); in ar9002_hw_spur_mitigate()
307 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); in ar9002_hw_spur_mitigate()
308 REG_WRITE(ah, chan_mask_reg[i], chan_mask); in ar9002_hw_spur_mitigate()
341 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); in ar9002_hw_spur_mitigate()
342 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); in ar9002_hw_spur_mitigate()
352 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); in ar9002_hw_spur_mitigate()
353 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); in ar9002_hw_spur_mitigate()
363 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); in ar9002_hw_spur_mitigate()
364 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); in ar9002_hw_spur_mitigate()
374 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); in ar9002_hw_spur_mitigate()
375 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); in ar9002_hw_spur_mitigate()
385 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); in ar9002_hw_spur_mitigate()
386 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); in ar9002_hw_spur_mitigate()
396 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); in ar9002_hw_spur_mitigate()
397 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); in ar9002_hw_spur_mitigate()
407 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); in ar9002_hw_spur_mitigate()
408 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); in ar9002_hw_spur_mitigate()
418 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); in ar9002_hw_spur_mitigate()
419 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); in ar9002_hw_spur_mitigate()
421 REGWRITE_BUFFER_FLUSH(ah); in ar9002_hw_spur_mitigate()
424 static void ar9002_olc_init(struct ath_hw *ah) in ar9002_olc_init() argument
432 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
434 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0, in ar9002_olc_init()
441 ah->originalGain[i] = in ar9002_olc_init()
442 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
444 ah->PDADCdelta = 0; in ar9002_olc_init()
448 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah, in ar9002_hw_compute_pll_control() argument
455 if (chan && IS_CHAN_5GHZ(chan) && !IS_CHAN_A_FAST_CLOCK(ah, chan)) { in ar9002_hw_compute_pll_control()
456 if (AR_SREV_9280_20(ah)) { in ar9002_hw_compute_pll_control()
475 static void ar9002_hw_do_getnf(struct ath_hw *ah, in ar9002_hw_do_getnf() argument
480 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
483 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
484 if (IS_CHAN_HT40(ah->curchan)) in ar9002_hw_do_getnf()
487 if (!(ah->rxchainmask & BIT(1))) in ar9002_hw_do_getnf()
490 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
493 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
494 if (IS_CHAN_HT40(ah->curchan)) in ar9002_hw_do_getnf()
498 static void ar9002_hw_set_nf_limits(struct ath_hw *ah) in ar9002_hw_set_nf_limits() argument
500 if (AR_SREV_9285(ah)) { in ar9002_hw_set_nf_limits()
501 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
502 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
503 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ; in ar9002_hw_set_nf_limits()
504 } else if (AR_SREV_9287(ah)) { in ar9002_hw_set_nf_limits()
505 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
506 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
507 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ; in ar9002_hw_set_nf_limits()
508 } else if (AR_SREV_9271(ah)) { in ar9002_hw_set_nf_limits()
509 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
510 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
511 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ; in ar9002_hw_set_nf_limits()
513 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
514 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
515 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; in ar9002_hw_set_nf_limits()
516 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
517 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
518 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; in ar9002_hw_set_nf_limits()
522 static void ar9002_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9002_hw_antdiv_comb_conf_get() argument
527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
539 static void ar9002_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9002_hw_antdiv_comb_conf_set() argument
544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
555 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_antdiv_comb_conf_set()
560 static void ar9002_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9002_hw_set_bt_ant_diversity() argument
562 struct ath_btcoex_hw *btcoex = &ah->btcoex_hw; in ar9002_hw_set_bt_ant_diversity()
574 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
576 REG_WRITE(ah, AR_PHY_SWITCH_COM, ATH_BT_COEX_ANT_DIV_SWITCH_COM); in ar9002_hw_set_bt_ant_diversity()
577 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
589 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); in ar9002_hw_set_bt_ant_diversity()
595 REG_WRITE(ah, AR_PHY_SWITCH_COM, 0); in ar9002_hw_set_bt_ant_diversity()
596 REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9002_hw_set_bt_ant_diversity()
599 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_set_bt_ant_diversity()
611 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval); in ar9002_hw_set_bt_ant_diversity()
613 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9002_hw_set_bt_ant_diversity()
616 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9002_hw_set_bt_ant_diversity()
621 static void ar9002_hw_spectral_scan_config(struct ath_hw *ah, in ar9002_hw_spectral_scan_config() argument
627 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
631 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9002_hw_spectral_scan_config()
632 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_config()
635 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
638 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
647 if (AR_SREV_9271(ah)) in ar9002_hw_spectral_scan_config()
654 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
656 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
658 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
664 static void ar9002_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9002_hw_spectral_scan_trigger() argument
666 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_trigger()
668 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_trigger()
672 static void ar9002_hw_spectral_scan_wait(struct ath_hw *ah) in ar9002_hw_spectral_scan_wait() argument
674 struct ath_common *common = ath9k_hw_common(ah); in ar9002_hw_spectral_scan_wait()
677 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_wait()
685 static void ar9002_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9002_hw_tx99_start() argument
687 REG_SET_BIT(ah, 0x9864, 0x7f000); in ar9002_hw_tx99_start()
688 REG_SET_BIT(ah, 0x9924, 0x7f00fe); in ar9002_hw_tx99_start()
689 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_start()
690 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9002_hw_tx99_start()
691 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9002_hw_tx99_start()
692 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); in ar9002_hw_tx99_start()
693 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9002_hw_tx99_start()
694 REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); in ar9002_hw_tx99_start()
695 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9002_hw_tx99_start()
696 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9002_hw_tx99_start()
697 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9002_hw_tx99_start()
700 static void ar9002_hw_tx99_stop(struct ath_hw *ah) in ar9002_hw_tx99_stop() argument
702 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9002_hw_tx99_stop()
705 void ar9002_hw_attach_phy_ops(struct ath_hw *ah) in ar9002_hw_attach_phy_ops() argument
707 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9002_hw_attach_phy_ops()
708 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9002_hw_attach_phy_ops()
729 ar9002_hw_set_nf_limits(ah); in ar9002_hw_attach_phy_ops()