525 	u32 regval;  in ar9002_hw_antdiv_comb_conf_get()  local
527 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_antdiv_comb_conf_get()
528 	antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>  in ar9002_hw_antdiv_comb_conf_get()
530 	antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>  in ar9002_hw_antdiv_comb_conf_get()
532 	antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>  in ar9002_hw_antdiv_comb_conf_get()
542 	u32 regval;  in ar9002_hw_antdiv_comb_conf_set()  local
544 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_antdiv_comb_conf_set()
545 	regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |  in ar9002_hw_antdiv_comb_conf_set()
548 	regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)  in ar9002_hw_antdiv_comb_conf_set()
550 	regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)  in ar9002_hw_antdiv_comb_conf_set()
552 	regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)  in ar9002_hw_antdiv_comb_conf_set()
555 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_antdiv_comb_conf_set()
564 	u32 regval;  in ar9002_hw_set_bt_ant_diversity()  local
599 	regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);  in ar9002_hw_set_bt_ant_diversity()
600 	regval &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));  in ar9002_hw_set_bt_ant_diversity()
605 	regval &= (~(AR_PHY_9285_FAST_DIV_BIAS));  in ar9002_hw_set_bt_ant_diversity()
606 	regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL);  in ar9002_hw_set_bt_ant_diversity()
607 	regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF);  in ar9002_hw_set_bt_ant_diversity()
608 	regval |= SM((antdiv_ctrl2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF);  in ar9002_hw_set_bt_ant_diversity()
609 	regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB);  in ar9002_hw_set_bt_ant_diversity()
610 	regval |= SM((antdiv_ctrl1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB);  in ar9002_hw_set_bt_ant_diversity()
611 	REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);  in ar9002_hw_set_bt_ant_diversity()
613 	regval = REG_READ(ah, AR_PHY_CCK_DETECT);  in ar9002_hw_set_bt_ant_diversity()
614 	regval &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);  in ar9002_hw_set_bt_ant_diversity()
615 	regval |= SM((antdiv_ctrl1 >> 3), AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);  in ar9002_hw_set_bt_ant_diversity()
616 	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);  in ar9002_hw_set_bt_ant_diversity()