40 static bool ar9003_hw_is_aic_enabled(struct ath_hw *ah)  in ar9003_hw_is_aic_enabled()  argument
42 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;  in ar9003_hw_is_aic_enabled()
106 static void ar9003_aic_gain_table(struct ath_hw *ah)  in ar9003_aic_gain_table()  argument
111 	REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);  in ar9003_aic_gain_table()
112 	REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);  in ar9003_aic_gain_table()
155 	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),  in ar9003_aic_gain_table()
160 		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),  in ar9003_aic_gain_table()
165 static u8 ar9003_aic_cal_start(struct ath_hw *ah, u8 min_valid_count)  in ar9003_aic_cal_start()  argument
167 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_cal_start()
171 	REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),  in ar9003_aic_cal_start()
176 		REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);  in ar9003_aic_cal_start()
180 	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,  in ar9003_aic_cal_start()
190 	REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,  in ar9003_aic_cal_start()
197 	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,  in ar9003_aic_cal_start()
206 	REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,  in ar9003_aic_cal_start()
210 	REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,  in ar9003_aic_cal_start()
220 	REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,  in ar9003_aic_cal_start()
230 	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,  in ar9003_aic_cal_start()
237 	REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,  in ar9003_aic_cal_start()
244 	ar9003_aic_gain_table(ah);  in ar9003_aic_cal_start()
247 	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,  in ar9003_aic_cal_start()
248 		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |  in ar9003_aic_cal_start()
251 	aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);  in ar9003_aic_cal_start()
254 	REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);  in ar9003_aic_cal_start()
255 	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);  in ar9003_aic_cal_start()
256 	REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);  in ar9003_aic_cal_start()
264 static bool ar9003_aic_cal_post_process(struct ath_hw *ah)  in ar9003_aic_cal_post_process()  argument
266 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_cal_post_process()
436 static void ar9003_aic_cal_done(struct ath_hw *ah)  in ar9003_aic_cal_done()  argument
438 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_cal_done()
441 	REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,  in ar9003_aic_cal_done()
442 		  (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &  in ar9003_aic_cal_done()
445 	if (ar9003_aic_cal_post_process(ah))  in ar9003_aic_cal_done()
451 static u8 ar9003_aic_cal_continue(struct ath_hw *ah, bool cal_once)  in ar9003_aic_cal_continue()  argument
453 	struct ath_common *common = ath9k_hw_common(ah);  in ar9003_aic_cal_continue()
454 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;  in ar9003_aic_cal_continue()
455 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_cal_continue()
467 			if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &  in ar9003_aic_cal_continue()
479 	if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) &  in ar9003_aic_cal_continue()
485 	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,  in ar9003_aic_cal_continue()
491 		value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);  in ar9003_aic_cal_continue()
505 		ar9003_aic_cal_done(ah);  in ar9003_aic_cal_continue()
508 		REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);  in ar9003_aic_cal_continue()
509 		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1,  in ar9003_aic_cal_continue()
511 		REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);  in ar9003_aic_cal_continue()
518 u8 ar9003_aic_calibration(struct ath_hw *ah)  in ar9003_aic_calibration()  argument
520 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_calibration()
525 		cal_ret = ar9003_aic_cal_start(ah, 1);  in ar9003_aic_calibration()
528 		cal_ret = ar9003_aic_cal_continue(ah, false);  in ar9003_aic_calibration()
540 u8 ar9003_aic_start_normal(struct ath_hw *ah)  in ar9003_aic_start_normal()  argument
542 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_start_normal()
548 	ar9003_aic_gain_table(ah);  in ar9003_aic_start_normal()
550 	REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT);  in ar9003_aic_start_normal()
553 		REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, aic->aic_sram[i]);  in ar9003_aic_start_normal()
557 	REG_WRITE(ah, 0xa6b0, 0x80);  in ar9003_aic_start_normal()
558 	REG_WRITE(ah, 0xa6b4, 0x5b2df0);  in ar9003_aic_start_normal()
559 	REG_WRITE(ah, 0xa6b8, 0x10762cc8);  in ar9003_aic_start_normal()
560 	REG_WRITE(ah, 0xa6bc, 0x1219a4b);  in ar9003_aic_start_normal()
561 	REG_WRITE(ah, 0xa6c0, 0x1e01);  in ar9003_aic_start_normal()
562 	REG_WRITE(ah, 0xb6b4, 0xf0);  in ar9003_aic_start_normal()
563 	REG_WRITE(ah, 0xb6c0, 0x1e01);  in ar9003_aic_start_normal()
564 	REG_WRITE(ah, 0xb6b0, 0x81);  in ar9003_aic_start_normal()
565 	REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX4, 0x40000000);  in ar9003_aic_start_normal()
572 u8 ar9003_aic_cal_reset(struct ath_hw *ah)  in ar9003_aic_cal_reset()  argument
574 	struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;  in ar9003_aic_cal_reset()
580 u8 ar9003_aic_calibration_single(struct ath_hw *ah)  in ar9003_aic_calibration_single()  argument
582 	struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;  in ar9003_aic_calibration_single()
588 	(void) ar9003_aic_cal_start(ah, num_chan);  in ar9003_aic_calibration_single()
589 	cal_ret = ar9003_aic_cal_continue(ah, true);  in ar9003_aic_calibration_single()
594 void ar9003_hw_attach_aic_ops(struct ath_hw *ah)  in ar9003_hw_attach_aic_ops()  argument
596 	struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);  in ar9003_hw_attach_aic_ops()