Lines Matching refs:ah
38 static void ar9003_hw_setup_calibration(struct ath_hw *ah, in ar9003_hw_setup_calibration() argument
41 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_setup_calibration()
50 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_setup_calibration()
53 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); in ar9003_hw_setup_calibration()
59 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
72 static bool ar9003_hw_per_calibration(struct ath_hw *ah, in ar9003_hw_per_calibration() argument
77 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_per_calibration()
84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { in ar9003_hw_per_calibration()
88 currCal->calData->calCollect(ah); in ar9003_hw_per_calibration()
89 ah->cal_samples++; in ar9003_hw_per_calibration()
91 if (ah->cal_samples >= in ar9003_hw_per_calibration()
102 currCal->calData->calPostProc(ah, numChains); in ar9003_hw_per_calibration()
113 ar9003_hw_setup_calibration(ah, currCal); in ar9003_hw_per_calibration()
118 ath9k_hw_reset_calibration(ah, currCal); in ar9003_hw_per_calibration()
124 static int ar9003_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan, in ar9003_hw_calibrate() argument
128 struct ath9k_cal_list *currCal = ah->cal_list_curr; in ar9003_hw_calibrate()
143 iscaldone = ar9003_hw_per_calibration(ah, chan, in ar9003_hw_calibrate()
146 ah->cal_list_curr = currCal = currCal->calNext; in ar9003_hw_calibrate()
150 ath9k_hw_reset_calibration(ah, currCal); in ar9003_hw_calibrate()
159 if (longcal && ath9k_hw_getnf(ah, chan)) { in ar9003_hw_calibrate()
165 ret = ath9k_hw_loadnf(ah, ah->curchan); in ar9003_hw_calibrate()
170 ath9k_hw_start_nfcal(ah, false); in ar9003_hw_calibrate()
176 static void ar9003_hw_iqcal_collect(struct ath_hw *ah) in ar9003_hw_iqcal_collect() argument
182 if (ah->txchainmask & BIT(i)) { in ar9003_hw_iqcal_collect()
183 ah->totalPowerMeasI[i] += in ar9003_hw_iqcal_collect()
184 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 ah->totalPowerMeasQ[i] += in ar9003_hw_iqcal_collect()
186 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
187 ah->totalIqCorrMeas[i] += in ar9003_hw_iqcal_collect()
188 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
189 ath_dbg(ath9k_hw_common(ah), CALIBRATE, in ar9003_hw_iqcal_collect()
191 ah->cal_samples, i, ah->totalPowerMeasI[i], in ar9003_hw_iqcal_collect()
192 ah->totalPowerMeasQ[i], in ar9003_hw_iqcal_collect()
193 ah->totalIqCorrMeas[i]); in ar9003_hw_iqcal_collect()
198 static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) in ar9003_hw_iqcalibrate() argument
200 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_iqcalibrate()
212 powerMeasI = ah->totalPowerMeasI[i]; in ar9003_hw_iqcalibrate()
213 powerMeasQ = ah->totalPowerMeasQ[i]; in ar9003_hw_iqcalibrate()
214 iqCorrMeas = ah->totalIqCorrMeas[i]; in ar9003_hw_iqcalibrate()
221 i, ah->totalIqCorrMeas[i]); in ar9003_hw_iqcalibrate()
272 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
274 if (AR_SREV_9565(ah) && in ar9003_hw_iqcalibrate()
279 REG_RMW_FIELD(ah, offset_array[i], in ar9003_hw_iqcalibrate()
282 REG_RMW_FIELD(ah, offset_array[i], in ar9003_hw_iqcalibrate()
289 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
294 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
301 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
307 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
318 static void ar9003_hw_init_cal_settings(struct ath_hw *ah) in ar9003_hw_init_cal_settings() argument
320 ah->iq_caldata.calData = &iq_cal_single_sample; in ar9003_hw_init_cal_settings()
322 if (AR_SREV_9300_20_OR_LATER(ah)) { in ar9003_hw_init_cal_settings()
323 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_init_cal_settings()
324 if (AR_SREV_9485_OR_LATER(ah) && !AR_SREV_9340(ah)) in ar9003_hw_init_cal_settings()
325 ah->enabled_cals |= TX_IQ_ON_AGC_CAL; in ar9003_hw_init_cal_settings()
328 ah->supp_cals = IQ_MISMATCH_CAL; in ar9003_hw_init_cal_settings()
334 static bool ar9003_hw_dynamic_osdac_selection(struct ath_hw *ah, in ar9003_hw_dynamic_osdac_selection() argument
337 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_dynamic_osdac_selection()
350 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
352 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_dynamic_osdac_selection()
354 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
355 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
357 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
371 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
373 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_dynamic_osdac_selection()
375 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
377 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
385 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
386 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
387 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
389 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
391 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
392 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
394 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
403 REG_CLR_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
408 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
409 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8))); in ar9003_hw_dynamic_osdac_selection()
410 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
411 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8))); in ar9003_hw_dynamic_osdac_selection()
412 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
413 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8))); in ar9003_hw_dynamic_osdac_selection()
415 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); in ar9003_hw_dynamic_osdac_selection()
419 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); in ar9003_hw_dynamic_osdac_selection()
423 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); in ar9003_hw_dynamic_osdac_selection()
430 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
431 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8))); in ar9003_hw_dynamic_osdac_selection()
432 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
433 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8))); in ar9003_hw_dynamic_osdac_selection()
434 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
435 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8))); in ar9003_hw_dynamic_osdac_selection()
437 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); in ar9003_hw_dynamic_osdac_selection()
441 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); in ar9003_hw_dynamic_osdac_selection()
445 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); in ar9003_hw_dynamic_osdac_selection()
452 REG_WRITE(ah, AR_PHY_65NM_CH0_BB3, in ar9003_hw_dynamic_osdac_selection()
453 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8))); in ar9003_hw_dynamic_osdac_selection()
454 REG_WRITE(ah, AR_PHY_65NM_CH1_BB3, in ar9003_hw_dynamic_osdac_selection()
455 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8))); in ar9003_hw_dynamic_osdac_selection()
456 REG_WRITE(ah, AR_PHY_65NM_CH2_BB3, in ar9003_hw_dynamic_osdac_selection()
457 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8))); in ar9003_hw_dynamic_osdac_selection()
459 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); in ar9003_hw_dynamic_osdac_selection()
463 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); in ar9003_hw_dynamic_osdac_selection()
467 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); in ar9003_hw_dynamic_osdac_selection()
482 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff; in ar9003_hw_dynamic_osdac_selection()
484 REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, val); in ar9003_hw_dynamic_osdac_selection()
503 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff; in ar9003_hw_dynamic_osdac_selection()
505 REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, val); in ar9003_hw_dynamic_osdac_selection()
524 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff; in ar9003_hw_dynamic_osdac_selection()
526 REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, val); in ar9003_hw_dynamic_osdac_selection()
535 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_dynamic_osdac_selection()
537 REG_SET_BIT(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_dynamic_osdac_selection()
543 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_dynamic_osdac_selection()
552 static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah, in ar9003_hw_solve_iq_cal() argument
568 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_solve_iq_cal()
600 static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im) in ar9003_hw_find_mag_approx() argument
619 static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, in ar9003_hw_calc_iq_corr() argument
638 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_calc_iq_corr()
740 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1); in ar9003_hw_calc_iq_corr()
741 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); in ar9003_hw_calc_iq_corr()
756 if (!ar9003_hw_solve_iq_cal(ah, in ar9003_hw_calc_iq_corr()
889 static void ar9003_hw_tx_iq_cal_outlier_detection(struct ath_hw *ah, in ar9003_hw_tx_iq_cal_outlier_detection() argument
896 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_tx_iq_cal_outlier_detection()
902 if (!AR_SREV_9485(ah)) { in ar9003_hw_tx_iq_cal_outlier_detection()
915 if (!(ah->txchainmask & (1 << i))) in ar9003_hw_tx_iq_cal_outlier_detection()
917 nmeasurement = REG_READ_FIELD(ah, in ar9003_hw_tx_iq_cal_outlier_detection()
927 if (!AR_SREV_9550(ah)) { in ar9003_hw_tx_iq_cal_outlier_detection()
950 REG_RMW_FIELD(ah, tx_corr_coeff[im][i], in ar9003_hw_tx_iq_cal_outlier_detection()
954 REG_RMW_FIELD(ah, tx_corr_coeff[im][i], in ar9003_hw_tx_iq_cal_outlier_detection()
966 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, in ar9003_hw_tx_iq_cal_outlier_detection()
968 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_tx_iq_cal_outlier_detection()
981 static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah) in ar9003_hw_tx_iq_cal_run() argument
983 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_tx_iq_cal_run()
986 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN, in ar9003_hw_tx_iq_cal_run()
989 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN, in ar9003_hw_tx_iq_cal_run()
992 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START, in ar9003_hw_tx_iq_cal_run()
995 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, in ar9003_hw_tx_iq_cal_run()
1004 static void __ar955x_tx_iq_cal_sort(struct ath_hw *ah, in __ar955x_tx_iq_cal_sort() argument
1008 struct ath_common *common = ath9k_hw_common(ah); in __ar955x_tx_iq_cal_sort()
1041 static bool ar955x_tx_iq_cal_median(struct ath_hw *ah, in ar955x_tx_iq_cal_median() argument
1052 __ar955x_tx_iq_cal_sort(ah, coeff, i, nmeasurement); in ar955x_tx_iq_cal_median()
1058 static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah, in ar9003_hw_tx_iq_cal_post_proc() argument
1062 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_tx_iq_cal_post_proc()
1080 if (!(ah->txchainmask & (1 << i))) in ar9003_hw_tx_iq_cal_post_proc()
1083 nmeasurement = REG_READ_FIELD(ah, in ar9003_hw_tx_iq_cal_post_proc()
1093 if (REG_READ(ah, txiqcal_status[i]) & in ar9003_hw_tx_iq_cal_post_proc()
1103 REG_RMW_FIELD(ah, in ar9003_hw_tx_iq_cal_post_proc()
1109 iq_res[idx] = REG_READ(ah, in ar9003_hw_tx_iq_cal_post_proc()
1113 REG_RMW_FIELD(ah, in ar9003_hw_tx_iq_cal_post_proc()
1119 iq_res[idx + 1] = 0xffff & REG_READ(ah, in ar9003_hw_tx_iq_cal_post_proc()
1128 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, in ar9003_hw_tx_iq_cal_post_proc()
1147 if (AR_SREV_9550(ah)) in ar9003_hw_tx_iq_cal_post_proc()
1148 outlier_detect = ar955x_tx_iq_cal_median(ah, &coeff, in ar9003_hw_tx_iq_cal_post_proc()
1151 ar9003_hw_tx_iq_cal_outlier_detection(ah, &coeff, is_reusable); in ar9003_hw_tx_iq_cal_post_proc()
1160 static void ar9003_hw_tx_iq_cal_reload(struct ath_hw *ah) in ar9003_hw_tx_iq_cal_reload() argument
1162 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_tx_iq_cal_reload()
1170 if (!AR_SREV_9485(ah)) { in ar9003_hw_tx_iq_cal_reload()
1182 if (!(ah->txchainmask & (1 << i))) in ar9003_hw_tx_iq_cal_reload()
1187 REG_RMW_FIELD(ah, tx_corr_coeff[im][i], in ar9003_hw_tx_iq_cal_reload()
1191 REG_RMW_FIELD(ah, tx_corr_coeff[im][i], in ar9003_hw_tx_iq_cal_reload()
1197 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, in ar9003_hw_tx_iq_cal_reload()
1199 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_tx_iq_cal_reload()
1203 static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g) in ar9003_hw_manual_peak_cal() argument
1208 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) in ar9003_hw_manual_peak_cal()
1216 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), in ar9003_hw_manual_peak_cal()
1218 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), in ar9003_hw_manual_peak_cal()
1221 if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9330_11(ah)) { in ar9003_hw_manual_peak_cal()
1223 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), in ar9003_hw_manual_peak_cal()
1226 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), in ar9003_hw_manual_peak_cal()
1233 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain), in ar9003_hw_manual_peak_cal()
1235 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain), in ar9003_hw_manual_peak_cal()
1241 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1243 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1245 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1248 if (AR_SREV_9330_11(ah)) in ar9003_hw_manual_peak_cal()
1249 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1252 if (AR_SREV_9003_PCOEM(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) { in ar9003_hw_manual_peak_cal()
1254 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1258 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1268 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1272 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1276 agc_out = REG_READ_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1283 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1286 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1292 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_GAINSTAGES(chain), in ar9003_hw_manual_peak_cal()
1297 REG_RMW_FIELD(ah, AR_PHY_65NM_RXTX2(chain), in ar9003_hw_manual_peak_cal()
1302 REG_RMW_FIELD(ah, AR_PHY_65NM_RXRF_AGC(chain), in ar9003_hw_manual_peak_cal()
1306 static void ar9003_hw_do_pcoem_manual_peak_cal(struct ath_hw *ah, in ar9003_hw_do_pcoem_manual_peak_cal() argument
1310 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_do_pcoem_manual_peak_cal()
1313 if (!AR_SREV_9462(ah) && !AR_SREV_9565(ah) && !AR_SREV_9485(ah)) in ar9003_hw_do_pcoem_manual_peak_cal()
1316 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && !run_rtt_cal) in ar9003_hw_do_pcoem_manual_peak_cal()
1320 if (!(ah->rxchainmask & (1 << i))) in ar9003_hw_do_pcoem_manual_peak_cal()
1322 ar9003_hw_manual_peak_cal(ah, i, IS_CHAN_2GHZ(chan)); in ar9003_hw_do_pcoem_manual_peak_cal()
1328 if ((ah->caps.hw_caps & ATH9K_HW_CAP_RTT) && caldata) { in ar9003_hw_do_pcoem_manual_peak_cal()
1330 caldata->caldac[0] = REG_READ_FIELD(ah, in ar9003_hw_do_pcoem_manual_peak_cal()
1333 caldata->caldac[1] = REG_READ_FIELD(ah, in ar9003_hw_do_pcoem_manual_peak_cal()
1337 caldata->caldac[0] = REG_READ_FIELD(ah, in ar9003_hw_do_pcoem_manual_peak_cal()
1340 caldata->caldac[1] = REG_READ_FIELD(ah, in ar9003_hw_do_pcoem_manual_peak_cal()
1347 static void ar9003_hw_cl_cal_post_proc(struct ath_hw *ah, bool is_reusable) in ar9003_hw_cl_cal_post_proc() argument
1352 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_cl_cal_post_proc()
1356 if (!caldata || !(ah->enabled_cals & TX_CL_CAL)) in ar9003_hw_cl_cal_post_proc()
1359 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & in ar9003_hw_cl_cal_post_proc()
1364 if (!(ah->txchainmask & (1 << i))) in ar9003_hw_cl_cal_post_proc()
1367 REG_WRITE(ah, CL_TAB_ENTRY(cl_idx[i]), in ar9003_hw_cl_cal_post_proc()
1372 if (!(ah->txchainmask & (1 << i))) in ar9003_hw_cl_cal_post_proc()
1376 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i])); in ar9003_hw_cl_cal_post_proc()
1382 static bool ar9003_hw_init_cal_pcoem(struct ath_hw *ah, in ar9003_hw_init_cal_pcoem() argument
1385 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_init_cal_pcoem()
1386 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_init_cal_pcoem()
1390 bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); in ar9003_hw_init_cal_pcoem()
1397 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask); in ar9003_hw_init_cal_pcoem()
1400 if (!ar9003_hw_rtt_restore(ah, chan)) in ar9003_hw_init_cal_pcoem()
1410 ar9003_hw_rtt_enable(ah); in ar9003_hw_init_cal_pcoem()
1411 ar9003_hw_rtt_set_mask(ah, 0x00); in ar9003_hw_init_cal_pcoem()
1412 ar9003_hw_rtt_clear_hist(ah); in ar9003_hw_init_cal_pcoem()
1417 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL); in ar9003_hw_init_cal_pcoem()
1422 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl); in ar9003_hw_init_cal_pcoem()
1424 if (ah->ah_flags & AH_FASTCC) in ar9003_hw_init_cal_pcoem()
1429 if (ah->enabled_cals & TX_CL_CAL) { in ar9003_hw_init_cal_pcoem()
1431 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem()
1434 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal_pcoem()
1441 !(ah->enabled_cals & TX_IQ_CAL)) in ar9003_hw_init_cal_pcoem()
1445 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1, in ar9003_hw_init_cal_pcoem()
1453 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) { in ar9003_hw_init_cal_pcoem()
1455 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal_pcoem()
1458 REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal_pcoem()
1464 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal) in ar9003_hw_init_cal_pcoem()
1465 ar9003_mci_init_cal_req(ah, &is_reusable); in ar9003_hw_init_cal_pcoem()
1467 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { in ar9003_hw_init_cal_pcoem()
1468 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY); in ar9003_hw_init_cal_pcoem()
1470 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_init_cal_pcoem()
1472 REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY); in ar9003_hw_init_cal_pcoem()
1473 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_cal_pcoem()
1476 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { in ar9003_hw_init_cal_pcoem()
1478 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_init_cal_pcoem()
1479 REG_READ(ah, AR_PHY_AGC_CONTROL) | in ar9003_hw_init_cal_pcoem()
1483 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_init_cal_pcoem()
1487 ar9003_hw_do_pcoem_manual_peak_cal(ah, chan, run_rtt_cal); in ar9003_hw_init_cal_pcoem()
1490 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { in ar9003_hw_init_cal_pcoem()
1491 REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay); in ar9003_hw_init_cal_pcoem()
1495 if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal) in ar9003_hw_init_cal_pcoem()
1496 ar9003_mci_init_cal_done(ah); in ar9003_hw_init_cal_pcoem()
1500 REG_WRITE(ah, AR_PHY_AGC_CONTROL, agc_ctrl); in ar9003_hw_init_cal_pcoem()
1505 ar9003_hw_rtt_disable(ah); in ar9003_hw_init_cal_pcoem()
1514 ar9003_hw_tx_iq_cal_post_proc(ah, 0, is_reusable); in ar9003_hw_init_cal_pcoem()
1516 ar9003_hw_tx_iq_cal_reload(ah); in ar9003_hw_init_cal_pcoem()
1518 ar9003_hw_cl_cal_post_proc(ah, is_reusable); in ar9003_hw_init_cal_pcoem()
1522 if (!ath9k_hw_rfbus_req(ah)) { in ar9003_hw_init_cal_pcoem()
1523 ath_err(ath9k_hw_common(ah), in ar9003_hw_init_cal_pcoem()
1526 ar9003_hw_rtt_fill_hist(ah); in ar9003_hw_init_cal_pcoem()
1529 ar9003_hw_rtt_load_hist(ah); in ar9003_hw_init_cal_pcoem()
1532 ath9k_hw_rfbus_done(ah); in ar9003_hw_init_cal_pcoem()
1535 ar9003_hw_rtt_disable(ah); in ar9003_hw_init_cal_pcoem()
1539 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_init_cal_pcoem()
1542 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9003_hw_init_cal_pcoem()
1544 INIT_CAL(&ah->iq_caldata); in ar9003_hw_init_cal_pcoem()
1545 INSERT_CAL(ah, &ah->iq_caldata); in ar9003_hw_init_cal_pcoem()
1549 ah->cal_list_curr = ah->cal_list; in ar9003_hw_init_cal_pcoem()
1551 if (ah->cal_list_curr) in ar9003_hw_init_cal_pcoem()
1552 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); in ar9003_hw_init_cal_pcoem()
1560 static bool do_ar9003_agc_cal(struct ath_hw *ah) in do_ar9003_agc_cal() argument
1562 struct ath_common *common = ath9k_hw_common(ah); in do_ar9003_agc_cal()
1565 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in do_ar9003_agc_cal()
1566 REG_READ(ah, AR_PHY_AGC_CONTROL) | in do_ar9003_agc_cal()
1569 status = ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, in do_ar9003_agc_cal()
1583 static bool ar9003_hw_init_cal_soc(struct ath_hw *ah, in ar9003_hw_init_cal_soc() argument
1586 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_init_cal_soc()
1587 struct ath9k_hw_cal_data *caldata = ah->caldata; in ar9003_hw_init_cal_soc()
1594 ar9003_hw_set_chain_masks(ah, ah->caps.rx_chainmask, ah->caps.tx_chainmask); in ar9003_hw_init_cal_soc()
1596 if (ah->enabled_cals & TX_CL_CAL) { in ar9003_hw_init_cal_soc()
1597 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9003_hw_init_cal_soc()
1605 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1, in ar9003_hw_init_cal_soc()
1613 if (ah->enabled_cals & TX_IQ_ON_AGC_CAL) { in ar9003_hw_init_cal_soc()
1614 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal_soc()
1630 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah); in ar9003_hw_init_cal_soc()
1631 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_init_cal_soc()
1633 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_cal_soc()
1636 if (AR_SREV_9550(ah) && IS_CHAN_2GHZ(chan)) { in ar9003_hw_init_cal_soc()
1637 if (!ar9003_hw_dynamic_osdac_selection(ah, txiqcal_done)) in ar9003_hw_init_cal_soc()
1642 if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { in ar9003_hw_init_cal_soc()
1643 if (AR_SREV_9330_11(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { in ar9003_hw_init_cal_soc()
1645 if (!(ah->rxchainmask & (1 << i))) in ar9003_hw_init_cal_soc()
1647 ar9003_hw_manual_peak_cal(ah, i, in ar9003_hw_init_cal_soc()
1660 if (!AR_SREV_9550(ah)) { in ar9003_hw_init_cal_soc()
1661 status = do_ar9003_agc_cal(ah); in ar9003_hw_init_cal_soc()
1666 ar9003_hw_tx_iq_cal_post_proc(ah, 0, false); in ar9003_hw_init_cal_soc()
1669 status = do_ar9003_agc_cal(ah); in ar9003_hw_init_cal_soc()
1674 status = do_ar9003_agc_cal(ah); in ar9003_hw_init_cal_soc()
1677 ar9003_hw_tx_iq_cal_post_proc(ah, i, false); in ar9003_hw_init_cal_soc()
1684 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_init_cal_soc()
1687 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; in ar9003_hw_init_cal_soc()
1689 INIT_CAL(&ah->iq_caldata); in ar9003_hw_init_cal_soc()
1690 INSERT_CAL(ah, &ah->iq_caldata); in ar9003_hw_init_cal_soc()
1694 ah->cal_list_curr = ah->cal_list; in ar9003_hw_init_cal_soc()
1696 if (ah->cal_list_curr) in ar9003_hw_init_cal_soc()
1697 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); in ar9003_hw_init_cal_soc()
1705 void ar9003_hw_attach_calib_ops(struct ath_hw *ah) in ar9003_hw_attach_calib_ops() argument
1707 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_calib_ops()
1708 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_calib_ops()
1710 if (AR_SREV_9485(ah) || AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_attach_calib_ops()