Lines Matching refs:ah
2959 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah) in ath9k_hw_ar9300_check_eeprom() argument
2974 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, in ath9k_hw_ar9300_get_eeprom() argument
2977 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_get_eeprom()
3004 if (AR_SREV_9565(ah)) in ath9k_hw_ar9300_get_eeprom()
3017 static bool ar9300_eeprom_read_byte(struct ath_hw *ah, int address, in ar9300_eeprom_read_byte() argument
3022 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) in ar9300_eeprom_read_byte()
3029 static bool ar9300_eeprom_read_word(struct ath_hw *ah, int address, in ar9300_eeprom_read_word() argument
3034 if (unlikely(!ath9k_hw_nvram_read(ah, address / 2, &val))) in ar9300_eeprom_read_word()
3043 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer, in ar9300_read_eeprom() argument
3046 struct ath_common *common = ath9k_hw_common(ah); in ar9300_read_eeprom()
3060 if (!ar9300_eeprom_read_byte(ah, address--, buffer++)) in ar9300_read_eeprom()
3067 if (!ar9300_eeprom_read_word(ah, address, buffer)) in ar9300_read_eeprom()
3075 if (!ar9300_eeprom_read_byte(ah, address, buffer)) in ar9300_read_eeprom()
3086 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data) in ar9300_otp_read_word() argument
3088 REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); in ar9300_otp_read_word()
3090 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE, in ar9300_otp_read_word()
3094 *data = REG_READ(ah, AR9300_OTP_READ_DATA); in ar9300_otp_read_word()
3098 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer, in ar9300_read_otp() argument
3106 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data)) in ar9300_read_otp()
3144 static bool ar9300_uncompress_block(struct ath_hw *ah, in ar9300_uncompress_block() argument
3154 struct ath_common *common = ath9k_hw_common(ah); in ar9300_uncompress_block()
3181 static int ar9300_compress_decision(struct ath_hw *ah, in ar9300_compress_decision() argument
3188 struct ath_common *common = ath9k_hw_common(ah); in ar9300_compress_decision()
3219 ar9300_uncompress_block(ah, mptr, mdata_size, in ar9300_compress_decision()
3229 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3238 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read, in ar9300_check_eeprom_header() argument
3243 if (!read(ah, base_addr, header, 4)) in ar9300_check_eeprom_header()
3249 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr, in ar9300_eeprom_restore_flash() argument
3256 ath9k_hw_nvram_read(ah, i, data); in ar9300_eeprom_restore_flash()
3267 static int ar9300_eeprom_restore_internal(struct ath_hw *ah, in ar9300_eeprom_restore_internal() argument
3279 struct ath_common *common = ath9k_hw_common(ah); in ar9300_eeprom_restore_internal()
3283 if (ath9k_hw_use_flash(ah)) { in ar9300_eeprom_restore_internal()
3286 ar9300_eeprom_restore_flash(ah, mptr, mdata_size); in ar9300_eeprom_restore_internal()
3302 if (AR_SREV_9485(ah)) in ar9300_eeprom_restore_internal()
3304 else if (AR_SREV_9330(ah)) in ar9300_eeprom_restore_internal()
3310 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3316 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3322 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3327 if (ar9300_check_eeprom_header(ah, read, cptr)) in ar9300_eeprom_restore_internal()
3336 if (!read(ah, cptr, word, COMP_HDR_LEN)) in ar9300_eeprom_restore_internal()
3347 if ((!AR_SREV_9485(ah) && length >= 1024) || in ar9300_eeprom_restore_internal()
3348 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) { in ar9300_eeprom_restore_internal()
3355 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN); in ar9300_eeprom_restore_internal()
3361 ar9300_compress_decision(ah, it, code, reference, mptr, in ar9300_eeprom_restore_internal()
3383 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) in ath9k_hw_ar9300_fill_eeprom() argument
3385 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_fill_eeprom()
3387 if (ar9300_eeprom_restore_internal(ah, mptr, in ath9k_hw_ar9300_fill_eeprom()
3433 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_ar9003_dump_eeprom() argument
3436 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9003_dump_eeprom()
3453 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); in ath9k_hw_ar9003_dump_eeprom()
3496 ah->eeprom.ar9300_eep.macAddr); in ath9k_hw_ar9003_dump_eeprom()
3504 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_ar9003_dump_eeprom() argument
3512 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) in ath9k_hw_ar9300_get_eeprom_ver() argument
3514 return ah->eeprom.ar9300_eep.eepromVersion; in ath9k_hw_ar9300_get_eeprom_ver()
3518 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) in ath9k_hw_ar9300_get_eeprom_rev() argument
3523 static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, in ar9003_modal_header() argument
3526 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_modal_header()
3534 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xpa_bias_level_apply() argument
3536 int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; in ar9003_hw_xpa_bias_level_apply()
3538 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ar9003_hw_xpa_bias_level_apply()
3539 AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ar9003_hw_xpa_bias_level_apply()
3540 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3541 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) in ar9003_hw_xpa_bias_level_apply()
3542 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3544 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); in ar9003_hw_xpa_bias_level_apply()
3545 REG_RMW_FIELD(ah, AR_CH0_THERM, in ar9003_hw_xpa_bias_level_apply()
3548 REG_RMW_FIELD(ah, AR_CH0_THERM, in ar9003_hw_xpa_bias_level_apply()
3553 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) in ar9003_switch_com_spdt_get() argument
3555 return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); in ar9003_switch_com_spdt_get()
3558 u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_common_get() argument
3560 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); in ar9003_hw_ant_ctrl_common_get()
3563 u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_common_2_get() argument
3565 return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); in ar9003_hw_ant_ctrl_common_2_get()
3568 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, in ar9003_hw_ant_ctrl_chain_get() argument
3571 __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; in ar9003_hw_ant_ctrl_chain_get()
3575 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_ant_ctrl_apply() argument
3577 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ant_ctrl_apply()
3578 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_ant_ctrl_apply()
3587 if (AR_SREV_9485(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) { in ar9003_hw_ant_ctrl_apply()
3588 if (ah->config.xlna_gpio) in ar9003_hw_ant_ctrl_apply()
3589 gpio = ah->config.xlna_gpio; in ar9003_hw_ant_ctrl_apply()
3593 ath9k_hw_cfg_output(ah, gpio, in ar9003_hw_ant_ctrl_apply()
3597 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3599 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3600 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3602 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_ant_ctrl_apply()
3603 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3606 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, in ar9003_hw_ant_ctrl_apply()
3623 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3624 value = ar9003_switch_com_spdt_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3625 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL, in ar9003_hw_ant_ctrl_apply()
3627 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); in ar9003_hw_ant_ctrl_apply()
3630 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz); in ar9003_hw_ant_ctrl_apply()
3631 if (AR_SREV_9485(ah) && common->bt_ant_diversity) { in ar9003_hw_ant_ctrl_apply()
3633 value |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_ant_ctrl_apply()
3636 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value); in ar9003_hw_ant_ctrl_apply()
3638 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_ant_ctrl_apply()
3639 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz); in ar9003_hw_ant_ctrl_apply()
3640 REG_RMW_FIELD(ah, switch_chain_reg[0], in ar9003_hw_ant_ctrl_apply()
3645 if ((ah->rxchainmask & BIT(chain)) || in ar9003_hw_ant_ctrl_apply()
3646 (ah->txchainmask & BIT(chain))) { in ar9003_hw_ant_ctrl_apply()
3647 value = ar9003_hw_ant_ctrl_chain_get(ah, chain, in ar9003_hw_ant_ctrl_apply()
3649 REG_RMW_FIELD(ah, switch_chain_reg[chain], in ar9003_hw_ant_ctrl_apply()
3654 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3655 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_ant_ctrl_apply()
3660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3667 if (AR_SREV_9485(ah) && common->bt_ant_diversity) in ar9003_hw_ant_ctrl_apply()
3670 if (AR_SREV_9565(ah)) { in ar9003_hw_ant_ctrl_apply()
3674 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_ant_ctrl_apply()
3678 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()
3684 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_ant_ctrl_apply()
3688 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_ant_ctrl_apply()
3693 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3696 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_ant_ctrl_apply()
3700 if ((AR_SREV_9485(ah) || AR_SREV_9565(ah)) in ar9003_hw_ant_ctrl_apply()
3704 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_ant_ctrl_apply()
3707 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_ant_ctrl_apply()
3721 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_ant_ctrl_apply()
3726 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) in ar9003_hw_drive_strength_apply() argument
3728 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_drive_strength_apply()
3737 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); in ar9003_hw_drive_strength_apply()
3745 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg); in ar9003_hw_drive_strength_apply()
3747 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); in ar9003_hw_drive_strength_apply()
3758 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg); in ar9003_hw_drive_strength_apply()
3760 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); in ar9003_hw_drive_strength_apply()
3765 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg); in ar9003_hw_drive_strength_apply()
3768 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, in ar9003_hw_atten_chain_get() argument
3773 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get()
3796 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, in ar9003_hw_atten_chain_get_margin() argument
3801 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_atten_chain_get_margin()
3823 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_atten_apply() argument
3832 if ((AR_SREV_9462(ah)) && (ah->rxchainmask == 0x2)) { in ar9003_hw_atten_apply()
3833 value = ar9003_hw_atten_chain_get(ah, 1, chan); in ar9003_hw_atten_apply()
3834 REG_RMW_FIELD(ah, ext_atten_reg[0], in ar9003_hw_atten_apply()
3837 value = ar9003_hw_atten_chain_get_margin(ah, 1, chan); in ar9003_hw_atten_apply()
3838 REG_RMW_FIELD(ah, ext_atten_reg[0], in ar9003_hw_atten_apply()
3845 if (ah->txchainmask & BIT(i)) { in ar9003_hw_atten_apply()
3846 value = ar9003_hw_atten_chain_get(ah, i, chan); in ar9003_hw_atten_apply()
3847 REG_RMW_FIELD(ah, ext_atten_reg[i], in ar9003_hw_atten_apply()
3850 if (AR_SREV_9485(ah) && in ar9003_hw_atten_apply()
3851 (ar9003_hw_get_rx_gain_idx(ah) == 0) && in ar9003_hw_atten_apply()
3852 ah->config.xatten_margin_cfg) in ar9003_hw_atten_apply()
3855 value = ar9003_hw_atten_chain_get_margin(ah, i, chan); in ar9003_hw_atten_apply()
3857 if (ah->config.alt_mingainidx) in ar9003_hw_atten_apply()
3858 REG_RMW_FIELD(ah, AR_PHY_EXT_ATTEN_CTL_0, in ar9003_hw_atten_apply()
3862 REG_RMW_FIELD(ah, ext_atten_reg[i], in ar9003_hw_atten_apply()
3869 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) in is_pmu_set() argument
3873 while (pmu_set != REG_READ(ah, pmu_reg)) { in is_pmu_set()
3876 REG_WRITE(ah, pmu_reg, pmu_set); in is_pmu_set()
3883 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) in ar9003_hw_internal_regulator_apply() argument
3885 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_internal_regulator_apply()
3890 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { in ar9003_hw_internal_regulator_apply()
3893 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; in ar9003_hw_internal_regulator_apply()
3894 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3895 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3898 if (AR_SREV_9330(ah)) { in ar9003_hw_internal_regulator_apply()
3899 if (ah->is_clk_25mhz) { in ar9003_hw_internal_regulator_apply()
3917 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3918 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3921 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) in ar9003_hw_internal_regulator_apply()
3923 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3924 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3927 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) in ar9003_hw_internal_regulator_apply()
3929 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set); in ar9003_hw_internal_regulator_apply()
3930 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) in ar9003_hw_internal_regulator_apply()
3932 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || in ar9003_hw_internal_regulator_apply()
3933 AR_SREV_9561(ah)) { in ar9003_hw_internal_regulator_apply()
3935 REG_WRITE(ah, AR_PHY_PMU1, reg_val); in ar9003_hw_internal_regulator_apply()
3937 if (AR_SREV_9561(ah)) in ar9003_hw_internal_regulator_apply()
3938 REG_WRITE(ah, AR_PHY_PMU2, 0x10200000); in ar9003_hw_internal_regulator_apply()
3942 REG_WRITE(ah, AR_RTC_REG_CONTROL1, in ar9003_hw_internal_regulator_apply()
3943 REG_READ(ah, AR_RTC_REG_CONTROL1) & in ar9003_hw_internal_regulator_apply()
3945 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val); in ar9003_hw_internal_regulator_apply()
3947 REG_WRITE(ah, AR_RTC_REG_CONTROL1, in ar9003_hw_internal_regulator_apply()
3948 REG_READ(ah, in ar9003_hw_internal_regulator_apply()
3953 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) { in ar9003_hw_internal_regulator_apply()
3954 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0); in ar9003_hw_internal_regulator_apply()
3955 while (REG_READ_FIELD(ah, AR_PHY_PMU2, in ar9003_hw_internal_regulator_apply()
3959 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); in ar9003_hw_internal_regulator_apply()
3960 while (!REG_READ_FIELD(ah, AR_PHY_PMU1, in ar9003_hw_internal_regulator_apply()
3963 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1); in ar9003_hw_internal_regulator_apply()
3964 while (!REG_READ_FIELD(ah, AR_PHY_PMU2, in ar9003_hw_internal_regulator_apply()
3967 } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_internal_regulator_apply()
3968 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1); in ar9003_hw_internal_regulator_apply()
3970 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | in ar9003_hw_internal_regulator_apply()
3972 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val); in ar9003_hw_internal_regulator_apply()
3978 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) in ar9003_hw_apply_tuning_caps() argument
3980 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_tuning_caps()
3983 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) in ar9003_hw_apply_tuning_caps()
3988 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, in ar9003_hw_apply_tuning_caps()
3990 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC, in ar9003_hw_apply_tuning_caps()
3995 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) in ar9003_hw_quick_drop_apply() argument
3997 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_quick_drop_apply()
4005 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) { in ar9003_hw_quick_drop_apply()
4014 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); in ar9003_hw_quick_drop_apply()
4018 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_txend_to_xpa_off_apply() argument
4022 value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; in ar9003_hw_txend_to_xpa_off_apply()
4024 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_txend_to_xpa_off_apply()
4026 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_txend_to_xpa_off_apply()
4030 static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xpa_timing_control_apply() argument
4032 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xpa_timing_control_apply()
4038 if (!AR_SREV_9300(ah) && in ar9003_hw_xpa_timing_control_apply()
4039 !AR_SREV_9340(ah) && in ar9003_hw_xpa_timing_control_apply()
4040 !AR_SREV_9580(ah) && in ar9003_hw_xpa_timing_control_apply()
4041 !AR_SREV_9531(ah) && in ar9003_hw_xpa_timing_control_apply()
4042 !AR_SREV_9561(ah)) in ar9003_hw_xpa_timing_control_apply()
4045 xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; in ar9003_hw_xpa_timing_control_apply()
4047 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_xpa_timing_control_apply()
4050 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, in ar9003_hw_xpa_timing_control_apply()
4054 static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) in ar9003_hw_xlna_bias_strength_apply() argument
4056 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_xlna_bias_strength_apply()
4062 if (!AR_SREV_9300(ah)) in ar9003_hw_xlna_bias_strength_apply()
4065 bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; in ar9003_hw_xlna_bias_strength_apply()
4066 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4069 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4072 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, in ar9003_hw_xlna_bias_strength_apply()
4076 static int ar9003_hw_get_thermometer(struct ath_hw *ah) in ar9003_hw_get_thermometer() argument
4078 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_thermometer()
4085 static void ar9003_hw_thermometer_apply(struct ath_hw *ah) in ar9003_hw_thermometer_apply() argument
4087 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_thermometer_apply()
4088 int thermometer = ar9003_hw_get_thermometer(ah); in ar9003_hw_thermometer_apply()
4091 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, in ar9003_hw_thermometer_apply()
4094 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, in ar9003_hw_thermometer_apply()
4097 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, in ar9003_hw_thermometer_apply()
4101 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, in ar9003_hw_thermometer_apply()
4105 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, in ar9003_hw_thermometer_apply()
4110 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, in ar9003_hw_thermometer_apply()
4115 static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) in ar9003_hw_thermo_cal_apply() argument
4119 if (!AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_thermo_cal_apply()
4122 ar9300_otp_read_word(ah, 1, &data); in ar9003_hw_thermo_cal_apply()
4126 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, in ar9003_hw_thermo_cal_apply()
4128 REG_RMW_FIELD(ah, AR_PHY_BB_THERM_ADC_3, in ar9003_hw_thermo_cal_apply()
4134 static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, in ar9003_hw_apply_minccapwr_thresh() argument
4137 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_apply_minccapwr_thresh()
4155 if (!(ah->caps.tx_chainmask & BIT(chain))) in ar9003_hw_apply_minccapwr_thresh()
4158 val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; in ar9003_hw_apply_minccapwr_thresh()
4159 REG_RMW_FIELD(ah, cca_ctrl[chain], in ar9003_hw_apply_minccapwr_thresh()
4165 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah, in ath9k_hw_ar9300_set_board_values() argument
4169 ar9003_hw_xpa_timing_control_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4170 ar9003_hw_xpa_bias_level_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4171 ar9003_hw_ant_ctrl_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4172 ar9003_hw_drive_strength_apply(ah); in ath9k_hw_ar9300_set_board_values()
4173 ar9003_hw_xlna_bias_strength_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4174 ar9003_hw_atten_apply(ah, chan); in ath9k_hw_ar9300_set_board_values()
4175 ar9003_hw_quick_drop_apply(ah, chan->channel); in ath9k_hw_ar9300_set_board_values()
4176 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9531(ah)) in ath9k_hw_ar9300_set_board_values()
4177 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_ar9300_set_board_values()
4178 ar9003_hw_apply_tuning_caps(ah); in ath9k_hw_ar9300_set_board_values()
4179 ar9003_hw_apply_minccapwr_thresh(ah, chan); in ath9k_hw_ar9300_set_board_values()
4180 ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz); in ath9k_hw_ar9300_set_board_values()
4181 ar9003_hw_thermometer_apply(ah); in ath9k_hw_ar9300_set_board_values()
4182 ar9003_hw_thermo_cal_apply(ah); in ath9k_hw_ar9300_set_board_values()
4185 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah, in ath9k_hw_ar9300_set_addac() argument
4253 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_tgt_pwr() argument
4259 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_tgt_pwr()
4288 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_ht20_tgt_pwr() argument
4295 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht20_tgt_pwr()
4324 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_ht40_tgt_pwr() argument
4331 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_ht40_tgt_pwr()
4360 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, in ar9003_hw_eeprom_get_cck_tgt_pwr() argument
4366 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_eeprom_get_cck_tgt_pwr()
4385 static void ar9003_hw_selfgen_tpc_txpower(struct ath_hw *ah, in ar9003_hw_selfgen_tpc_txpower() argument
4401 REG_WRITE(ah, AR_TPC, val); in ar9003_hw_selfgen_tpc_txpower()
4405 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray) in ar9003_hw_tx_power_regwrite() argument
4409 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0); in ar9003_hw_tx_power_regwrite()
4414 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0), in ar9003_hw_tx_power_regwrite()
4421 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1), in ar9003_hw_tx_power_regwrite()
4430 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2), in ar9003_hw_tx_power_regwrite()
4437 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3), in ar9003_hw_tx_power_regwrite()
4447 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8), in ar9003_hw_tx_power_regwrite()
4457 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4), in ar9003_hw_tx_power_regwrite()
4465 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5), in ar9003_hw_tx_power_regwrite()
4473 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9), in ar9003_hw_tx_power_regwrite()
4483 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10), in ar9003_hw_tx_power_regwrite()
4495 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6), in ar9003_hw_tx_power_regwrite()
4503 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7), in ar9003_hw_tx_power_regwrite()
4511 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11), in ar9003_hw_tx_power_regwrite()
4522 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_legacy_target_powers() argument
4527 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq, in ar9003_hw_get_legacy_target_powers()
4530 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq, in ar9003_hw_get_legacy_target_powers()
4533 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq, in ar9003_hw_get_legacy_target_powers()
4536 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq, in ar9003_hw_get_legacy_target_powers()
4540 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_cck_target_powers() argument
4544 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L, in ar9003_hw_get_cck_target_powers()
4547 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq); in ar9003_hw_get_cck_target_powers()
4549 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq); in ar9003_hw_get_cck_target_powers()
4551 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq); in ar9003_hw_get_cck_target_powers()
4554 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq, in ar9003_hw_get_ht20_target_powers() argument
4558 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, in ar9003_hw_get_ht20_target_powers()
4561 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, in ar9003_hw_get_ht20_target_powers()
4564 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq, in ar9003_hw_get_ht20_target_powers()
4567 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq, in ar9003_hw_get_ht20_target_powers()
4570 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq, in ar9003_hw_get_ht20_target_powers()
4573 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq, in ar9003_hw_get_ht20_target_powers()
4576 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq, in ar9003_hw_get_ht20_target_powers()
4579 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq, in ar9003_hw_get_ht20_target_powers()
4582 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq, in ar9003_hw_get_ht20_target_powers()
4585 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq, in ar9003_hw_get_ht20_target_powers()
4588 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq, in ar9003_hw_get_ht20_target_powers()
4591 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq, in ar9003_hw_get_ht20_target_powers()
4594 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq, in ar9003_hw_get_ht20_target_powers()
4597 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq, in ar9003_hw_get_ht20_target_powers()
4601 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah, in ar9003_hw_get_ht40_target_powers() argument
4610 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq, in ar9003_hw_get_ht40_target_powers()
4613 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19, in ar9003_hw_get_ht40_target_powers()
4617 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq, in ar9003_hw_get_ht40_target_powers()
4620 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq, in ar9003_hw_get_ht40_target_powers()
4623 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq, in ar9003_hw_get_ht40_target_powers()
4626 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq, in ar9003_hw_get_ht40_target_powers()
4629 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq, in ar9003_hw_get_ht40_target_powers()
4632 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq, in ar9003_hw_get_ht40_target_powers()
4635 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq, in ar9003_hw_get_ht40_target_powers()
4638 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq, in ar9003_hw_get_ht40_target_powers()
4641 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq, in ar9003_hw_get_ht40_target_powers()
4644 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq, in ar9003_hw_get_ht40_target_powers()
4647 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq, in ar9003_hw_get_ht40_target_powers()
4650 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq, in ar9003_hw_get_ht40_target_powers()
4654 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah, in ar9003_hw_get_target_power_eeprom() argument
4660 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_get_target_power_eeprom()
4664 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2); in ar9003_hw_get_target_power_eeprom()
4666 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz); in ar9003_hw_get_target_power_eeprom()
4667 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz); in ar9003_hw_get_target_power_eeprom()
4670 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2, in ar9003_hw_get_target_power_eeprom()
4679 static int ar9003_hw_cal_pier_get(struct ath_hw *ah, in ar9003_hw_cal_pier_get() argument
4690 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_cal_pier_get()
4691 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_cal_pier_get()
4731 static void ar9003_hw_power_control_override(struct ath_hw *ah, in ar9003_hw_power_control_override() argument
4737 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_power_control_override()
4740 REG_RMW(ah, AR_PHY_TPC_11_B0, in ar9003_hw_power_control_override()
4743 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4744 REG_RMW(ah, AR_PHY_TPC_11_B1, in ar9003_hw_power_control_override()
4747 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4748 REG_RMW(ah, AR_PHY_TPC_11_B2, in ar9003_hw_power_control_override()
4753 REG_RMW(ah, AR_PHY_TPC_6_B0, in ar9003_hw_power_control_override()
4756 if (ah->caps.tx_chainmask & BIT(1)) in ar9003_hw_power_control_override()
4757 REG_RMW(ah, AR_PHY_TPC_6_B1, in ar9003_hw_power_control_override()
4760 if (ah->caps.tx_chainmask & BIT(2)) in ar9003_hw_power_control_override()
4761 REG_RMW(ah, AR_PHY_TPC_6_B2, in ar9003_hw_power_control_override()
4772 if (AR_SREV_9550(ah)) { in ar9003_hw_power_control_override()
4820 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_power_control_override()
4830 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4834 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4838 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4843 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4847 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4851 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4861 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4864 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4867 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, in ar9003_hw_power_control_override()
4871 REG_RMW_FIELD(ah, AR_PHY_TPC_19, in ar9003_hw_power_control_override()
4875 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_power_control_override()
4876 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, in ar9003_hw_power_control_override()
4880 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE, in ar9003_hw_power_control_override()
4885 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) in ar9003_hw_calibration_apply() argument
4899 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_calibration_apply()
4914 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain, in ar9003_hw_calibration_apply()
5014 ar9003_hw_power_control_override(ah, frequency, correction, voltage, in ar9003_hw_calibration_apply()
5112 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, in ar9003_hw_set_power_per_rate_table() argument
5118 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_set_power_per_rate_table()
5119 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; in ar9003_hw_set_power_per_rate_table()
5139 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_power_per_rate_table()
5140 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, in ar9003_hw_set_power_per_rate_table()
5265 if (ath9k_hw_mci_is_enabled(ah)) in ar9003_hw_set_power_per_rate_table()
5268 ar9003_mci_get_max_txpower(ah, in ar9003_hw_set_power_per_rate_table()
5278 if (ath9k_hw_mci_is_enabled(ah)) in ar9003_hw_set_power_per_rate_table()
5281 ar9003_mci_get_max_txpower(ah, in ar9003_hw_set_power_per_rate_table()
5301 static void ar9003_paprd_set_txpower(struct ath_hw *ah, in ar9003_paprd_set_txpower() argument
5307 if (!ar9003_is_paprd_enabled(ah)) in ar9003_paprd_set_txpower()
5316 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && in ar9003_paprd_set_txpower()
5317 !AR_SREV_9462(ah) && !AR_SREV_9565(ah)) { in ar9003_paprd_set_txpower()
5325 ah->paprd_target_power = targetPowerValT2[i]; in ar9003_paprd_set_txpower()
5328 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah, in ath9k_hw_ar9300_set_txpower() argument
5333 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_ar9300_set_txpower()
5334 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_ar9300_set_txpower()
5335 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ath9k_hw_ar9300_set_txpower()
5348 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5350 if (ar9003_is_paprd_enabled(ah)) { in ath9k_hw_ar9300_set_txpower()
5356 ah->paprd_ratemask = in ath9k_hw_ar9300_set_txpower()
5360 ah->paprd_ratemask_ht40 = in ath9k_hw_ar9300_set_txpower()
5364 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan); in ath9k_hw_ar9300_set_txpower()
5368 if (!ah->paprd_table_write_done) { in ath9k_hw_ar9300_set_txpower()
5373 if (ah->paprd_ratemask & (1 << i)) { in ath9k_hw_ar9300_set_txpower()
5386 ar9003_hw_set_power_per_rate_table(ah, chan, in ath9k_hw_ar9300_set_txpower()
5394 if (ar9003_is_paprd_enabled(ah)) { in ath9k_hw_ar9300_set_txpower()
5396 if ((ah->paprd_ratemask & (1 << i)) && in ath9k_hw_ar9300_set_txpower()
5400 ah->paprd_ratemask &= ~(1 << i); in ath9k_hw_ar9300_set_txpower()
5413 ath9k_hw_update_regulatory_maxpower(ah); in ath9k_hw_ar9300_set_txpower()
5424 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5425 ar9003_hw_calibration_apply(ah, chan->channel); in ath9k_hw_ar9300_set_txpower()
5426 ar9003_paprd_set_txpower(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5428 ar9003_hw_selfgen_tpc_txpower(ah, chan, targetPowerValT2); in ath9k_hw_ar9300_set_txpower()
5431 if (ah->tpc_enabled) { in ath9k_hw_ar9300_set_txpower()
5434 ar9003_hw_init_rate_txpower(ah, targetPowerValT2_tpc, chan); in ath9k_hw_ar9300_set_txpower()
5437 REG_WRITE(ah, AR_PHY_PWRTX_MAX, in ath9k_hw_ar9300_set_txpower()
5440 val = REG_READ(ah, AR_PHY_POWER_TX_SUB); in ath9k_hw_ar9300_set_txpower()
5441 if (AR_SREV_9340(ah)) in ath9k_hw_ar9300_set_txpower()
5442 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_ar9300_set_txpower()
5445 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_ar9300_set_txpower()
5449 REG_WRITE(ah, AR_PHY_PWRTX_MAX, 0); in ath9k_hw_ar9300_set_txpower()
5453 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, in ath9k_hw_ar9300_get_spur_channel() argument
5459 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) in ar9003_hw_get_tx_gain_idx() argument
5461 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_tx_gain_idx()
5466 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) in ar9003_hw_get_rx_gain_idx() argument
5468 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_get_rx_gain_idx()
5473 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) in ar9003_get_spur_chan_ptr() argument
5475 return ar9003_modal_header(ah, is2ghz)->spurChans; in ar9003_get_spur_chan_ptr()
5478 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, in ar9003_get_paprd_scale_factor() argument
5481 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_get_paprd_scale_factor()