Lines Matching refs:ah
148 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
155 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_channel()
159 if (AR_SREV_9330(ah)) { in ar9003_hw_set_channel()
160 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
168 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
178 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
179 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
186 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_set_channel()
187 AR_SREV_9561(ah)) { in ar9003_hw_set_channel()
188 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
202 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
203 AR_SREV_9531(ah) || AR_SREV_9561(ah)) && in ar9003_hw_set_channel()
204 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
223 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
226 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
232 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
238 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
240 ah->curchan = chan; in ar9003_hw_set_channel()
255 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, in ar9003_hw_spur_mitigate_mrc_cck() argument
262 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_mrc_cck()
269 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
270 AR_SREV_9550(ah) || AR_SREV_9561(ah)) { in ar9003_hw_spur_mitigate_mrc_cck()
276 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_mrc_cck()
286 range = AR_SREV_9462(ah) ? 5 : 10; in ar9003_hw_spur_mitigate_mrc_cck()
292 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
296 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
297 AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_spur_mitigate_mrc_cck()
316 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
318 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
320 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
323 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
326 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
334 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, in ar9003_hw_spur_mitigate_mrc_cck()
336 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
338 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
343 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) in ar9003_hw_spur_ofdm_clear() argument
345 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
347 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
349 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
351 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm_clear()
353 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
355 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
357 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
359 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
361 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
364 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
366 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
368 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
370 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
372 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
374 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
376 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
378 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
380 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm_clear()
382 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
386 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, in ar9003_hw_spur_ofdm() argument
397 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
399 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
401 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
403 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm()
405 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
408 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) in ar9003_hw_spur_ofdm()
409 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
412 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
416 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
419 if (!AR_SREV_9340(ah) && in ar9003_hw_spur_ofdm()
420 REG_READ_FIELD(ah, AR_PHY_MODE, in ar9003_hw_spur_ofdm()
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
431 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
433 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
435 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
437 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
439 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
441 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
443 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
445 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
447 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, in ar9003_hw_spur_ofdm()
449 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
453 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, in ar9003_hw_spur_ofdm_9565() argument
464 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
469 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
473 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
476 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
478 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
482 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, in ar9003_hw_spur_ofdm_9565()
486 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, in ar9003_hw_spur_ofdm_work() argument
498 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
507 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
528 ar9003_hw_spur_ofdm(ah, in ar9003_hw_spur_ofdm_work()
537 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, in ar9003_hw_spur_mitigate_ofdm() argument
546 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; in ar9003_hw_spur_mitigate_ofdm()
562 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_ofdm()
572 ar9003_hw_spur_ofdm_clear(ah); in ar9003_hw_spur_mitigate_ofdm()
578 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, in ar9003_hw_spur_mitigate_ofdm()
581 if (AR_SREV_9565(ah) && (i < 4)) { in ar9003_hw_spur_mitigate_ofdm()
586 ar9003_hw_spur_ofdm_9565(ah, freq_offset); in ar9003_hw_spur_mitigate_ofdm()
594 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, in ar9003_hw_spur_mitigate() argument
597 if (!AR_SREV_9565(ah)) in ar9003_hw_spur_mitigate()
598 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); in ar9003_hw_spur_mitigate()
599 ar9003_hw_spur_mitigate_ofdm(ah, chan); in ar9003_hw_spur_mitigate()
602 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, in ar9003_hw_compute_pll_control_soc() argument
619 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, in ar9003_hw_compute_pll_control() argument
636 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, in ar9003_hw_set_channel_regs() argument
643 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
648 if (!AR_SREV_9561(ah)) in ar9003_hw_set_channel_regs()
661 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
665 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
668 ath9k_hw_set11nmac2040(ah, chan); in ar9003_hw_set_channel_regs()
671 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
673 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
676 static void ar9003_hw_init_bb(struct ath_hw *ah, in ar9003_hw_init_bb() argument
686 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
689 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
690 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar9003_hw_init_bb()
693 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) in ar9003_hw_set_chain_masks() argument
695 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
696 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
699 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
700 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
702 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
705 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
711 static void ar9003_hw_override_ini(struct ath_hw *ah) in ar9003_hw_override_ini() argument
720 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
729 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
733 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar9003_hw_override_ini()
735 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_override_ini()
736 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, in ar9003_hw_override_ini()
739 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_override_ini()
741 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
743 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
747 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
748 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
750 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
752 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_override_ini()
753 AR_SREV_9561(ah)) { in ar9003_hw_override_ini()
754 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
755 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); in ar9003_hw_override_ini()
756 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
757 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
759 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); in ar9003_hw_override_ini()
760 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
761 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
767 static void ar9003_hw_prog_ini(struct ath_hw *ah, in ar9003_hw_prog_ini() argument
789 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
795 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9550_hw_get_modes_txgain_index() argument
820 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9561_hw_get_modes_txgain_index() argument
833 static void ar9003_doubler_fix(struct ath_hw *ah) in ar9003_doubler_fix() argument
835 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
836 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
839 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
842 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
848 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
850 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
852 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
857 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
859 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
861 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
866 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, in ar9003_doubler_fix()
869 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
872 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
875 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
881 static int ar9003_hw_process_ini(struct ath_hw *ah, in ar9003_hw_process_ini() argument
896 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
897 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
898 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
899 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
900 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_process_ini()
901 ar9003_hw_prog_ini(ah, in ar9003_hw_process_ini()
902 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
906 ar9003_doubler_fix(ah); in ar9003_hw_process_ini()
911 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
913 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_process_ini()
917 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_process_ini()
918 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
920 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
927 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || in ar9003_hw_process_ini()
928 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { in ar9003_hw_process_ini()
929 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna, in ar9003_hw_process_ini()
933 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) in ar9003_hw_process_ini()
934 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna, in ar9003_hw_process_ini()
938 if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_process_ini()
939 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
945 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_process_ini()
948 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
949 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
951 if (AR_SREV_9561(ah)) in ar9003_hw_process_ini()
953 ar9561_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
958 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
961 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
968 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_process_ini()
969 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
975 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
981 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
983 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
984 ar9003_hw_override_ini(ah); in ar9003_hw_process_ini()
985 ar9003_hw_set_channel_regs(ah, chan); in ar9003_hw_process_ini()
986 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
987 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_hw_process_ini()
992 static void ar9003_hw_set_rfmode(struct ath_hw *ah, in ar9003_hw_set_rfmode() argument
1005 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_set_rfmode()
1009 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar9003_hw_set_rfmode()
1012 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
1015 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) in ar9003_hw_mark_phy_inactive() argument
1017 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_mark_phy_inactive()
1020 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, in ar9003_hw_set_delta_slope() argument
1040 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_delta_slope()
1043 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1046 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1048 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1057 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1061 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1063 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1067 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) in ar9003_hw_rfbus_req() argument
1069 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar9003_hw_rfbus_req()
1070 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar9003_hw_rfbus_req()
1078 static void ar9003_hw_rfbus_done(struct ath_hw *ah) in ar9003_hw_rfbus_done() argument
1080 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1082 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1084 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1087 static bool ar9003_hw_ani_control(struct ath_hw *ah, in ar9003_hw_ani_control() argument
1090 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control()
1091 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1092 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1100 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1111 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_ani_control()
1135 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1138 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1141 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1144 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1147 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1150 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1153 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1156 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1159 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1162 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1167 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1170 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1181 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1183 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1209 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar9003_hw_ani_control()
1225 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar9003_hw_ani_control()
1246 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1248 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1273 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar9003_hw_ani_control()
1289 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar9003_hw_ani_control()
1310 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1312 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1324 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1327 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1329 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1337 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1339 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1361 static void ar9003_hw_do_getnf(struct ath_hw *ah, in ar9003_hw_do_getnf() argument
1373 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1374 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1378 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1381 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1389 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) in ar9003_hw_set_nf_limits() argument
1391 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1392 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1393 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1394 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1395 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1396 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1398 if (AR_SREV_9330(ah)) in ar9003_hw_set_nf_limits()
1399 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1401 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_nf_limits()
1402 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1403 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1404 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1405 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1414 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar9003_hw_ani_cache_ini_regs() argument
1417 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs()
1418 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1422 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1426 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1427 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1428 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1431 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1436 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
1441 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar9003_hw_ani_cache_ini_regs()
1446 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1449 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1452 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1455 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1466 static void ar9003_hw_set_radar_params(struct ath_hw *ah, in ar9003_hw_set_radar_params() argument
1473 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1484 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar9003_hw_set_radar_params()
1493 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar9003_hw_set_radar_params()
1494 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar9003_hw_set_radar_params()
1496 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1498 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1500 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1501 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1502 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1506 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) in ar9003_hw_set_radar_conf() argument
1508 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1520 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_get() argument
1525 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1533 if (AR_SREV_9330_11(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1537 } else if (AR_SREV_9485(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1541 } else if (AR_SREV_9565(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1552 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_set() argument
1557 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1574 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_antdiv_comb_conf_set()
1579 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9003_hw_set_bt_ant_diversity() argument
1581 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1585 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ar9003_hw_set_bt_ant_diversity()
1588 if (AR_SREV_9485(ah)) { in ar9003_hw_set_bt_ant_diversity()
1589 regval = ar9003_hw_ant_ctrl_common_2_get(ah, in ar9003_hw_set_bt_ant_diversity()
1590 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1593 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, in ar9003_hw_set_bt_ant_diversity()
1599 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1605 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1608 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1610 if (AR_SREV_9485_11_OR_LATER(ah)) { in ar9003_hw_set_bt_ant_diversity()
1614 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1620 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1625 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_set_bt_ant_diversity()
1631 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_set_bt_ant_diversity()
1634 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1647 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1649 } else if (AR_SREV_9565(ah)) { in ar9003_hw_set_bt_ant_diversity()
1651 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1653 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1655 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1657 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1659 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1662 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1664 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1666 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1668 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1670 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1673 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1682 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1689 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, in ar9003_hw_fast_chan_change() argument
1701 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; in ar9003_hw_fast_chan_change()
1703 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1708 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1709 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1710 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1711 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1713 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_fast_chan_change()
1714 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1717 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1719 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_fast_chan_change()
1723 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_fast_chan_change()
1724 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1726 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1735 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_fast_chan_change()
1736 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1738 if (AR_SREV_9565(ah)) in ar9003_hw_fast_chan_change()
1739 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1745 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1747 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1751 ar9003_hw_set_rfmode(ah, chan); in ar9003_hw_fast_chan_change()
1755 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, in ar9003_hw_spectral_scan_config() argument
1761 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1766 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1767 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
1780 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1783 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1786 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1788 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1790 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1796 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9003_hw_spectral_scan_trigger() argument
1799 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1803 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) in ar9003_hw_spectral_scan_wait() argument
1805 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait()
1808 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_wait()
1816 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9003_hw_tx99_start() argument
1818 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_start()
1819 REG_SET_BIT(ah, 0x9864, 0x7f000); in ar9003_hw_tx99_start()
1820 REG_SET_BIT(ah, 0x9924, 0x7f00fe); in ar9003_hw_tx99_start()
1821 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_start()
1822 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1823 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1824 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ in ar9003_hw_tx99_start()
1825 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9003_hw_tx99_start()
1826 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1827 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1828 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9003_hw_tx99_start()
1831 static void ar9003_hw_tx99_stop(struct ath_hw *ah) in ar9003_hw_tx99_stop() argument
1833 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); in ar9003_hw_tx99_stop()
1834 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_stop()
1837 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) in ar9003_hw_tx99_set_txpower() argument
1850 REG_WRITE(ah, 0xa458, 0); in ar9003_hw_tx99_set_txpower()
1852 REG_WRITE(ah, 0xa3c0, in ar9003_hw_tx99_set_txpower()
1857 REG_WRITE(ah, 0xa3c4, in ar9003_hw_tx99_set_txpower()
1862 REG_WRITE(ah, 0xa3c8, in ar9003_hw_tx99_set_txpower()
1866 REG_WRITE(ah, 0xa3cc, in ar9003_hw_tx99_set_txpower()
1871 REG_WRITE(ah, 0xa3d0, in ar9003_hw_tx99_set_txpower()
1876 REG_WRITE(ah, 0xa3d4, in ar9003_hw_tx99_set_txpower()
1881 REG_WRITE(ah, 0xa3e4, in ar9003_hw_tx99_set_txpower()
1886 REG_WRITE(ah, 0xa3e8, in ar9003_hw_tx99_set_txpower()
1891 REG_WRITE(ah, 0xa3d8, in ar9003_hw_tx99_set_txpower()
1896 REG_WRITE(ah, 0xa3dc, in ar9003_hw_tx99_set_txpower()
1901 REG_WRITE(ah, 0xa3ec, in ar9003_hw_tx99_set_txpower()
1908 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) in ar9003_hw_init_txpower_cck() argument
1910 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1911 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1912 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1914 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1918 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ofdm() argument
1926 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1930 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ht() argument
1939 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1945 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1951 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1956 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, in ar9003_hw_init_txpower_stbc() argument
1959 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1961 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1963 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1967 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_rate_txpower() argument
1971 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1974 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1979 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1985 ar9003_hw_init_txpower_cck(ah, rate_array); in ar9003_hw_init_rate_txpower()
1986 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1989 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1994 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
2002 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) in ar9003_hw_attach_phy_ops() argument
2004 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_phy_ops()
2005 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_phy_ops()
2018 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_attach_phy_ops()
2019 AR_SREV_9561(ah)) in ar9003_hw_attach_phy_ops()
2051 ar9003_hw_set_nf_limits(ah); in ar9003_hw_attach_phy_ops()
2052 ar9003_hw_set_radar_conf(ah); in ar9003_hw_attach_phy_ops()
2053 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
2081 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) in ar9003_hw_bb_watchdog_check() argument
2085 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2087 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2090 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2092 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2095 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2104 if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) in ar9003_hw_bb_watchdog_check()
2118 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) in ar9003_hw_bb_watchdog_config() argument
2120 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config()
2121 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2126 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2127 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & in ar9003_hw_bb_watchdog_config()
2132 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2133 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & in ar9003_hw_bb_watchdog_config()
2142 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; in ar9003_hw_bb_watchdog_config()
2143 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2161 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2168 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2177 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) in ar9003_hw_bb_watchdog_read() argument
2183 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2189 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, in ar9003_hw_bb_watchdog_read()
2190 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2193 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) in ar9003_hw_bb_watchdog_dbg_info() argument
2195 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info()
2201 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2217 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), in ar9003_hw_bb_watchdog_dbg_info()
2218 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); in ar9003_hw_bb_watchdog_dbg_info()
2220 REG_READ(ah, AR_PHY_GEN_CTRL)); in ar9003_hw_bb_watchdog_dbg_info()
2232 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) in ar9003_hw_disable_phy_restart() argument
2242 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2244 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2245 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()
2246 val = REG_READ(ah, AR_PHY_RESTART); in ar9003_hw_disable_phy_restart()
2248 REG_WRITE(ah, AR_PHY_RESTART, val); in ar9003_hw_disable_phy_restart()