Lines Matching refs:ah
21 static void ath9k_get_txgain_index(struct ath_hw *ah, in ath9k_get_txgain_index() argument
31 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_get_txgain_index()
49 while (pcdac > ah->originalGain[i] && in ath9k_get_txgain_index()
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah, in ath9k_olc_get_pdadcs() argument
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0, in ath9k_olc_get_pdadcs()
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1, in ath9k_olc_get_pdadcs()
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7, in ath9k_olc_get_pdadcs()
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah) in ath9k_hw_def_get_eeprom_ver() argument
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF); in ath9k_hw_def_get_eeprom_ver()
85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah) in ath9k_hw_def_get_eeprom_rev() argument
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF); in ath9k_hw_def_get_eeprom_rev()
92 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah) in __ath9k_hw_def_fill_eeprom() argument
94 u16 *eep_data = (u16 *)&ah->eeprom.def; in __ath9k_hw_def_fill_eeprom()
98 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, in __ath9k_hw_def_fill_eeprom()
106 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah) in __ath9k_hw_usb_def_fill_eeprom() argument
108 u16 *eep_data = (u16 *)&ah->eeprom.def; in __ath9k_hw_usb_def_fill_eeprom()
110 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, in __ath9k_hw_usb_def_fill_eeprom()
115 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah) in ath9k_hw_def_fill_eeprom() argument
117 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_def_fill_eeprom()
119 if (!ath9k_hw_use_flash(ah)) { in ath9k_hw_def_fill_eeprom()
124 return __ath9k_hw_usb_def_fill_eeprom(ah); in ath9k_hw_def_fill_eeprom()
126 return __ath9k_hw_def_fill_eeprom(ah); in ath9k_hw_def_fill_eeprom()
201 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_def_dump_eeprom() argument
204 struct ar5416_eeprom_def *eep = &ah->eeprom.def; in ath9k_hw_def_dump_eeprom()
253 static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, in ath9k_hw_def_dump_eeprom() argument
261 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah) in ath9k_hw_def_check_eeprom() argument
263 struct ar5416_eeprom_def *eep = &ah->eeprom.def; in ath9k_hw_def_check_eeprom()
264 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_def_check_eeprom()
270 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { in ath9k_hw_def_check_eeprom()
276 !(ah->ah_flags & AH_NO_EEP_SWAP)) { in ath9k_hw_def_check_eeprom()
279 eepdata = (u16 *) (&ah->eeprom); in ath9k_hw_def_check_eeprom()
292 el = swab16(ah->eeprom.def.baseEepHeader.length); in ath9k_hw_def_check_eeprom()
294 el = ah->eeprom.def.baseEepHeader.length; in ath9k_hw_def_check_eeprom()
301 eepdata = (u16 *)(&ah->eeprom); in ath9k_hw_def_check_eeprom()
359 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || in ath9k_hw_def_check_eeprom()
360 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { in ath9k_hw_def_check_eeprom()
362 sum, ah->eep_ops->get_eeprom_ver(ah)); in ath9k_hw_def_check_eeprom()
367 if ((ah->hw_version.devid == AR9280_DEVID_PCI) && in ath9k_hw_def_check_eeprom()
370 ah->need_an_top2_fixup = true; in ath9k_hw_def_check_eeprom()
373 (AR_SREV_9280(ah))) in ath9k_hw_def_check_eeprom()
379 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah, in ath9k_hw_def_get_eeprom() argument
382 struct ar5416_eeprom_def *eep = &ah->eeprom.def; in ath9k_hw_def_get_eeprom()
464 static void ath9k_hw_def_set_gain(struct ath_hw *ah, in ath9k_hw_def_set_gain() argument
469 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_def_set_gain()
473 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_def_set_gain()
474 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
477 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
480 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
483 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
487 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
490 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
496 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_def_set_gain()
497 REG_RMW_FIELD(ah, in ath9k_hw_def_set_gain()
500 REG_RMW_FIELD(ah, in ath9k_hw_def_set_gain()
504 REG_RMW(ah, AR_PHY_RXGAIN + regChainOffset, in ath9k_hw_def_set_gain()
507 REG_RMW(ah, AR_PHY_GAIN_2GHZ + regChainOffset, in ath9k_hw_def_set_gain()
511 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_def_set_gain()
514 static void ath9k_hw_def_set_board_values(struct ath_hw *ah, in ath9k_hw_def_set_board_values() argument
518 struct ar5416_eeprom_def *eep = &ah->eeprom.def; in ath9k_hw_def_set_board_values()
525 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff); in ath9k_hw_def_set_board_values()
528 if (AR_SREV_9280(ah)) { in ath9k_hw_def_set_board_values()
533 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0)) in ath9k_hw_def_set_board_values()
538 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, in ath9k_hw_def_set_board_values()
541 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
542 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_def_set_board_values()
550 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal, in ath9k_hw_def_set_board_values()
554 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_def_set_board_values()
556 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, in ath9k_hw_def_set_board_values()
560 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0, in ath9k_hw_def_set_board_values()
564 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, in ath9k_hw_def_set_board_values()
568 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1, in ath9k_hw_def_set_board_values()
573 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, in ath9k_hw_def_set_board_values()
577 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0, in ath9k_hw_def_set_board_values()
581 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, in ath9k_hw_def_set_board_values()
585 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1, in ath9k_hw_def_set_board_values()
590 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, in ath9k_hw_def_set_board_values()
594 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2, in ath9k_hw_def_set_board_values()
599 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG, in ath9k_hw_def_set_board_values()
603 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, in ath9k_hw_def_set_board_values()
605 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, in ath9k_hw_def_set_board_values()
608 if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_def_set_board_values()
609 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, in ath9k_hw_def_set_board_values()
613 REG_WRITE(ah, AR_PHY_RF_CTL4, in ath9k_hw_def_set_board_values()
622 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, in ath9k_hw_def_set_board_values()
625 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_def_set_board_values()
626 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, in ath9k_hw_def_set_board_values()
628 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, in ath9k_hw_def_set_board_values()
632 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, in ath9k_hw_def_set_board_values()
634 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ath9k_hw_def_set_board_values()
640 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, in ath9k_hw_def_set_board_values()
643 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON, in ath9k_hw_def_set_board_values()
649 REG_RMW_FIELD(ah, AR_PHY_SETTLING, in ath9k_hw_def_set_board_values()
654 if (AR_SREV_9280_20_OR_LATER(ah) && in ath9k_hw_def_set_board_values()
656 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_def_set_board_values()
661 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) { in ath9k_hw_def_set_board_values()
663 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, in ath9k_hw_def_set_board_values()
666 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0); in ath9k_hw_def_set_board_values()
668 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, in ath9k_hw_def_set_board_values()
673 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP, in ath9k_hw_def_set_board_values()
676 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9, in ath9k_hw_def_set_board_values()
682 static void ath9k_hw_def_set_addac(struct ath_hw *ah, in ath9k_hw_def_set_addac() argument
687 struct ar5416_eeprom_def *eep = &ah->eeprom.def; in ath9k_hw_def_set_addac()
690 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160) in ath9k_hw_def_set_addac()
693 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7) in ath9k_hw_def_set_addac()
704 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_def_set_addac()
727 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac, in ath9k_hw_def_set_addac()
730 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac, in ath9k_hw_def_set_addac()
736 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah, in ath9k_change_gain_boundary_setting() argument
751 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_change_gain_boundary_setting()
777 static void ath9k_adjust_pdadc_values(struct ath_hw *ah, in ath9k_adjust_pdadc_values() argument
790 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_adjust_pdadc_values()
806 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah, in ath9k_hw_set_def_power_cal_table() argument
812 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_def_power_cal_table()
813 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; in ath9k_hw_set_def_power_cal_table()
830 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET); in ath9k_hw_set_def_power_cal_table()
837 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), in ath9k_hw_set_def_power_cal_table()
851 ah->initPDADC = ((struct calDataPerFreqOpLoop *) in ath9k_hw_set_def_power_cal_table()
867 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN, in ath9k_hw_set_def_power_cal_table()
869 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1, in ath9k_hw_set_def_power_cal_table()
871 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2, in ath9k_hw_set_def_power_cal_table()
873 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, in ath9k_hw_set_def_power_cal_table()
877 if ((ah->rxchainmask == 5 || ah->txchainmask == 5) && in ath9k_hw_set_def_power_cal_table()
894 ath9k_get_txgain_index(ah, chan, in ath9k_hw_set_def_power_cal_table()
897 ath9k_olc_get_pdadcs(ah, pcdacIdx, in ath9k_hw_set_def_power_cal_table()
900 ath9k_hw_get_gain_boundaries_pdadcs(ah, in ath9k_hw_set_def_power_cal_table()
909 diff = ath9k_change_gain_boundary_setting(ah, in ath9k_hw_set_def_power_cal_table()
916 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_def_power_cal_table()
919 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
926 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
936 ath9k_adjust_pdadc_values(ah, pwr_table_offset, in ath9k_hw_set_def_power_cal_table()
942 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
957 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_def_power_cal_table()
965 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, in ath9k_hw_set_def_power_per_rate_table() argument
972 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; in ath9k_hw_set_def_power_per_rate_table()
1001 tx_chainmask = ah->txchainmask; in ath9k_hw_set_def_power_per_rate_table()
1003 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ath9k_hw_set_def_power_per_rate_table()
1005 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit, in ath9k_hw_set_def_power_per_rate_table()
1013 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1017 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1021 ath9k_hw_get_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1028 ath9k_hw_get_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1032 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1036 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1046 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1050 ath9k_hw_get_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1057 ath9k_hw_get_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1061 ath9k_hw_get_legacy_target_powers(ah, chan, in ath9k_hw_set_def_power_per_rate_table()
1188 static void ath9k_hw_def_set_txpower(struct ath_hw *ah, in ath9k_hw_def_set_txpower() argument
1195 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_def_set_txpower()
1196 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def; in ath9k_hw_def_set_txpower()
1210 ath9k_hw_set_def_power_per_rate_table(ah, chan, in ath9k_hw_def_set_txpower()
1215 ath9k_hw_set_def_power_cal_table(ah, chan); in ath9k_hw_def_set_txpower()
1225 ath9k_hw_update_regulatory_maxpower(ah); in ath9k_hw_def_set_txpower()
1230 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_def_set_txpower()
1234 pwr_table_offset = ah->eep_ops->get_eeprom(ah, in ath9k_hw_def_set_txpower()
1240 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_def_set_txpower()
1242 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, in ath9k_hw_def_set_txpower()
1247 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, in ath9k_hw_def_set_txpower()
1256 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_def_set_txpower()
1261 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_def_set_txpower()
1267 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, in ath9k_hw_def_set_txpower()
1272 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, in ath9k_hw_def_set_txpower()
1280 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, in ath9k_hw_def_set_txpower()
1285 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, in ath9k_hw_def_set_txpower()
1292 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, in ath9k_hw_def_set_txpower()
1301 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, in ath9k_hw_def_set_txpower()
1311 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, in ath9k_hw_def_set_txpower()
1317 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, in ath9k_hw_def_set_txpower()
1325 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_def_set_txpower()
1330 if (ah->tpc_enabled) { in ath9k_hw_def_set_txpower()
1334 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta); in ath9k_hw_def_set_txpower()
1336 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, in ath9k_hw_def_set_txpower()
1340 REG_WRITE(ah, AR_PHY_POWER_TX_RATE_MAX, MAX_RATE_POWER); in ath9k_hw_def_set_txpower()
1343 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_def_set_txpower()
1346 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz) in ath9k_hw_def_get_spur_channel() argument
1348 return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan; in ath9k_hw_def_get_spur_channel()