Lines Matching refs:ah
33 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
40 static void ath9k_hw_set_clockrate(struct ath_hw *ah) in ath9k_hw_set_clockrate() argument
42 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_clockrate()
43 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_clockrate()
47 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) in ath9k_hw_set_clockrate()
53 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK) in ath9k_hw_set_clockrate()
70 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) in ath9k_hw_mac_to_clks() argument
72 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_mac_to_clks()
77 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) in ath9k_hw_wait() argument
84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
90 ath_dbg(ath9k_hw_common(ah), ANY, in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
98 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_synth_delay() argument
111 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array, in ath9k_hw_write_array() argument
116 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_write_array()
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
122 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_write_array()
125 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size) in ath9k_hw_read_array() argument
132 dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__); in ath9k_hw_read_array()
138 dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__); in ath9k_hw_read_array()
145 REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size); in ath9k_hw_read_array()
167 u16 ath9k_hw_computetxtime(struct ath_hw *ah, in ath9k_hw_computetxtime() argument
186 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
193 } else if (ah->curchan && in ath9k_hw_computetxtime()
194 IS_CHAN_HALF_RATE(ah->curchan)) { in ath9k_hw_computetxtime()
210 ath_err(ath9k_hw_common(ah), in ath9k_hw_computetxtime()
220 void ath9k_hw_get_channel_centers(struct ath_hw *ah, in ath9k_hw_get_channel_centers() argument
253 static void ath9k_hw_read_revisions(struct ath_hw *ah) in ath9k_hw_read_revisions() argument
257 if (ah->get_mac_revision) in ath9k_hw_read_revisions()
258 ah->hw_version.macRev = ah->get_mac_revision(); in ath9k_hw_read_revisions()
260 switch (ah->hw_version.devid) { in ath9k_hw_read_revisions()
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100; in ath9k_hw_read_revisions()
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330; in ath9k_hw_read_revisions()
266 if (!ah->get_mac_revision) { in ath9k_hw_read_revisions()
267 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
268 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
272 ah->hw_version.macVersion = AR_SREV_VERSION_9340; in ath9k_hw_read_revisions()
275 ah->hw_version.macVersion = AR_SREV_VERSION_9550; in ath9k_hw_read_revisions()
278 ah->hw_version.macVersion = AR_SREV_VERSION_9531; in ath9k_hw_read_revisions()
281 ah->hw_version.macVersion = AR_SREV_VERSION_9561; in ath9k_hw_read_revisions()
284 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
287 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
288 ah->hw_version.macVersion = in ath9k_hw_read_revisions()
290 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); in ath9k_hw_read_revisions()
292 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_read_revisions()
293 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
295 ah->is_pciexpress = (val & in ath9k_hw_read_revisions()
298 if (!AR_SREV_9100(ah)) in ath9k_hw_read_revisions()
299 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); in ath9k_hw_read_revisions()
301 ah->hw_version.macRev = val & AR_SREV_REVISION; in ath9k_hw_read_revisions()
303 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) in ath9k_hw_read_revisions()
304 ah->is_pciexpress = true; in ath9k_hw_read_revisions()
312 static void ath9k_hw_disablepcie(struct ath_hw *ah) in ath9k_hw_disablepcie() argument
314 if (!AR_SREV_5416(ah)) in ath9k_hw_disablepcie()
317 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
318 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
319 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
320 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
321 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
322 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
323 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
324 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
325 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
327 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
331 static bool ath9k_hw_chip_test(struct ath_hw *ah) in ath9k_hw_chip_test() argument
333 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_chip_test()
341 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_chip_test()
351 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
354 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
355 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
365 REG_WRITE(ah, addr, wrData); in ath9k_hw_chip_test()
366 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
374 REG_WRITE(ah, regAddr[i], regHold[i]); in ath9k_hw_chip_test()
381 static void ath9k_hw_init_config(struct ath_hw *ah) in ath9k_hw_init_config() argument
383 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_config()
385 ah->config.dma_beacon_response_time = 1; in ath9k_hw_init_config()
386 ah->config.sw_beacon_response_time = 6; in ath9k_hw_init_config()
387 ah->config.cwm_ignore_extcca = 0; in ath9k_hw_init_config()
388 ah->config.analog_shiftreg = 1; in ath9k_hw_init_config()
390 ah->config.rx_intr_mitigation = true; in ath9k_hw_init_config()
392 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_config()
393 ah->config.rimt_last = 500; in ath9k_hw_init_config()
394 ah->config.rimt_first = 2000; in ath9k_hw_init_config()
396 ah->config.rimt_last = 250; in ath9k_hw_init_config()
397 ah->config.rimt_first = 700; in ath9k_hw_init_config()
400 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_init_config()
401 ah->config.pll_pwrsave = 7; in ath9k_hw_init_config()
420 ah->config.serialize_regmode = SER_REG_MODE_AUTO; in ath9k_hw_init_config()
422 if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) { in ath9k_hw_init_config()
423 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || in ath9k_hw_init_config()
424 ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) && in ath9k_hw_init_config()
425 !ah->is_pciexpress)) { in ath9k_hw_init_config()
426 ah->config.serialize_regmode = SER_REG_MODE_ON; in ath9k_hw_init_config()
428 ah->config.serialize_regmode = SER_REG_MODE_OFF; in ath9k_hw_init_config()
433 ah->config.serialize_regmode); in ath9k_hw_init_config()
435 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_config()
436 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; in ath9k_hw_init_config()
438 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; in ath9k_hw_init_config()
441 static void ath9k_hw_init_defaults(struct ath_hw *ah) in ath9k_hw_init_defaults() argument
443 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_init_defaults()
448 ah->hw_version.magic = AR5416_MAGIC; in ath9k_hw_init_defaults()
449 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
451 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE | in ath9k_hw_init_defaults()
453 if (AR_SREV_9100(ah)) in ath9k_hw_init_defaults()
454 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX; in ath9k_hw_init_defaults()
456 ah->slottime = ATH9K_SLOT_TIME_9; in ath9k_hw_init_defaults()
457 ah->globaltxtimeout = (u32) -1; in ath9k_hw_init_defaults()
458 ah->power_mode = ATH9K_PM_UNDEFINED; in ath9k_hw_init_defaults()
459 ah->htc_reset_init = true; in ath9k_hw_init_defaults()
461 ah->tpc_enabled = false; in ath9k_hw_init_defaults()
463 ah->ani_function = ATH9K_ANI_ALL; in ath9k_hw_init_defaults()
464 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_init_defaults()
465 ah->ani_function &= ~ATH9K_ANI_MRC_CCK; in ath9k_hw_init_defaults()
467 if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) in ath9k_hw_init_defaults()
468 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
470 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); in ath9k_hw_init_defaults()
473 static int ath9k_hw_init_macaddr(struct ath_hw *ah) in ath9k_hw_init_macaddr() argument
475 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_macaddr()
483 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); in ath9k_hw_init_macaddr()
502 static int ath9k_hw_post_init(struct ath_hw *ah) in ath9k_hw_post_init() argument
504 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_post_init()
508 if (!ath9k_hw_chip_test(ah)) in ath9k_hw_post_init()
512 if (!AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
513 ecode = ar9002_hw_rf_claim(ah); in ath9k_hw_post_init()
518 ecode = ath9k_hw_eeprom_init(ah); in ath9k_hw_post_init()
522 ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n", in ath9k_hw_post_init()
523 ah->eep_ops->get_eeprom_ver(ah), in ath9k_hw_post_init()
524 ah->eep_ops->get_eeprom_rev(ah)); in ath9k_hw_post_init()
526 ath9k_hw_ani_init(ah); in ath9k_hw_post_init()
532 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_post_init()
533 u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_post_init()
535 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ; in ath9k_hw_post_init()
536 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ; in ath9k_hw_post_init()
543 static int ath9k_hw_attach_ops(struct ath_hw *ah) in ath9k_hw_attach_ops() argument
545 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_attach_ops()
546 return ar9002_hw_attach_ops(ah); in ath9k_hw_attach_ops()
548 ar9003_hw_attach_ops(ah); in ath9k_hw_attach_ops()
553 static int __ath9k_hw_init(struct ath_hw *ah) in __ath9k_hw_init() argument
555 struct ath_common *common = ath9k_hw_common(ah); in __ath9k_hw_init()
558 ath9k_hw_read_revisions(ah); in __ath9k_hw_init()
560 switch (ah->hw_version.macVersion) { in __ath9k_hw_init()
582 ah->hw_version.macVersion, ah->hw_version.macRev); in __ath9k_hw_init()
591 if (AR_SREV_9300_20_OR_LATER(ah)) { in __ath9k_hw_init()
592 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
593 ah->WARegVal |= (AR_WA_D3_L1_DISABLE | in __ath9k_hw_init()
597 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in __ath9k_hw_init()
602 if (AR_SREV_9565(ah)) { in __ath9k_hw_init()
603 ah->WARegVal |= AR_WA_BIT22; in __ath9k_hw_init()
604 REG_WRITE(ah, AR_WA, ah->WARegVal); in __ath9k_hw_init()
607 ath9k_hw_init_defaults(ah); in __ath9k_hw_init()
608 ath9k_hw_init_config(ah); in __ath9k_hw_init()
610 r = ath9k_hw_attach_ops(ah); in __ath9k_hw_init()
614 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { in __ath9k_hw_init()
619 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) || in __ath9k_hw_init()
620 AR_SREV_9330(ah) || AR_SREV_9550(ah)) in __ath9k_hw_init()
621 ah->is_pciexpress = false; in __ath9k_hw_init()
623 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
624 ath9k_hw_init_cal_settings(ah); in __ath9k_hw_init()
626 if (!ah->is_pciexpress) in __ath9k_hw_init()
627 ath9k_hw_disablepcie(ah); in __ath9k_hw_init()
629 r = ath9k_hw_post_init(ah); in __ath9k_hw_init()
633 ath9k_hw_init_mode_gain_regs(ah); in __ath9k_hw_init()
634 r = ath9k_hw_fill_cap_info(ah); in __ath9k_hw_init()
638 r = ath9k_hw_init_macaddr(ah); in __ath9k_hw_init()
644 ath9k_hw_init_hang_checks(ah); in __ath9k_hw_init()
651 int ath9k_hw_init(struct ath_hw *ah) in ath9k_hw_init() argument
654 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init()
657 switch (ah->hw_version.devid) { in ath9k_hw_init()
684 ah->hw_version.devid); in ath9k_hw_init()
688 ret = __ath9k_hw_init(ah); in ath9k_hw_init()
696 ath_dynack_init(ah); in ath9k_hw_init()
702 static void ath9k_hw_init_qos(struct ath_hw *ah) in ath9k_hw_init_qos() argument
704 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_qos()
706 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
707 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
709 REG_WRITE(ah, AR_QOS_NO_ACK, in ath9k_hw_init_qos()
714 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); in ath9k_hw_init_qos()
715 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
716 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
717 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
718 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
720 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_qos()
723 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) in ar9003_get_pll_sqsum_dvc() argument
725 struct ath_common *common = ath9k_hw_common(ah); in ar9003_get_pll_sqsum_dvc()
728 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
730 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
732 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
744 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; in ar9003_get_pll_sqsum_dvc()
748 static void ath9k_hw_init_pll(struct ath_hw *ah, in ath9k_hw_init_pll() argument
753 pll = ath9k_hw_compute_pll_control(ah, chan); in ath9k_hw_init_pll()
755 if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_init_pll()
757 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
759 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
761 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
764 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
766 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
768 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1, in ath9k_hw_init_pll()
771 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
773 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
775 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
779 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
782 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, in ath9k_hw_init_pll()
785 } else if (AR_SREV_9330(ah)) { in ath9k_hw_init_pll()
788 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
799 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2); in ath9k_hw_init_pll()
802 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3, in ath9k_hw_init_pll()
805 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
810 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2); in ath9k_hw_init_pll()
813 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd); in ath9k_hw_init_pll()
814 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
817 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, in ath9k_hw_init_pll()
819 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_pll()
820 AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
823 REG_WRITE(ah, AR_RTC_PLL_CONTROL, in ath9k_hw_init_pll()
827 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
830 if (ah->is_clk_25mhz) { in ath9k_hw_init_pll()
831 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
841 if (AR_SREV_9340(ah)) { in ath9k_hw_init_pll()
847 pll2_divfrac = (AR_SREV_9531(ah) || in ath9k_hw_init_pll()
848 AR_SREV_9561(ah)) ? in ath9k_hw_init_pll()
854 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
855 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
859 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
862 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
866 regval = REG_READ(ah, AR_PHY_PLL_MODE); in ath9k_hw_init_pll()
867 if (AR_SREV_9340(ah)) in ath9k_hw_init_pll()
873 else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ath9k_hw_init_pll()
880 if (AR_SREV_9531(ah)) in ath9k_hw_init_pll()
888 REG_WRITE(ah, AR_PHY_PLL_MODE, regval); in ath9k_hw_init_pll()
890 if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ath9k_hw_init_pll()
891 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
894 REG_WRITE(ah, AR_PHY_PLL_MODE, in ath9k_hw_init_pll()
895 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
900 if (AR_SREV_9565(ah)) in ath9k_hw_init_pll()
902 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); in ath9k_hw_init_pll()
904 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ath9k_hw_init_pll()
905 AR_SREV_9550(ah)) in ath9k_hw_init_pll()
909 if (AR_SREV_9271(ah)) { in ath9k_hw_init_pll()
911 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
916 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); in ath9k_hw_init_pll()
919 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, in ath9k_hw_init_interrupt_masks() argument
929 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_interrupt_masks()
930 AR_SREV_9561(ah)) in ath9k_hw_init_interrupt_masks()
933 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
935 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
941 if (ah->config.rx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
947 if (ah->config.tx_intr_mitigation) in ath9k_hw_init_interrupt_masks()
952 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_interrupt_masks()
954 REG_WRITE(ah, AR_IMR, imr_reg); in ath9k_hw_init_interrupt_masks()
955 ah->imrs2_reg |= AR_IMR_S2_GTT; in ath9k_hw_init_interrupt_masks()
956 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); in ath9k_hw_init_interrupt_masks()
958 if (!AR_SREV_9100(ah)) { in ath9k_hw_init_interrupt_masks()
959 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
960 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); in ath9k_hw_init_interrupt_masks()
961 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
964 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_interrupt_masks()
966 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_init_interrupt_masks()
967 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
968 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
969 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); in ath9k_hw_init_interrupt_masks()
970 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); in ath9k_hw_init_interrupt_masks()
974 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us) in ath9k_hw_set_sifs_time() argument
976 u32 val = ath9k_hw_mac_to_clks(ah, us - 2); in ath9k_hw_set_sifs_time()
978 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val); in ath9k_hw_set_sifs_time()
981 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) in ath9k_hw_setslottime() argument
983 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_setslottime()
985 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); in ath9k_hw_setslottime()
988 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_ack_timeout() argument
990 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_ack_timeout()
992 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); in ath9k_hw_set_ack_timeout()
995 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) in ath9k_hw_set_cts_timeout() argument
997 u32 val = ath9k_hw_mac_to_clks(ah, us); in ath9k_hw_set_cts_timeout()
999 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); in ath9k_hw_set_cts_timeout()
1002 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) in ath9k_hw_set_global_txtimeout() argument
1005 ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n", in ath9k_hw_set_global_txtimeout()
1007 ah->globaltxtimeout = (u32) -1; in ath9k_hw_set_global_txtimeout()
1010 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); in ath9k_hw_set_global_txtimeout()
1011 ah->globaltxtimeout = tu; in ath9k_hw_set_global_txtimeout()
1016 void ath9k_hw_init_global_settings(struct ath_hw *ah) in ath9k_hw_init_global_settings() argument
1018 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_global_settings()
1019 const struct ath9k_channel *chan = ah->curchan; in ath9k_hw_init_global_settings()
1026 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1027 ah->misc_mode); in ath9k_hw_init_global_settings()
1032 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1033 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1035 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1050 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1060 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ath9k_hw_init_global_settings()
1067 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_init_global_settings()
1071 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ in ath9k_hw_init_global_settings()
1073 reg = REG_READ(ah, AR_USEC); in ath9k_hw_init_global_settings()
1078 slottime = ah->slottime; in ath9k_hw_init_global_settings()
1082 slottime += 3 * ah->coverage_class; in ath9k_hw_init_global_settings()
1095 acktimeout += 64 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1096 ctstimeout += 48 - sifstime - ah->slottime; in ath9k_hw_init_global_settings()
1099 if (ah->dynack.enabled) { in ath9k_hw_init_global_settings()
1100 acktimeout = ah->dynack.ackto; in ath9k_hw_init_global_settings()
1104 ah->dynack.ackto = acktimeout; in ath9k_hw_init_global_settings()
1107 ath9k_hw_set_sifs_time(ah, sifstime); in ath9k_hw_init_global_settings()
1108 ath9k_hw_setslottime(ah, slottime); in ath9k_hw_init_global_settings()
1109 ath9k_hw_set_ack_timeout(ah, acktimeout); in ath9k_hw_init_global_settings()
1110 ath9k_hw_set_cts_timeout(ah, ctstimeout); in ath9k_hw_init_global_settings()
1111 if (ah->globaltxtimeout != (u32) -1) in ath9k_hw_init_global_settings()
1112 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); in ath9k_hw_init_global_settings()
1114 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs)); in ath9k_hw_init_global_settings()
1115 REG_RMW(ah, AR_USEC, in ath9k_hw_init_global_settings()
1124 void ath9k_hw_deinit(struct ath_hw *ah) in ath9k_hw_deinit() argument
1126 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_deinit()
1131 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); in ath9k_hw_deinit()
1155 static inline void ath9k_hw_set_dma(struct ath_hw *ah) in ath9k_hw_set_dma() argument
1157 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_dma()
1160 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1165 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1166 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1171 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1173 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1180 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1181 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); in ath9k_hw_set_dma()
1183 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_dma()
1188 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK); in ath9k_hw_set_dma()
1193 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1195 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_dma()
1196 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1197 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1199 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - in ath9k_hw_set_dma()
1200 ah->caps.rx_status_len); in ath9k_hw_set_dma()
1207 if (AR_SREV_9285(ah)) { in ath9k_hw_set_dma()
1213 } else if (AR_SREV_9340_13_OR_LATER(ah)) { in ath9k_hw_set_dma()
1220 if (!AR_SREV_9271(ah)) in ath9k_hw_set_dma()
1221 REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size); in ath9k_hw_set_dma()
1223 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_dma()
1225 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_dma()
1226 ath9k_hw_reset_txstatus_ring(ah); in ath9k_hw_set_dma()
1229 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) in ath9k_hw_set_operating_mode() argument
1234 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_set_operating_mode()
1237 if (!AR_SREV_9340_13(ah)) { in ath9k_hw_set_operating_mode()
1239 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1248 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1251 if (!ah->is_monitoring) in ath9k_hw_set_operating_mode()
1255 REG_RMW(ah, AR_STA_ID1, set, mask); in ath9k_hw_set_operating_mode()
1256 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_set_operating_mode()
1259 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, in ath9k_hw_get_delta_slope_vals() argument
1281 static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type) in ath9k_hw_ar9330_reset_war() argument
1286 npend = ath9k_hw_numtxpending(ah, i); in ath9k_hw_ar9330_reset_war()
1291 if (ah->external_reset && in ath9k_hw_ar9330_reset_war()
1295 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_ar9330_reset_war()
1298 reset_err = ah->external_reset(); in ath9k_hw_ar9330_reset_war()
1300 ath_err(ath9k_hw_common(ah), in ath9k_hw_ar9330_reset_war()
1306 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_ar9330_reset_war()
1312 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) in ath9k_hw_set_reset() argument
1317 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1318 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK, in ath9k_hw_set_reset()
1320 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); in ath9k_hw_set_reset()
1323 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset()
1325 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset()
1326 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset()
1330 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset()
1333 if (AR_SREV_9100(ah)) { in ath9k_hw_set_reset()
1337 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); in ath9k_hw_set_reset()
1338 if (AR_SREV_9340(ah)) in ath9k_hw_set_reset()
1346 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); in ath9k_hw_set_reset()
1349 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1351 REG_WRITE(ah, AR_RC, val); in ath9k_hw_set_reset()
1353 } else if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1354 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset()
1361 if (AR_SREV_9330(ah)) { in ath9k_hw_set_reset()
1362 if (!ath9k_hw_ar9330_reset_war(ah, type)) in ath9k_hw_set_reset()
1366 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_reset()
1367 ar9003_mci_check_gpm_offset(ah); in ath9k_hw_set_reset()
1369 REG_WRITE(ah, AR_RTC_RC, rst_flags); in ath9k_hw_set_reset()
1371 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset()
1373 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset()
1375 else if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1380 REG_WRITE(ah, AR_RTC_RC, 0); in ath9k_hw_set_reset()
1381 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1382 ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n"); in ath9k_hw_set_reset()
1386 if (!AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1387 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1389 if (AR_SREV_9100(ah)) in ath9k_hw_set_reset()
1395 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) in ath9k_hw_set_reset_power_on() argument
1397 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_reset_power_on()
1399 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_power_on()
1400 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_power_on()
1404 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | in ath9k_hw_set_reset_power_on()
1407 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1408 REG_WRITE(ah, AR_RC, AR_RC_AHB); in ath9k_hw_set_reset_power_on()
1410 REG_WRITE(ah, AR_RTC_RESET, 0); in ath9k_hw_set_reset_power_on()
1412 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_reset_power_on()
1416 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_reset_power_on()
1417 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1419 REG_WRITE(ah, AR_RTC_RESET, 1); in ath9k_hw_set_reset_power_on()
1421 if (!ath9k_hw_wait(ah, in ath9k_hw_set_reset_power_on()
1426 ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n"); in ath9k_hw_set_reset_power_on()
1430 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); in ath9k_hw_set_reset_power_on()
1433 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) in ath9k_hw_set_reset_reg() argument
1437 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_reset_reg()
1438 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_reset_reg()
1442 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_reset_reg()
1445 if (!ah->reset_power_on) in ath9k_hw_set_reset_reg()
1450 ret = ath9k_hw_set_reset_power_on(ah); in ath9k_hw_set_reset_reg()
1452 ah->reset_power_on = true; in ath9k_hw_set_reset_reg()
1456 ret = ath9k_hw_set_reset(ah, type); in ath9k_hw_set_reset_reg()
1465 static bool ath9k_hw_chip_reset(struct ath_hw *ah, in ath9k_hw_chip_reset() argument
1470 if (AR_SREV_9280(ah)) { in ath9k_hw_chip_reset()
1471 if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) in ath9k_hw_chip_reset()
1475 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || in ath9k_hw_chip_reset()
1476 (REG_READ(ah, AR_CR) & AR_CR_RXE)) in ath9k_hw_chip_reset()
1479 if (!ath9k_hw_set_reset_reg(ah, reset_type)) in ath9k_hw_chip_reset()
1482 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_chip_reset()
1485 ah->chip_fullsleep = false; in ath9k_hw_chip_reset()
1487 if (AR_SREV_9330(ah)) in ath9k_hw_chip_reset()
1488 ar9003_hw_internal_regulator_apply(ah); in ath9k_hw_chip_reset()
1489 ath9k_hw_init_pll(ah, chan); in ath9k_hw_chip_reset()
1494 static bool ath9k_hw_channel_change(struct ath_hw *ah, in ath9k_hw_channel_change() argument
1497 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_channel_change()
1498 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_channel_change()
1505 u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags; in ath9k_hw_channel_change()
1511 if (ath9k_hw_numtxpending(ah, qnum)) { in ath9k_hw_channel_change()
1518 if (!ath9k_hw_rfbus_req(ah)) { in ath9k_hw_channel_change()
1524 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_channel_change()
1528 ath9k_hw_init_pll(ah, chan); in ath9k_hw_channel_change()
1530 if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) { in ath9k_hw_channel_change()
1536 ath9k_hw_set_channel_regs(ah, chan); in ath9k_hw_channel_change()
1538 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_channel_change()
1543 ath9k_hw_set_clockrate(ah); in ath9k_hw_channel_change()
1544 ath9k_hw_apply_txpower(ah, chan, false); in ath9k_hw_channel_change()
1546 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_channel_change()
1547 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_channel_change()
1550 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_channel_change()
1552 ath9k_hw_init_bb(ah, chan); in ath9k_hw_channel_change()
1553 ath9k_hw_rfbus_done(ah); in ath9k_hw_channel_change()
1556 ah->ah_flags |= AH_FASTCC; in ath9k_hw_channel_change()
1557 ath9k_hw_init_cal(ah, chan); in ath9k_hw_channel_change()
1558 ah->ah_flags &= ~AH_FASTCC; in ath9k_hw_channel_change()
1564 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah) in ath9k_hw_apply_gpio_override() argument
1566 u32 gpio_mask = ah->gpio_mask; in ath9k_hw_apply_gpio_override()
1573 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT); in ath9k_hw_apply_gpio_override()
1574 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i))); in ath9k_hw_apply_gpio_override()
1578 void ath9k_hw_check_nav(struct ath_hw *ah) in ath9k_hw_check_nav() argument
1580 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_check_nav()
1583 val = REG_READ(ah, AR_NAV); in ath9k_hw_check_nav()
1586 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1591 bool ath9k_hw_check_alive(struct ath_hw *ah) in ath9k_hw_check_alive() argument
1596 if (AR_SREV_9300(ah)) in ath9k_hw_check_alive()
1597 return !ath9k_hw_detect_mac_hang(ah); in ath9k_hw_check_alive()
1599 if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_check_alive()
1602 last_val = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1604 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_check_alive()
1627 static void ath9k_hw_init_mfp(struct ath_hw *ah) in ath9k_hw_init_mfp() argument
1630 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1633 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, in ath9k_hw_init_mfp()
1635 if (AR_SREV_9271(ah) || AR_DEVID_7010(ah)) in ath9k_hw_init_mfp()
1636 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1638 ah->sw_mgmt_crypto_tx = false; in ath9k_hw_init_mfp()
1639 ah->sw_mgmt_crypto_rx = false; in ath9k_hw_init_mfp()
1640 } else if (AR_SREV_9160_10_OR_LATER(ah)) { in ath9k_hw_init_mfp()
1642 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1644 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1646 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1647 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1649 ah->sw_mgmt_crypto_tx = true; in ath9k_hw_init_mfp()
1650 ah->sw_mgmt_crypto_rx = true; in ath9k_hw_init_mfp()
1654 static void ath9k_hw_reset_opmode(struct ath_hw *ah, in ath9k_hw_reset_opmode() argument
1657 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset_opmode()
1659 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset_opmode()
1661 REG_RMW(ah, AR_STA_ID1, macStaId1 in ath9k_hw_reset_opmode()
1663 | ah->sta_id1_defaults, in ath9k_hw_reset_opmode()
1666 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); in ath9k_hw_reset_opmode()
1667 ath9k_hw_write_associd(ah); in ath9k_hw_reset_opmode()
1668 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1669 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); in ath9k_hw_reset_opmode()
1671 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset_opmode()
1673 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_reset_opmode()
1676 static void ath9k_hw_init_queues(struct ath_hw *ah) in ath9k_hw_init_queues() argument
1680 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_init_queues()
1683 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); in ath9k_hw_init_queues()
1685 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_init_queues()
1687 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1689 ath9k_hw_resettxqueue(ah, i); in ath9k_hw_init_queues()
1695 static void ath9k_hw_init_desc(struct ath_hw *ah) in ath9k_hw_init_desc() argument
1697 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_init_desc()
1699 if (AR_SREV_9100(ah)) { in ath9k_hw_init_desc()
1701 mask = REG_READ(ah, AR_CFG); in ath9k_hw_init_desc()
1707 REG_WRITE(ah, AR_CFG, mask); in ath9k_hw_init_desc()
1709 REG_READ(ah, AR_CFG)); in ath9k_hw_init_desc()
1714 if (AR_SREV_9271(ah)) in ath9k_hw_init_desc()
1715 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); in ath9k_hw_init_desc()
1717 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1720 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || in ath9k_hw_init_desc()
1721 AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ath9k_hw_init_desc()
1722 AR_SREV_9561(ah)) in ath9k_hw_init_desc()
1723 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1725 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); in ath9k_hw_init_desc()
1734 static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_do_fastcc() argument
1736 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_do_fastcc()
1737 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_do_fastcc()
1740 if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI) in ath9k_hw_do_fastcc()
1743 if (ah->chip_fullsleep) in ath9k_hw_do_fastcc()
1746 if (!ah->curchan) in ath9k_hw_do_fastcc()
1749 if (chan->channel == ah->curchan->channel) in ath9k_hw_do_fastcc()
1752 if ((ah->curchan->channelFlags | chan->channelFlags) & in ath9k_hw_do_fastcc()
1760 ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT)) in ath9k_hw_do_fastcc()
1763 if (!ath9k_hw_check_alive(ah)) in ath9k_hw_do_fastcc()
1770 if (AR_SREV_9462(ah) && (ah->caldata && in ath9k_hw_do_fastcc()
1771 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1772 !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) || in ath9k_hw_do_fastcc()
1773 !test_bit(RTT_DONE, &ah->caldata->cal_flags)))) in ath9k_hw_do_fastcc()
1777 ah->curchan->channel, chan->channel); in ath9k_hw_do_fastcc()
1779 ret = ath9k_hw_channel_change(ah, chan); in ath9k_hw_do_fastcc()
1783 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_do_fastcc()
1784 ar9003_mci_2g5g_switch(ah, false); in ath9k_hw_do_fastcc()
1786 ath9k_hw_loadnf(ah, ah->curchan); in ath9k_hw_do_fastcc()
1787 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_do_fastcc()
1789 if (AR_SREV_9271(ah)) in ath9k_hw_do_fastcc()
1790 ar9002_hw_load_ani_reg(ah, chan); in ath9k_hw_do_fastcc()
1814 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_reset() argument
1817 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_reset()
1825 bool save_fullsleep = ah->chip_fullsleep; in ath9k_hw_reset()
1827 if (ath9k_hw_mci_is_enabled(ah)) { in ath9k_hw_reset()
1828 start_mci_reset = ar9003_mci_start_reset(ah, chan); in ath9k_hw_reset()
1833 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_reset()
1836 if (ah->curchan && !ah->chip_fullsleep) in ath9k_hw_reset()
1837 ath9k_hw_getnf(ah, ah->curchan); in ath9k_hw_reset()
1839 ah->caldata = caldata; in ath9k_hw_reset()
1844 ath9k_init_nfcal_hist_buffer(ah, chan); in ath9k_hw_reset()
1848 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor); in ath9k_hw_reset()
1851 r = ath9k_hw_do_fastcc(ah, chan); in ath9k_hw_reset()
1856 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1857 ar9003_mci_stop_bt(ah, save_fullsleep); in ath9k_hw_reset()
1859 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); in ath9k_hw_reset()
1863 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; in ath9k_hw_reset()
1866 tsf = ath9k_hw_gettsf64(ah); in ath9k_hw_reset()
1869 saveLedState = REG_READ(ah, AR_CFG_LED) & in ath9k_hw_reset()
1873 ath9k_hw_mark_phy_inactive(ah); in ath9k_hw_reset()
1875 ah->paprd_table_write_done = false; in ath9k_hw_reset()
1878 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1879 REG_WRITE(ah, in ath9k_hw_reset()
1885 if (!ath9k_hw_chip_reset(ah, chan)) { in ath9k_hw_reset()
1891 if (AR_SREV_9271(ah) && ah->htc_reset_init) { in ath9k_hw_reset()
1892 ah->htc_reset_init = false; in ath9k_hw_reset()
1893 REG_WRITE(ah, in ath9k_hw_reset()
1901 ath9k_hw_settsf64(ah, tsf + usec); in ath9k_hw_reset()
1903 if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_reset()
1904 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1906 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
1907 ar9002_hw_enable_async_fifo(ah); in ath9k_hw_reset()
1909 r = ath9k_hw_process_ini(ah, chan); in ath9k_hw_reset()
1913 ath9k_hw_set_rfmode(ah, chan); in ath9k_hw_reset()
1915 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1916 ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep); in ath9k_hw_reset()
1924 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) { in ath9k_hw_reset()
1926 ath9k_hw_settsf64(ah, tsf); in ath9k_hw_reset()
1929 ath9k_hw_init_mfp(ah); in ath9k_hw_reset()
1931 ath9k_hw_set_delta_slope(ah, chan); in ath9k_hw_reset()
1932 ath9k_hw_spur_mitigate_freq(ah, chan); in ath9k_hw_reset()
1933 ah->eep_ops->set_board_values(ah, chan); in ath9k_hw_reset()
1935 ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna); in ath9k_hw_reset()
1937 r = ath9k_hw_rf_set_freq(ah, chan); in ath9k_hw_reset()
1941 ath9k_hw_set_clockrate(ah); in ath9k_hw_reset()
1943 ath9k_hw_init_queues(ah); in ath9k_hw_reset()
1944 ath9k_hw_init_interrupt_masks(ah, ah->opmode); in ath9k_hw_reset()
1945 ath9k_hw_ani_cache_ini_regs(ah); in ath9k_hw_reset()
1946 ath9k_hw_init_qos(ah); in ath9k_hw_reset()
1948 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) in ath9k_hw_reset()
1949 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio); in ath9k_hw_reset()
1951 ath9k_hw_init_global_settings(ah); in ath9k_hw_reset()
1953 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) { in ath9k_hw_reset()
1954 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1956 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN, in ath9k_hw_reset()
1958 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1962 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
1964 ath9k_hw_set_dma(ah); in ath9k_hw_reset()
1966 if (!ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
1967 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
1969 ENABLE_REG_RMW_BUFFER(ah); in ath9k_hw_reset()
1970 if (ah->config.rx_intr_mitigation) { in ath9k_hw_reset()
1971 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last); in ath9k_hw_reset()
1972 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first); in ath9k_hw_reset()
1975 if (ah->config.tx_intr_mitigation) { in ath9k_hw_reset()
1976 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); in ath9k_hw_reset()
1977 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); in ath9k_hw_reset()
1979 REG_RMW_BUFFER_FLUSH(ah); in ath9k_hw_reset()
1981 ath9k_hw_init_bb(ah, chan); in ath9k_hw_reset()
1987 if (!ath9k_hw_init_cal(ah, chan)) in ath9k_hw_reset()
1990 if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata)) in ath9k_hw_reset()
1993 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_reset()
1995 ath9k_hw_restore_chainmask(ah); in ath9k_hw_reset()
1996 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); in ath9k_hw_reset()
1998 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_reset()
2000 ath9k_hw_gen_timer_start_tsf2(ah); in ath9k_hw_reset()
2002 ath9k_hw_init_desc(ah); in ath9k_hw_reset()
2004 if (ath9k_hw_btcoex_is_enabled(ah)) in ath9k_hw_reset()
2005 ath9k_hw_btcoex_enable(ah); in ath9k_hw_reset()
2007 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_reset()
2008 ar9003_mci_check_bt(ah); in ath9k_hw_reset()
2010 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_reset()
2011 ath9k_hw_loadnf(ah, chan); in ath9k_hw_reset()
2012 ath9k_hw_start_nfcal(ah, true); in ath9k_hw_reset()
2015 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_reset()
2016 ar9003_hw_bb_watchdog_config(ah); in ath9k_hw_reset()
2018 if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR) in ath9k_hw_reset()
2019 ar9003_hw_disable_phy_restart(ah); in ath9k_hw_reset()
2021 ath9k_hw_apply_gpio_override(ah); in ath9k_hw_reset()
2023 if (AR_SREV_9565(ah) && common->bt_ant_diversity) in ath9k_hw_reset()
2024 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON); in ath9k_hw_reset()
2026 if (ah->hw->conf.radar_enabled) { in ath9k_hw_reset()
2028 ah->radar_conf.ext_channel = IS_CHAN_HT40(chan); in ath9k_hw_reset()
2029 ath9k_hw_set_radar_params(ah); in ath9k_hw_reset()
2044 static void ath9k_set_power_sleep(struct ath_hw *ah) in ath9k_set_power_sleep() argument
2046 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_sleep()
2048 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_set_power_sleep()
2049 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2050 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2051 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2053 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2061 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_sleep()
2063 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_sleep()
2066 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2067 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); in ath9k_set_power_sleep()
2070 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) { in ath9k_set_power_sleep()
2071 REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN); in ath9k_set_power_sleep()
2076 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_sleep()
2077 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_sleep()
2085 static void ath9k_set_power_network_sleep(struct ath_hw *ah) in ath9k_set_power_network_sleep() argument
2087 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_set_power_network_sleep()
2089 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_set_power_network_sleep()
2093 REG_WRITE(ah, AR_RTC_FORCE_WAKE, in ath9k_set_power_network_sleep()
2106 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2107 REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN, in ath9k_set_power_network_sleep()
2113 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); in ath9k_set_power_network_sleep()
2115 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_set_power_network_sleep()
2120 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_set_power_network_sleep()
2121 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE); in ath9k_set_power_network_sleep()
2124 static bool ath9k_hw_set_power_awake(struct ath_hw *ah) in ath9k_hw_set_power_awake() argument
2130 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_set_power_awake()
2131 REG_WRITE(ah, AR_WA, ah->WARegVal); in ath9k_hw_set_power_awake()
2135 if ((REG_READ(ah, AR_RTC_STATUS) & in ath9k_hw_set_power_awake()
2137 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { in ath9k_hw_set_power_awake()
2140 if (!AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_set_power_awake()
2141 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_set_power_awake()
2143 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2144 REG_SET_BIT(ah, AR_RTC_RESET, in ath9k_hw_set_power_awake()
2147 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2149 if (AR_SREV_9100(ah)) in ath9k_hw_set_power_awake()
2155 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; in ath9k_hw_set_power_awake()
2159 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, in ath9k_hw_set_power_awake()
2163 ath_err(ath9k_hw_common(ah), in ath9k_hw_set_power_awake()
2169 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_set_power_awake()
2170 ar9003_mci_set_power_awake(ah); in ath9k_hw_set_power_awake()
2172 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_power_awake()
2177 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) in ath9k_hw_setpower() argument
2179 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_setpower()
2188 if (ah->power_mode == mode) in ath9k_hw_setpower()
2192 modes[ah->power_mode], modes[mode]); in ath9k_hw_setpower()
2196 status = ath9k_hw_set_power_awake(ah); in ath9k_hw_setpower()
2199 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_setpower()
2200 ar9003_mci_set_full_sleep(ah); in ath9k_hw_setpower()
2202 ath9k_set_power_sleep(ah); in ath9k_hw_setpower()
2203 ah->chip_fullsleep = true; in ath9k_hw_setpower()
2206 ath9k_set_power_network_sleep(ah); in ath9k_hw_setpower()
2212 ah->power_mode = mode; in ath9k_hw_setpower()
2220 if (!(ah->ah_flags & AH_UNPLUGGED)) in ath9k_hw_setpower()
2231 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) in ath9k_hw_beaconinit() argument
2235 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_beaconinit()
2237 switch (ah->opmode) { in ath9k_hw_beaconinit()
2239 REG_SET_BIT(ah, AR_TXCFG, in ath9k_hw_beaconinit()
2243 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon); in ath9k_hw_beaconinit()
2244 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon - in ath9k_hw_beaconinit()
2245 TU_TO_USEC(ah->config.dma_beacon_response_time)); in ath9k_hw_beaconinit()
2246 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon - in ath9k_hw_beaconinit()
2247 TU_TO_USEC(ah->config.sw_beacon_response_time)); in ath9k_hw_beaconinit()
2252 ath_dbg(ath9k_hw_common(ah), BEACON, in ath9k_hw_beaconinit()
2253 "%s: unsupported opmode: %d\n", __func__, ah->opmode); in ath9k_hw_beaconinit()
2258 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2259 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2260 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period); in ath9k_hw_beaconinit()
2262 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_beaconinit()
2264 REG_SET_BIT(ah, AR_TIMER_MODE, flags); in ath9k_hw_beaconinit()
2268 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, in ath9k_hw_set_sta_beacon_timers() argument
2272 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_set_sta_beacon_timers()
2273 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_set_sta_beacon_timers()
2275 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2277 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt); in ath9k_hw_set_sta_beacon_timers()
2278 REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2279 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval); in ath9k_hw_set_sta_beacon_timers()
2281 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2283 REG_RMW_FIELD(ah, AR_RSSI_THR, in ath9k_hw_set_sta_beacon_timers()
2305 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_set_sta_beacon_timers()
2307 REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2308 REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP); in ath9k_hw_set_sta_beacon_timers()
2310 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
2319 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
2322 REG_WRITE(ah, AR_TIM_PERIOD, beaconintval); in ath9k_hw_set_sta_beacon_timers()
2323 REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod); in ath9k_hw_set_sta_beacon_timers()
2325 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_set_sta_beacon_timers()
2327 REG_SET_BIT(ah, AR_TIMER_MODE, in ath9k_hw_set_sta_beacon_timers()
2332 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); in ath9k_hw_set_sta_beacon_timers()
2362 static bool ath9k_hw_dfs_tested(struct ath_hw *ah) in ath9k_hw_dfs_tested() argument
2365 switch (ah->hw_version.macVersion) { in ath9k_hw_dfs_tested()
2376 int ath9k_hw_fill_cap_info(struct ath_hw *ah) in ath9k_hw_fill_cap_info() argument
2378 struct ath9k_hw_capabilities *pCap = &ah->caps; in ath9k_hw_fill_cap_info()
2379 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); in ath9k_hw_fill_cap_info()
2380 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_fill_cap_info()
2385 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); in ath9k_hw_fill_cap_info()
2388 if (ah->opmode != NL80211_IFTYPE_AP && in ath9k_hw_fill_cap_info()
2389 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { in ath9k_hw_fill_cap_info()
2399 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); in ath9k_hw_fill_cap_info()
2402 if (ah->disable_5ghz) in ath9k_hw_fill_cap_info()
2409 if (ah->disable_2ghz) in ath9k_hw_fill_cap_info()
2420 if (AR_SREV_9485(ah) || in ath9k_hw_fill_cap_info()
2421 AR_SREV_9285(ah) || in ath9k_hw_fill_cap_info()
2422 AR_SREV_9330(ah) || in ath9k_hw_fill_cap_info()
2423 AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2425 else if (!AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2427 else if (!AR_SREV_9300_20_OR_LATER(ah) || in ath9k_hw_fill_cap_info()
2428 AR_SREV_9340(ah) || in ath9k_hw_fill_cap_info()
2429 AR_SREV_9462(ah) || in ath9k_hw_fill_cap_info()
2430 AR_SREV_9531(ah)) in ath9k_hw_fill_cap_info()
2435 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); in ath9k_hw_fill_cap_info()
2440 if ((ah->hw_version.devid == AR5416_DEVID_PCI) && in ath9k_hw_fill_cap_info()
2442 !(AR_SREV_9271(ah))) in ath9k_hw_fill_cap_info()
2444 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2445 else if (AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2449 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); in ath9k_hw_fill_cap_info()
2453 ah->txchainmask = pCap->tx_chainmask; in ath9k_hw_fill_cap_info()
2454 ah->rxchainmask = pCap->rx_chainmask; in ath9k_hw_fill_cap_info()
2456 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; in ath9k_hw_fill_cap_info()
2459 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2460 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH; in ath9k_hw_fill_cap_info()
2464 if (ah->hw_version.devid != AR2427_DEVID_PCIE) in ath9k_hw_fill_cap_info()
2469 if (AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2471 else if (AR_DEVID_7010(ah)) in ath9k_hw_fill_cap_info()
2473 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2475 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2477 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2479 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2484 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) in ath9k_hw_fill_cap_info()
2490 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); in ath9k_hw_fill_cap_info()
2491 if (ah->rfsilent & EEP_RFSILENT_ENABLED) { in ath9k_hw_fill_cap_info()
2492 ah->rfkill_gpio = in ath9k_hw_fill_cap_info()
2493 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); in ath9k_hw_fill_cap_info()
2494 ah->rfkill_polarity = in ath9k_hw_fill_cap_info()
2495 MS(ah->rfsilent, EEP_RFSILENT_POLARITY); in ath9k_hw_fill_cap_info()
2500 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2505 if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) in ath9k_hw_fill_cap_info()
2510 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2512 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && in ath9k_hw_fill_cap_info()
2513 !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) in ath9k_hw_fill_cap_info()
2523 if (AR_SREV_9280_20(ah)) in ath9k_hw_fill_cap_info()
2527 if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2530 if (AR_SREV_9561(ah)) in ath9k_hw_fill_cap_info()
2531 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2532 else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2533 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); in ath9k_hw_fill_cap_info()
2535 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah)) in ath9k_hw_fill_cap_info()
2538 if (AR_SREV_9285(ah)) { in ath9k_hw_fill_cap_info()
2539 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) { in ath9k_hw_fill_cap_info()
2541 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2549 if (AR_SREV_9300_20_OR_LATER(ah)) { in ath9k_hw_fill_cap_info()
2550 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE)) in ath9k_hw_fill_cap_info()
2554 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2555 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ath9k_hw_fill_cap_info()
2562 if (ath9k_hw_dfs_tested(ah)) in ath9k_hw_fill_cap_info()
2577 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_fill_cap_info()
2578 if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE)) in ath9k_hw_fill_cap_info()
2581 if (AR_SREV_9462_20_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2585 if (AR_SREV_9300_20_OR_LATER(ah) && in ath9k_hw_fill_cap_info()
2586 ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) in ath9k_hw_fill_cap_info()
2590 if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah)) in ath9k_hw_fill_cap_info()
2591 ah->wow.max_patterns = MAX_NUM_PATTERN; in ath9k_hw_fill_cap_info()
2593 ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY; in ath9k_hw_fill_cap_info()
2603 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, in ath9k_hw_gpio_cfg_output_mux() argument
2618 if (AR_SREV_9280_20_OR_LATER(ah) in ath9k_hw_gpio_cfg_output_mux()
2620 REG_RMW(ah, addr, (type << gpio_shift), in ath9k_hw_gpio_cfg_output_mux()
2623 tmp = REG_READ(ah, addr); in ath9k_hw_gpio_cfg_output_mux()
2627 REG_WRITE(ah, addr, tmp); in ath9k_hw_gpio_cfg_output_mux()
2631 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) in ath9k_hw_cfg_gpio_input() argument
2635 BUG_ON(gpio >= ah->caps.num_gpio_pins); in ath9k_hw_cfg_gpio_input()
2637 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_gpio_input()
2639 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_gpio_input()
2646 REG_RMW(ah, in ath9k_hw_cfg_gpio_input()
2653 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) in ath9k_hw_gpio_get() argument
2656 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) in ath9k_hw_gpio_get()
2658 if (gpio >= ah->caps.num_gpio_pins) in ath9k_hw_gpio_get()
2661 if (AR_DEVID_7010(ah)) { in ath9k_hw_gpio_get()
2663 val = REG_READ(ah, AR7010_GPIO_IN); in ath9k_hw_gpio_get()
2665 } else if (AR_SREV_9300_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2666 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & in ath9k_hw_gpio_get()
2668 else if (AR_SREV_9271(ah)) in ath9k_hw_gpio_get()
2670 else if (AR_SREV_9287_11_OR_LATER(ah)) in ath9k_hw_gpio_get()
2672 else if (AR_SREV_9285_12_OR_LATER(ah)) in ath9k_hw_gpio_get()
2674 else if (AR_SREV_9280_20_OR_LATER(ah)) in ath9k_hw_gpio_get()
2681 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, in ath9k_hw_cfg_output() argument
2686 if (AR_DEVID_7010(ah)) { in ath9k_hw_cfg_output()
2688 REG_RMW(ah, AR7010_GPIO_OE, in ath9k_hw_cfg_output()
2694 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); in ath9k_hw_cfg_output()
2696 REG_RMW(ah, in ath9k_hw_cfg_output()
2703 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) in ath9k_hw_set_gpio() argument
2705 if (AR_DEVID_7010(ah)) { in ath9k_hw_set_gpio()
2707 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio), in ath9k_hw_set_gpio()
2712 if (AR_SREV_9271(ah)) in ath9k_hw_set_gpio()
2716 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), in ath9k_hw_set_gpio()
2723 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label) in ath9k_hw_request_gpio() argument
2725 if (gpio >= ah->caps.num_gpio_pins) in ath9k_hw_request_gpio()
2732 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) in ath9k_hw_setantenna() argument
2734 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2742 u32 ath9k_hw_getrxfilter(struct ath_hw *ah) in ath9k_hw_getrxfilter() argument
2744 u32 bits = REG_READ(ah, AR_RX_FILTER); in ath9k_hw_getrxfilter()
2745 u32 phybits = REG_READ(ah, AR_PHY_ERR); in ath9k_hw_getrxfilter()
2756 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) in ath9k_hw_setrxfilter() argument
2760 ENABLE_REGWRITE_BUFFER(ah); in ath9k_hw_setrxfilter()
2762 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ath9k_hw_setrxfilter()
2765 REG_WRITE(ah, AR_RX_FILTER, bits); in ath9k_hw_setrxfilter()
2772 REG_WRITE(ah, AR_PHY_ERR, phybits); in ath9k_hw_setrxfilter()
2775 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2777 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA); in ath9k_hw_setrxfilter()
2779 REGWRITE_BUFFER_FLUSH(ah); in ath9k_hw_setrxfilter()
2783 bool ath9k_hw_phy_disable(struct ath_hw *ah) in ath9k_hw_phy_disable() argument
2785 if (ath9k_hw_mci_is_enabled(ah)) in ath9k_hw_phy_disable()
2786 ar9003_mci_bt_gain_ctrl(ah); in ath9k_hw_phy_disable()
2788 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) in ath9k_hw_phy_disable()
2791 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_phy_disable()
2792 ah->htc_reset_init = true; in ath9k_hw_phy_disable()
2797 bool ath9k_hw_disable(struct ath_hw *ah) in ath9k_hw_disable() argument
2799 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) in ath9k_hw_disable()
2802 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) in ath9k_hw_disable()
2805 ath9k_hw_init_pll(ah, NULL); in ath9k_hw_disable()
2810 static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan) in get_antenna_gain() argument
2819 return ah->eep_ops->get_eeprom(ah, gain_param); in get_antenna_gain()
2822 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan, in ath9k_hw_apply_txpower() argument
2825 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_apply_txpower()
2838 ant_gain = get_antenna_gain(ah, chan); in ath9k_hw_apply_txpower()
2842 ah->eep_ops->set_txpower(ah, chan, in ath9k_hw_apply_txpower()
2847 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test) in ath9k_hw_set_txpowerlimit() argument
2849 struct ath_regulatory *reg = ath9k_hw_regulatory(ah); in ath9k_hw_set_txpowerlimit()
2850 struct ath9k_channel *chan = ah->curchan; in ath9k_hw_set_txpowerlimit()
2857 ath9k_hw_apply_txpower(ah, chan, test); in ath9k_hw_set_txpowerlimit()
2864 void ath9k_hw_setopmode(struct ath_hw *ah) in ath9k_hw_setopmode() argument
2866 ath9k_hw_set_operating_mode(ah, ah->opmode); in ath9k_hw_setopmode()
2870 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) in ath9k_hw_setmcastfilter() argument
2872 REG_WRITE(ah, AR_MCAST_FIL0, filter0); in ath9k_hw_setmcastfilter()
2873 REG_WRITE(ah, AR_MCAST_FIL1, filter1); in ath9k_hw_setmcastfilter()
2877 void ath9k_hw_write_associd(struct ath_hw *ah) in ath9k_hw_write_associd() argument
2879 struct ath_common *common = ath9k_hw_common(ah); in ath9k_hw_write_associd()
2881 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); in ath9k_hw_write_associd()
2882 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | in ath9k_hw_write_associd()
2889 u64 ath9k_hw_gettsf64(struct ath_hw *ah) in ath9k_hw_gettsf64() argument
2894 tsf_upper1 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2896 tsf_lower = REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf64()
2897 tsf_upper2 = REG_READ(ah, AR_TSF_U32); in ath9k_hw_gettsf64()
2909 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) in ath9k_hw_settsf64() argument
2911 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
2912 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
2916 void ath9k_hw_reset_tsf(struct ath_hw *ah) in ath9k_hw_reset_tsf() argument
2918 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
2920 ath_dbg(ath9k_hw_common(ah), RESET, in ath9k_hw_reset_tsf()
2923 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); in ath9k_hw_reset_tsf()
2927 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set) in ath9k_hw_set_tsfadjust() argument
2930 ah->misc_mode |= AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2932 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; in ath9k_hw_set_tsfadjust()
2936 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan) in ath9k_hw_set11nmac2040() argument
2940 if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca) in ath9k_hw_set11nmac2040()
2945 REG_WRITE(ah, AR_2040_MODE, macmode); in ath9k_hw_set11nmac2040()
2979 u32 ath9k_hw_gettsf32(struct ath_hw *ah) in ath9k_hw_gettsf32() argument
2981 return REG_READ(ah, AR_TSF_L32); in ath9k_hw_gettsf32()
2985 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah) in ath9k_hw_gen_timer_start_tsf2() argument
2987 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start_tsf2()
2990 REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN); in ath9k_hw_gen_timer_start_tsf2()
2991 REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE); in ath9k_hw_gen_timer_start_tsf2()
2995 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, in ath_gen_timer_alloc() argument
3001 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_alloc()
3009 !AR_SREV_9300_20_OR_LATER(ah)) in ath_gen_timer_alloc()
3025 ath9k_hw_gen_timer_start_tsf2(ah); in ath_gen_timer_alloc()
3032 void ath9k_hw_gen_timer_start(struct ath_hw *ah, in ath9k_hw_gen_timer_start() argument
3037 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_start()
3045 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, in ath9k_hw_gen_timer_start()
3047 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, in ath9k_hw_gen_timer_start()
3049 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_start()
3052 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_start()
3059 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3062 REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_start()
3073 REG_SET_BIT(ah, AR_IMR_S5, mask); in ath9k_hw_gen_timer_start()
3075 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3076 ah->imask |= ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_start()
3077 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_start()
3082 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) in ath9k_hw_gen_timer_stop() argument
3084 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath9k_hw_gen_timer_stop()
3087 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, in ath9k_hw_gen_timer_stop()
3090 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ath9k_hw_gen_timer_stop()
3095 REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL, in ath9k_hw_gen_timer_stop()
3101 REG_CLR_BIT(ah, AR_IMR_S5, in ath9k_hw_gen_timer_stop()
3108 ah->imask &= ~ATH9K_INT_GENTIMER; in ath9k_hw_gen_timer_stop()
3109 ath9k_hw_set_interrupts(ah); in ath9k_hw_gen_timer_stop()
3114 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) in ath_gen_timer_free() argument
3116 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_free()
3127 void ath_gen_timer_isr(struct ath_hw *ah) in ath_gen_timer_isr() argument
3129 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; in ath_gen_timer_isr()
3135 trigger_mask = ah->intr_gen_timer_trigger; in ath_gen_timer_isr()
3136 thresh_mask = ah->intr_gen_timer_thresh; in ath_gen_timer_isr()
3235 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) in ath9k_hw_name() argument
3240 if (AR_SREV_9280_20_OR_LATER(ah)) { in ath9k_hw_name()
3243 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3244 ah->hw_version.macRev); in ath9k_hw_name()
3249 ath9k_hw_mac_bb_name(ah->hw_version.macVersion), in ath9k_hw_name()
3250 ah->hw_version.macRev, in ath9k_hw_name()
3251 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev in ath9k_hw_name()
3253 ah->hw_version.phyRev); in ath9k_hw_name()