30 	struct ath_hw *ah;  member
118 	struct ath_hw *ah = (struct ath_hw *) hw_priv;  in ath9k_iowrite32()  local
119 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_iowrite32()
122 	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {  in ath9k_iowrite32()
133 	struct ath_hw *ah = (struct ath_hw *) hw_priv;  in ath9k_ioread32()  local
134 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_ioread32()
138 	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {  in ath9k_ioread32()
173 	struct ath_hw *ah = (struct ath_hw *) hw_priv;  in ath9k_reg_rmw()  local
174 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_reg_rmw()
179 	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {  in ath9k_reg_rmw()
198 	struct ath_hw *ah = sc->sc_ah;  in ath9k_reg_notifier()  local
199 	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);  in ath9k_reg_notifier()
204 	if (!ah->curchan)  in ath9k_reg_notifier()
207 	sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;  in ath9k_reg_notifier()
209 	ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);  in ath9k_reg_notifier()
210 	ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,  in ath9k_reg_notifier()
383 	sc->spec_priv.ah = sc->sc_ah;  in ath9k_init_misc()
394 	struct ath_hw *ah = sc->sc_ah;  in ath9k_init_pcoem_platform()  local
395 	struct ath9k_hw_capabilities *pCap = &ah->caps;  in ath9k_init_pcoem_platform()
396 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_init_pcoem_platform()
406 		ah->config.xlna_gpio = 9;  in ath9k_init_pcoem_platform()
407 		ah->config.xatten_margin_cfg = true;  in ath9k_init_pcoem_platform()
408 		ah->config.alt_mingainidx = true;  in ath9k_init_pcoem_platform()
409 		ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;  in ath9k_init_pcoem_platform()
450 		ah->config.pcie_waen = 0x0040473b;  in ath9k_init_pcoem_platform()
459 	ah->config.pll_pwrsave = 1;  in ath9k_init_pcoem_platform()
462 		ah->config.pll_pwrsave = 0;  in ath9k_init_pcoem_platform()
467 		ah->config.led_active_high = true;  in ath9k_init_pcoem_platform()
476 		ec->ah->eeprom_blob = eeprom_blob;  in ath9k_eeprom_request_cb()
484 	struct ath_hw *ah = ah = sc->sc_ah;  in ath9k_eeprom_request()  local
489 	ec.ah = sc->sc_ah;  in ath9k_eeprom_request()
494 		ath_err(ath9k_hw_common(ah),  in ath9k_eeprom_request()
501 	if (!ah->eeprom_blob) {  in ath9k_eeprom_request()
502 		ath_err(ath9k_hw_common(ah),  in ath9k_eeprom_request()
518 	struct ath_hw *ah = sc->sc_ah;  in ath9k_init_soc_platform()  local
531 		ah->config.tx_gain_buffalo = true;  in ath9k_init_soc_platform()
540 	struct ath_hw *ah = NULL;  in ath9k_init_softc()  local
546 	ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);  in ath9k_init_softc()
547 	if (!ah)  in ath9k_init_softc()
550 	ah->dev = sc->dev;  in ath9k_init_softc()
551 	ah->hw = sc->hw;  in ath9k_init_softc()
552 	ah->hw_version.devid = devid;  in ath9k_init_softc()
553 	ah->reg_ops.read = ath9k_ioread32;  in ath9k_init_softc()
554 	ah->reg_ops.multi_read = ath9k_multi_ioread32;  in ath9k_init_softc()
555 	ah->reg_ops.write = ath9k_iowrite32;  in ath9k_init_softc()
556 	ah->reg_ops.rmw = ath9k_reg_rmw;  in ath9k_init_softc()
557 	pCap = &ah->caps;  in ath9k_init_softc()
559 	common = ath9k_hw_common(ah);  in ath9k_init_softc()
564 	sc->sc_ah = ah;  in ath9k_init_softc()
573 		ah->ah_flags |= AH_USE_EEPROM;  in ath9k_init_softc()
579 		ah->is_clk_25mhz = pdata->is_clk_25mhz;  in ath9k_init_softc()
580 		ah->get_mac_revision = pdata->get_mac_revision;  in ath9k_init_softc()
581 		ah->external_reset = pdata->external_reset;  in ath9k_init_softc()
582 		ah->disable_2ghz = pdata->disable_2ghz;  in ath9k_init_softc()
583 		ah->disable_5ghz = pdata->disable_5ghz;  in ath9k_init_softc()
585 			ah->ah_flags |= AH_NO_EEP_SWAP;  in ath9k_init_softc()
588 	common->ops = &ah->reg_ops;  in ath9k_init_softc()
591 	common->ah = ah;  in ath9k_init_softc()
608 		ah->config.led_active_high = ath9k_led_active_high == 1;  in ath9k_init_softc()
645 	ret = ath9k_hw_init(ah);  in ath9k_init_softc()
684 	ath9k_hw_deinit(ah);  in ath9k_init_softc()
695 	struct ath_hw *ah = sc->sc_ah;  in ath9k_init_band_txpower()  local
696 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_init_band_txpower()
703 		ah->curchan = &ah->channels[chan->hw_value];  in ath9k_init_band_txpower()
705 		ath9k_cmn_get_channel(sc->hw, ah, &chandef);  in ath9k_init_band_txpower()
706 		ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);  in ath9k_init_band_txpower()
712 	struct ath_hw *ah = sc->sc_ah;  in ath9k_init_txpower_limits()  local
713 	struct ath9k_channel *curchan = ah->curchan;  in ath9k_init_txpower_limits()
715 	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)  in ath9k_init_txpower_limits()
717 	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)  in ath9k_init_txpower_limits()
720 	ah->curchan = curchan;  in ath9k_init_txpower_limits()
800 	struct ath_hw *ah = sc->sc_ah;  in ath9k_set_mcc_capab()  local
801 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_set_mcc_capab()
825 	struct ath_hw *ah = sc->sc_ah;  in ath9k_set_hw_capab()  local
826 	struct ath_common *common = ath9k_hw_common(ah);  in ath9k_set_hw_capab()
843 		if (AR_SREV_9280_20_OR_LATER(ah))  in ath9k_set_hw_capab()
886 	hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;  in ath9k_set_hw_capab()
887 	hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;  in ath9k_set_hw_capab()
890 	if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)  in ath9k_set_hw_capab()
907 	ath9k_cmn_reload_chainmask(ah);  in ath9k_set_hw_capab()
917 	struct ath_hw *ah;  in ath9k_init_device()  local
926 	ah = sc->sc_ah;  in ath9k_init_device()
927 	common = ath9k_hw_common(ah);  in ath9k_init_device()
962 	error = ath9k_init_debug(ah);  in ath9k_init_device()