Lines Matching refs:ah
23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
345 #define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc)
346 #define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0)
347 #define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4)
348 #define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8)
692 #define AR_WA (AR_SREV_9340(ah) ? 0x40c4 : 0x4004)
714 #define AR_HOST_TIMEOUT (AR_SREV_9340(ah) ? 0x4008 : 0x4018)
744 ((AR_SREV_9100(ah)) ? 0x0600 : (AR_SREV_9340(ah) \
748 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF)
827 #define AR_SREV_9100(ah) \ argument
828 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100)
884 (AR_SREV_9300(ah) && \
1027 #define AR_INTR_SYNC_CAUSE (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
1028 #define AR_INTR_SYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4010 : 0x4028)
1031 #define AR_INTR_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4014 : 0x402c)
1073 #define AR_INTR_ASYNC_MASK (AR_SREV_9340(ah) ? 0x4018 : 0x4030)
1079 #define AR_INTR_SYNC_MASK (AR_SREV_9340(ah) ? 0x401c : 0x4034)
1083 #define AR_INTR_ASYNC_CAUSE_CLR (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
1084 #define AR_INTR_ASYNC_CAUSE (AR_SREV_9340(ah) ? 0x4020 : 0x4038)
1094 #define AR_INTR_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4024 : 0x403c)
1100 #define AR_PCIE_PM_CTRL (AR_SREV_9340(ah) ? 0x4004 : 0x4014)
1113 #define AR_GPIO_IN_OUT (AR_SREV_9340(ah) ? 0x4028 : 0x4048)
1127 #define AR_GPIO_IN (AR_SREV_9340(ah) ? 0x402c : 0x404c)
1131 #define AR_GPIO_OE_OUT (AR_SREV_9340(ah) ? 0x4030 : \
1132 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c))
1133 #define AR_GPIO_OE_OUT_MASK (AR_SREV_9550_OR_LATER(ah) ? \
1156 #define AR_GPIO_INTR_POL (AR_SREV_9340(ah) ? 0x4038 : \
1157 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050))
1161 #define AR_GPIO_INPUT_EN_VAL (AR_SREV_9340(ah) ? 0x403c : \
1162 (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054))
1180 #define AR_GPIO_INPUT_MUX1 (AR_SREV_9340(ah) ? 0x4040 : \
1181 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058))
1187 #define AR_GPIO_INPUT_MUX2 (AR_SREV_9340(ah) ? 0x4044 : \
1188 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c))
1196 #define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9340(ah) ? 0x4048 : \
1197 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060))
1198 #define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9340(ah) ? 0x404c : \
1199 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064))
1200 #define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9340(ah) ? 0x4050 : \
1201 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068))
1203 #define AR_INPUT_STATE (AR_SREV_9340(ah) ? 0x4054 : \
1204 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c))
1206 #define AR_EEPROM_STATUS_DATA (AR_SREV_9340(ah) ? 0x40c8 : \
1207 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c))
1215 #define AR_OBS (AR_SREV_9340(ah) ? 0x405c : \
1216 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080))
1218 #define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088)
1220 #define AR_PCIE_MSI (AR_SREV_9340(ah) ? 0x40d8 : \
1221 (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094))
1224 #define AR_INTR_PRIO_SYNC_ENABLE (AR_SREV_9340(ah) ? 0x4088 : 0x40c4)
1225 #define AR_INTR_PRIO_ASYNC_MASK (AR_SREV_9340(ah) ? 0x408c : 0x40c8)
1226 #define AR_INTR_PRIO_SYNC_MASK (AR_SREV_9340(ah) ? 0x4090 : 0x40cc)
1227 #define AR_INTR_PRIO_ASYNC_ENABLE (AR_SREV_9340(ah) ? 0x4094 : 0x40d4)
1292 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000)
1310 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014)
1331 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040)
1335 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044)
1338 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f)
1348 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048)
1353 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c)
1359 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050)
1362 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054)
1365 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058)
1372 (AR_SREV_9100(ah) ? (AR_RTC_BASE + 0x0038) : 0x7038)
2038 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AG…