1106 	struct ath_hw *ah = sc->sc_ah;  in ath_get_rate_txpower()  local
1108 	if (sc->tx99_state || !ah->tpc_enabled)  in ath_get_rate_txpower()
1115 	if (!AR_SREV_9300_20_OR_LATER(ah)) {  in ath_get_rate_txpower()
1120 			struct ar5416_eeprom_def *eep = &ah->eeprom.def;  in ath_get_rate_txpower()
1135 		if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||  in ath_get_rate_txpower()
1136 		    AR_SREV_9271(ah)) {  in ath_get_rate_txpower()
1138 		} else if (AR_SREV_9280_20_OR_LATER(ah)) {  in ath_get_rate_txpower()
1141 			power_offset = ah->eep_ops->get_eeprom(ah,  in ath_get_rate_txpower()
1150 		max_power = min_t(u8, ah->tx_power[rateidx], txpower);  in ath_get_rate_txpower()
1156 		if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))  in ath_get_rate_txpower()
1160 			max_power = min_t(u8, ah->tx_power_stbc[rateidx],  in ath_get_rate_txpower()
1163 			max_power = min_t(u8, ah->tx_power[rateidx],  in ath_get_rate_txpower()
1166 		max_power = ah->paprd_training_power;  in ath_get_rate_txpower()
1175 	struct ath_hw *ah = sc->sc_ah;  in ath_buf_set_rate()  local
1176 	struct ath_common *common = ath9k_hw_common(ah);  in ath_buf_set_rate()
1237 					ah->txchainmask, info->rates[i].Rate);  in ath_buf_set_rate()
1265 			info->rates[i].ChSel = ah->txchainmask;  in ath_buf_set_rate()
1268 					ah->txchainmask, info->rates[i].Rate);  in ath_buf_set_rate()
1313 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_fill_desc()  local
1397 		ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);  in ath_tx_fill_desc()
1694 	struct ath_hw *ah = sc->sc_ah;  in ath_txq_setup()  local
1726 	if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {  in ath_txq_setup()
1735 	axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);  in ath_txq_setup()
1767 	struct ath_hw *ah = sc->sc_ah;  in ath_txq_update()  local
1773 	ath9k_hw_get_txq_props(ah, qnum, &qi);  in ath_txq_update()
1780 	if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {  in ath_txq_update()
1785 		ath9k_hw_resettxqueue(ah, qnum);  in ath_txq_update()
1863 	struct ath_hw *ah = sc->sc_ah;  in ath_drain_all_txq()  local
1872 	ath9k_hw_abort_tx_dma(ah);  in ath_drain_all_txq()
1882 		if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))  in ath_drain_all_txq()
2019 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_txqaddbuf()  local
2020 	struct ath_common *common = ath9k_hw_common(ah);  in ath_tx_txqaddbuf()
2033 	edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);  in ath_tx_txqaddbuf()
2048 			ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);  in ath_tx_txqaddbuf()
2060 		ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);  in ath_tx_txqaddbuf()
2067 		ath9k_hw_txstart(ah, txq->axq_qnum);  in ath_tx_txqaddbuf()
2167 	struct ath_hw *ah = sc->sc_ah;  in ath_txchainmask_reduction()  local
2168 	struct ath9k_channel *curchan = ah->curchan;  in ath_txchainmask_reduction()
2170 	if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&  in ath_txchainmask_reduction()
2173 	else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&  in ath_txchainmask_reduction()
2591 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_rc_status()  local
2625 		    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)  in ath_tx_rc_status()
2640 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_processq()  local
2641 	struct ath_common *common = ath9k_hw_common(ah);  in ath_tx_processq()
2686 		status = ath9k_hw_txprocdesc(ah, ds, &ts);  in ath_tx_processq()
2715 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_tasklet()  local
2716 	u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;  in ath_tx_tasklet()
2729 	struct ath_hw *ah = sc->sc_ah;  in ath_tx_edma_tasklet()  local
2740 		status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);  in ath_tx_edma_tasklet()