244 	b43_phy_maskset(dev, B43_PHY_HT_CLASS_CTL, ~allowed, tmp);  in b43_phy_ht_classifier()
688 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1,  in b43_phy_ht_tx_power_ctl_setup()
690 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C2,  in b43_phy_ht_tx_power_ctl_setup()
692 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C3,  in b43_phy_ht_tx_power_ctl_setup()
698 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,  in b43_phy_ht_tx_power_ctl_setup()
701 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI,  in b43_phy_ht_tx_power_ctl_setup()
704 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_IDLE_TSSI2,  in b43_phy_ht_tx_power_ctl_setup()
708 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_TSSID,  in b43_phy_ht_tx_power_ctl_setup()
710 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_N, ~B43_PHY_HT_TXPCTL_N_NPTIL2,  in b43_phy_ht_tx_power_ctl_setup()
714 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x800, 0)  in b43_phy_ht_tx_power_ctl_setup()
715 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_CMD_C1, 0x400, 0)  in b43_phy_ht_tx_power_ctl_setup()
718 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,  in b43_phy_ht_tx_power_ctl_setup()
721 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR,  in b43_phy_ht_tx_power_ctl_setup()
724 	b43_phy_maskset(dev, B43_PHY_HT_TXPCTL_TARG_PWR2,  in b43_phy_ht_tx_power_ctl_setup()
960 	b43_phy_maskset(dev, 0x0280, 0xff00, 0x3e);  in b43_phy_ht_op_init()
961 	b43_phy_maskset(dev, 0x0283, 0xff00, 0x3e);  in b43_phy_ht_op_init()
962 	b43_phy_maskset(dev, B43_PHY_OFDM(0x0141), 0xff00, 0x46);  in b43_phy_ht_op_init()
963 	b43_phy_maskset(dev, 0x0283, 0xff00, 0x40);  in b43_phy_ht_op_init()
973 	b43_phy_maskset(dev, B43_PHY_OFDM(0x24), 0x3f, 0xd);  in b43_phy_ht_op_init()
974 	b43_phy_maskset(dev, B43_PHY_OFDM(0x64), 0x3f, 0xd);  in b43_phy_ht_op_init()
975 	b43_phy_maskset(dev, B43_PHY_OFDM(0xa4), 0x3f, 0xd);  in b43_phy_ht_op_init()