Lines Matching refs:reg
88 u32 reg; in rt2800_bbp_write() local
96 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2800_bbp_write()
97 reg = 0; in rt2800_bbp_write()
98 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
99 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
100 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
101 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
102 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
104 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); in rt2800_bbp_write()
113 u32 reg; in rt2800_bbp_read() local
125 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2800_bbp_read()
126 reg = 0; in rt2800_bbp_read()
127 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
128 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
129 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
130 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
132 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg); in rt2800_bbp_read()
134 WAIT_FOR_BBP(rt2x00dev, ®); in rt2800_bbp_read()
137 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE); in rt2800_bbp_read()
145 u32 reg; in rt2800_rfcsr_write() local
153 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { in rt2800_rfcsr_write()
154 reg = 0; in rt2800_rfcsr_write()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
157 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
160 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); in rt2800_rfcsr_write()
169 u32 reg; in rt2800_rfcsr_read() local
181 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) { in rt2800_rfcsr_read()
182 reg = 0; in rt2800_rfcsr_read()
183 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
184 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
185 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
187 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg); in rt2800_rfcsr_read()
189 WAIT_FOR_RFCSR(rt2x00dev, ®); in rt2800_rfcsr_read()
192 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA); in rt2800_rfcsr_read()
200 u32 reg; in rt2800_rf_write() local
208 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2800_rf_write()
209 reg = 0; in rt2800_rf_write()
210 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
211 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
212 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
213 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
215 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg); in rt2800_rf_write()
372 u32 reg; in rt2800_enable_wlan_rt3290() local
375 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_enable_wlan_rt3290()
376 if (rt2x00_get_field32(reg, WLAN_EN)) in rt2800_enable_wlan_rt3290()
379 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
380 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
381 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
382 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
383 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
393 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); in rt2800_enable_wlan_rt3290()
394 if (rt2x00_get_field32(reg, PLL_LD) && in rt2800_enable_wlan_rt3290()
395 rt2x00_get_field32(reg, XTAL_RDY)) in rt2800_enable_wlan_rt3290()
416 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_enable_wlan_rt3290()
417 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
418 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
419 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
420 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
422 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
423 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_enable_wlan_rt3290()
435 u32 reg; in rt2800_mcu_request() local
449 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt2800_mcu_request()
450 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
451 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
452 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
453 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
454 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt2800_mcu_request()
456 reg = 0; in rt2800_mcu_request()
457 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
458 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg); in rt2800_mcu_request()
468 u32 reg; in rt2800_wait_csr_ready() local
471 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); in rt2800_wait_csr_ready()
472 if (reg && reg != ~0) in rt2800_wait_csr_ready()
485 u32 reg; in rt2800_wait_wpdma_ready() local
492 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_wait_wpdma_ready()
493 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) && in rt2800_wait_wpdma_ready()
494 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY)) in rt2800_wait_wpdma_ready()
500 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg); in rt2800_wait_wpdma_ready()
507 u32 reg; in rt2800_disable_wpdma() local
509 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_disable_wpdma()
510 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
511 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
512 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
513 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
514 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
515 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_disable_wpdma()
632 u32 reg; in rt2800_load_firmware() local
658 rt2800_register_read(rt2x00dev, AUX_CTRL, ®); in rt2800_load_firmware()
659 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
660 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
661 rt2800_register_write(rt2x00dev, AUX_CTRL, reg); in rt2800_load_firmware()
677 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®); in rt2800_load_firmware()
678 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY)) in rt2800_load_firmware()
955 u64 off, reg = 0; in rt2800_update_beacons_setup() local
966 reg |= off << (8 * bcn_num); in rt2800_update_beacons_setup()
972 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg); in rt2800_update_beacons_setup()
973 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32)); in rt2800_update_beacons_setup()
990 u32 orig_reg, reg; in rt2800_write_beacon() local
997 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_write_beacon()
998 orig_reg = reg; in rt2800_write_beacon()
999 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1000 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_write_beacon()
1081 u32 orig_reg, reg; in rt2800_clear_beacon() local
1088 reg = orig_reg; in rt2800_clear_beacon()
1089 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1090 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_clear_beacon()
1157 u32 reg; in rt2800_rfkill_poll() local
1160 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_rfkill_poll()
1161 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0); in rt2800_rfkill_poll()
1163 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_rfkill_poll()
1164 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2); in rt2800_rfkill_poll()
1184 u32 reg; in rt2800_brightness_set() local
1188 rt2800_register_read(led->rt2x00dev, LED_CFG, ®); in rt2800_brightness_set()
1191 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1195 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1198 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1201 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1205 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); in rt2800_brightness_set()
1271 u32 reg; in rt2800_config_wcid_attr_bssidx() local
1277 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_bssidx()
1278 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1279 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1281 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_bssidx()
1290 u32 reg; in rt2800_config_wcid_attr_cipher() local
1295 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_cipher()
1296 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1303 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1305 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1307 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1308 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_cipher()
1311 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_wcid_attr_cipher()
1312 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1313 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1314 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1315 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1316 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_wcid_attr_cipher()
1338 u32 reg; in rt2800_config_shared_key() local
1367 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_shared_key()
1368 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1370 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_shared_key()
1503 u32 reg; in rt2800_config_filter() local
1511 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®); in rt2800_config_filter()
1512 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1514 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1516 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, in rt2800_config_filter()
1518 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1519 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1520 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1522 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1523 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1524 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1526 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1528 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1530 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1532 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1534 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1536 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1537 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1539 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1541 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg); in rt2800_config_filter()
1548 u32 reg; in rt2800_config_intf() local
1555 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_config_intf()
1556 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1557 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_config_intf()
1563 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); in rt2800_config_intf()
1564 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1565 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1566 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1567 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1568 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); in rt2800_config_intf()
1570 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®); in rt2800_config_intf()
1571 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1572 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1573 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1574 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
1575 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg); in rt2800_config_intf()
1591 reg = le32_to_cpu(conf->mac[1]); in rt2800_config_intf()
1592 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
1593 conf->mac[1] = cpu_to_le32(reg); in rt2800_config_intf()
1602 reg = le32_to_cpu(conf->bssid[1]); in rt2800_config_intf()
1603 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
1604 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
1605 conf->bssid[1] = cpu_to_le32(reg); in rt2800_config_intf()
1622 u32 reg; in rt2800_config_ht_opmode() local
1689 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_config_ht_opmode()
1690 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
1691 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
1692 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_config_ht_opmode()
1694 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_config_ht_opmode()
1695 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
1696 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
1697 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_config_ht_opmode()
1699 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_config_ht_opmode()
1700 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
1701 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
1702 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_config_ht_opmode()
1704 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_config_ht_opmode()
1705 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
1706 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
1707 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_config_ht_opmode()
1713 u32 reg; in rt2800_config_erp() local
1716 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); in rt2800_config_erp()
1717 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, in rt2800_config_erp()
1719 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
1721 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); in rt2800_config_erp()
1725 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_config_erp()
1726 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
1728 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_config_erp()
1738 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); in rt2800_config_erp()
1739 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
1741 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); in rt2800_config_erp()
1743 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); in rt2800_config_erp()
1744 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
1745 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); in rt2800_config_erp()
1749 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_config_erp()
1750 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
1752 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_config_erp()
1762 u32 reg; in rt2800_config_3572bt_ant() local
1766 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_config_3572bt_ant()
1768 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
1769 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
1771 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
1772 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
1774 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_config_3572bt_ant()
1776 rt2800_register_read(rt2x00dev, LED_CFG, ®); in rt2800_config_3572bt_ant()
1777 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; in rt2800_config_3572bt_ant()
1778 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; in rt2800_config_3572bt_ant()
1779 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || in rt2800_config_3572bt_ant()
1780 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { in rt2800_config_3572bt_ant()
1784 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
1785 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
1786 rt2800_register_write(rt2x00dev, LED_CFG, reg); in rt2800_config_3572bt_ant()
1797 u32 reg; in rt2800_set_ant_diversity() local
1802 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®); in rt2800_set_ant_diversity()
1803 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
1804 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg); in rt2800_set_ant_diversity()
1809 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_set_ant_diversity()
1810 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
1811 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
1812 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_set_ant_diversity()
2115 u32 reg; in rt2800_config_channel_rf3052() local
2265 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_config_channel_rf3052()
2266 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2268 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2270 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
2271 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_config_channel_rf3052()
2762 u32 reg; in rt2800_config_channel_rf55xx() local
2769 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_config_channel_rf55xx()
2770 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
2772 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_config_channel_rf55xx()
3035 u8 chain, reg; in rt2800_bbp_write_with_rx_chain() local
3038 rt2800_bbp_read(rt2x00dev, 27, ®); in rt2800_bbp_write_with_rx_chain()
3039 rt2x00_set_field8(®, BBP27_RX_CHAIN_SEL, chain); in rt2800_bbp_write_with_rx_chain()
3040 rt2800_bbp_write(rt2x00dev, 27, reg); in rt2800_bbp_write_with_rx_chain()
3154 u32 reg; in rt2800_config_channel() local
3288 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®); in rt2800_config_channel()
3289 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
3290 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
3291 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
3292 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); in rt2800_config_channel()
3354 reg = 0x1c + (2 * rt2x00dev->lna_gain); in rt2800_config_channel()
3356 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); in rt2800_config_channel()
3358 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3362 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_config_channel()
3368 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
3370 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
3372 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
3380 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3381 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
3383 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3384 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
3387 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
3388 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
3391 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_config_channel()
3395 reg = 0x1c + 2 * rt2x00dev->lna_gain; in rt2800_config_channel()
3397 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3); in rt2800_config_channel()
3399 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3409 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain; in rt2800_config_channel()
3410 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg); in rt2800_config_channel()
3440 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®); in rt2800_config_channel()
3441 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®); in rt2800_config_channel()
3442 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®); in rt2800_config_channel()
4105 u32 reg, offset; in rt2800_config_txpower_rt28xx() local
4173 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_config_txpower_rt28xx()
4189 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
4200 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
4211 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
4222 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
4238 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
4249 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
4260 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
4271 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
4273 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_config_txpower_rt28xx()
4380 u32 reg; in rt2800_config_retry_limit() local
4382 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); in rt2800_config_retry_limit()
4383 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
4385 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
4387 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); in rt2800_config_retry_limit()
4396 u32 reg; in rt2800_config_ps() local
4401 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); in rt2800_config_ps()
4402 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
4403 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
4405 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
4406 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); in rt2800_config_ps()
4410 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®); in rt2800_config_ps()
4411 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
4412 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
4413 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
4414 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); in rt2800_config_ps()
4448 u32 reg; in rt2800_link_stats() local
4453 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); in rt2800_link_stats()
4454 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR); in rt2800_link_stats()
4564 u32 reg; in rt2800_init_registers() local
4580 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®); in rt2800_init_registers()
4581 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
4582 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
4583 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
4584 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
4585 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
4586 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
4587 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); in rt2800_init_registers()
4591 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®); in rt2800_init_registers()
4592 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
4593 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
4594 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); in rt2800_init_registers()
4597 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®); in rt2800_init_registers()
4598 if (rt2x00_get_field32(reg, WLAN_EN) == 1) { in rt2800_init_registers()
4599 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
4600 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg); in rt2800_init_registers()
4603 rt2800_register_read(rt2x00dev, CMB_CTRL, ®); in rt2800_init_registers()
4604 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) { in rt2800_init_registers()
4605 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
4606 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
4607 rt2800_register_write(rt2x00dev, CMB_CTRL, reg); in rt2800_init_registers()
4610 rt2800_register_read(rt2x00dev, OSC_CTRL, ®); in rt2800_init_registers()
4611 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
4612 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
4613 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
4614 rt2800_register_write(rt2x00dev, OSC_CTRL, reg); in rt2800_init_registers()
4616 rt2800_register_read(rt2x00dev, COEX_CFG0, ®); in rt2800_init_registers()
4617 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
4618 rt2800_register_write(rt2x00dev, COEX_CFG0, reg); in rt2800_init_registers()
4620 rt2800_register_read(rt2x00dev, COEX_CFG2, ®); in rt2800_init_registers()
4621 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
4622 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
4623 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
4624 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
4625 rt2800_register_write(rt2x00dev, COEX_CFG2, reg); in rt2800_init_registers()
4627 rt2800_register_read(rt2x00dev, PLL_CTRL, ®); in rt2800_init_registers()
4628 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
4629 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); in rt2800_init_registers()
4708 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); in rt2800_init_registers()
4709 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
4710 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
4711 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
4712 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
4713 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
4714 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
4715 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
4716 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
4717 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); in rt2800_init_registers()
4719 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); in rt2800_init_registers()
4720 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
4721 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
4722 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
4723 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); in rt2800_init_registers()
4725 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); in rt2800_init_registers()
4726 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
4730 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); in rt2800_init_registers()
4732 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); in rt2800_init_registers()
4733 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0); in rt2800_init_registers()
4734 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0); in rt2800_init_registers()
4735 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); in rt2800_init_registers()
4737 rt2800_register_read(rt2x00dev, LED_CFG, ®); in rt2800_init_registers()
4738 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
4739 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
4740 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
4741 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
4742 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
4743 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
4744 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
4745 rt2800_register_write(rt2x00dev, LED_CFG, reg); in rt2800_init_registers()
4749 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); in rt2800_init_registers()
4750 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); in rt2800_init_registers()
4751 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); in rt2800_init_registers()
4752 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
4753 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
4754 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
4755 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
4756 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); in rt2800_init_registers()
4758 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); in rt2800_init_registers()
4759 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
4760 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
4761 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0); in rt2800_init_registers()
4762 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
4763 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1); in rt2800_init_registers()
4764 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
4765 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
4766 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); in rt2800_init_registers()
4768 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); in rt2800_init_registers()
4769 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4770 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4771 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4772 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4773 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4774 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4775 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4776 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4777 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4778 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4779 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); in rt2800_init_registers()
4781 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_init_registers()
4782 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
4783 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4784 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4785 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4786 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4787 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4788 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4789 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4790 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4791 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
4792 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_init_registers()
4794 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_init_registers()
4795 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4796 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4797 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4798 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4799 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4800 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4801 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4802 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4803 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4804 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4805 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_init_registers()
4807 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_init_registers()
4808 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4809 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4810 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4811 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4812 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4813 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4814 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4815 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4816 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4817 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4818 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_init_registers()
4820 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_init_registers()
4821 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
4822 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4823 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4824 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4825 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4826 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4827 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
4828 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4829 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
4830 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4831 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_init_registers()
4833 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_init_registers()
4834 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
4835 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
4836 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
4837 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
4838 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
4839 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
4840 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
4841 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
4842 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
4843 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
4844 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_init_registers()
4849 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_init_registers()
4850 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
4851 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
4852 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
4853 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
4854 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
4855 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
4856 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
4857 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
4858 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
4859 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_init_registers()
4866 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); in rt2800_init_registers()
4867 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
4868 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
4869 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
4870 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
4871 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
4872 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
4873 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
4874 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
4875 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
4876 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
4877 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); in rt2800_init_registers()
4879 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; in rt2800_init_registers()
4880 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); in rt2800_init_registers()
4882 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); in rt2800_init_registers()
4883 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32); in rt2800_init_registers()
4884 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
4886 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0); in rt2800_init_registers()
4887 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); in rt2800_init_registers()
4898 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®); in rt2800_init_registers()
4899 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
4900 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
4901 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
4902 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
4903 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
4904 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); in rt2800_init_registers()
4928 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); in rt2800_init_registers()
4929 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
4930 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); in rt2800_init_registers()
4932 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®); in rt2800_init_registers()
4933 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
4934 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg); in rt2800_init_registers()
4937 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®); in rt2800_init_registers()
4938 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
4939 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
4940 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
4941 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
4942 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
4943 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
4944 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
4945 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
4946 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg); in rt2800_init_registers()
4948 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®); in rt2800_init_registers()
4949 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
4950 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
4951 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
4952 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
4953 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
4954 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
4955 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
4956 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
4957 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg); in rt2800_init_registers()
4959 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®); in rt2800_init_registers()
4960 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
4961 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
4962 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
4963 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
4964 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
4965 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
4966 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
4967 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
4968 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg); in rt2800_init_registers()
4970 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®); in rt2800_init_registers()
4971 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
4972 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
4973 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
4974 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
4975 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg); in rt2800_init_registers()
4980 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®); in rt2800_init_registers()
4981 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
4982 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
4983 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg); in rt2800_init_registers()
4990 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®); in rt2800_init_registers()
4991 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®); in rt2800_init_registers()
4992 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®); in rt2800_init_registers()
4993 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®); in rt2800_init_registers()
4994 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®); in rt2800_init_registers()
4995 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®); in rt2800_init_registers()
5000 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®); in rt2800_init_registers()
5001 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
5002 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg); in rt2800_init_registers()
5007 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®); in rt2800_init_registers()
5008 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
5009 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
5010 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
5011 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
5012 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
5013 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg); in rt2800_init_registers()
5021 u32 reg; in rt2800_wait_bbp_rf_ready() local
5024 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®); in rt2800_wait_bbp_rf_ready()
5025 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY)) in rt2800_wait_bbp_rf_ready()
5557 u32 reg; in rt2800_init_bbp_53xx() local
5559 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_init_bbp_53xx()
5560 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
5561 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
5562 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
5563 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
5565 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
5567 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
5568 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_init_bbp_53xx()
5721 u32 reg; in rt2800_led_open_drain_enable() local
5723 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®); in rt2800_led_open_drain_enable()
5724 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
5725 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); in rt2800_led_open_drain_enable()
5961 u8 reg; in rt2800_normal_mode_setup_5xxx() local
5965 rt2800_bbp_read(rt2x00dev, 138, ®); in rt2800_normal_mode_setup_5xxx()
5968 rt2x00_set_field8(®, BBP138_RX_ADC1, 0); in rt2800_normal_mode_setup_5xxx()
5970 rt2x00_set_field8(®, BBP138_TX_DAC1, 1); in rt2800_normal_mode_setup_5xxx()
5971 rt2800_bbp_write(rt2x00dev, 138, reg); in rt2800_normal_mode_setup_5xxx()
5973 rt2800_rfcsr_read(rt2x00dev, 38, ®); in rt2800_normal_mode_setup_5xxx()
5974 rt2x00_set_field8(®, RFCSR38_RX_LO1_EN, 0); in rt2800_normal_mode_setup_5xxx()
5975 rt2800_rfcsr_write(rt2x00dev, 38, reg); in rt2800_normal_mode_setup_5xxx()
5977 rt2800_rfcsr_read(rt2x00dev, 39, ®); in rt2800_normal_mode_setup_5xxx()
5978 rt2x00_set_field8(®, RFCSR39_RX_LO2_EN, 0); in rt2800_normal_mode_setup_5xxx()
5979 rt2800_rfcsr_write(rt2x00dev, 39, reg); in rt2800_normal_mode_setup_5xxx()
5983 rt2800_rfcsr_read(rt2x00dev, 30, ®); in rt2800_normal_mode_setup_5xxx()
5984 rt2x00_set_field8(®, RFCSR30_RX_VCM, 2); in rt2800_normal_mode_setup_5xxx()
5985 rt2800_rfcsr_write(rt2x00dev, 30, reg); in rt2800_normal_mode_setup_5xxx()
6030 u32 reg; in rt2800_init_rfcsr_30xx() local
6056 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_30xx()
6057 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6058 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6059 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_30xx()
6068 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_30xx()
6069 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
6075 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
6077 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
6079 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_30xx()
6081 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_30xx()
6082 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
6083 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_30xx()
6233 u32 reg; in rt2800_init_rfcsr_3390() local
6270 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_3390()
6271 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
6272 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_3390()
6286 u32 reg; in rt2800_init_rfcsr_3572() local
6326 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3572()
6327 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
6328 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6329 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3572()
6331 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3572()
6332 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
6333 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
6334 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3572()
6391 u32 reg; in rt2800_init_rfcsr_3593() local
6395 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); in rt2800_init_rfcsr_3593()
6396 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
6397 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
6398 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); in rt2800_init_rfcsr_3593()
6446 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3593()
6447 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
6448 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
6449 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3593()
6451 rt2800_register_read(rt2x00dev, LDO_CFG0, ®); in rt2800_init_rfcsr_3593()
6452 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
6453 rt2800_register_write(rt2x00dev, LDO_CFG0, reg); in rt2800_init_rfcsr_3593()
6722 u32 reg; in rt2800_enable_radio() local
6772 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_enable_radio()
6773 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6774 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
6775 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_enable_radio()
6779 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); in rt2800_enable_radio()
6780 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
6781 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
6782 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2); in rt2800_enable_radio()
6783 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
6784 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); in rt2800_enable_radio()
6786 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_enable_radio()
6787 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
6788 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
6789 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_enable_radio()
6812 u32 reg; in rt2800_disable_radio() local
6819 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®); in rt2800_disable_radio()
6820 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
6821 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
6822 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg); in rt2800_disable_radio()
6828 u32 reg; in rt2800_efuse_detect() local
6836 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®); in rt2800_efuse_detect()
6837 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT); in rt2800_efuse_detect()
6843 u32 reg; in rt2800_efuse_read() local
6865 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®); in rt2800_efuse_read()
6866 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
6867 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
6868 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
6869 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg); in rt2800_efuse_read()
6872 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®); in rt2800_efuse_read()
6874 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®); in rt2800_efuse_read()
6876 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg); in rt2800_efuse_read()
6877 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®); in rt2800_efuse_read()
6878 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg); in rt2800_efuse_read()
6879 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®); in rt2800_efuse_read()
6880 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg); in rt2800_efuse_read()
6881 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®); in rt2800_efuse_read()
6882 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg); in rt2800_efuse_read()
7491 u32 reg; in rt2800_probe_hw_mode() local
7581 rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, ®); in rt2800_probe_hw_mode()
7582 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) { in rt2800_probe_hw_mode()
7709 u32 reg; in rt2800_probe_rt() local
7714 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®); in rt2800_probe_rt()
7716 rt2800_register_read(rt2x00dev, MAC_CSR0, ®); in rt2800_probe_rt()
7718 rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET); in rt2800_probe_rt()
7719 rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION); in rt2800_probe_rt()
7751 u32 reg; in rt2800_probe_hw() local
7772 rt2800_register_read(rt2x00dev, GPIO_CTRL, ®); in rt2800_probe_hw()
7773 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
7774 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg); in rt2800_probe_hw()
7840 u32 reg; in rt2800_set_rts_threshold() local
7843 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); in rt2800_set_rts_threshold()
7844 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
7845 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); in rt2800_set_rts_threshold()
7847 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); in rt2800_set_rts_threshold()
7848 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7849 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); in rt2800_set_rts_threshold()
7851 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); in rt2800_set_rts_threshold()
7852 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7853 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); in rt2800_set_rts_threshold()
7855 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); in rt2800_set_rts_threshold()
7856 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7857 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); in rt2800_set_rts_threshold()
7859 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); in rt2800_set_rts_threshold()
7860 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7861 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); in rt2800_set_rts_threshold()
7863 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); in rt2800_set_rts_threshold()
7864 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7865 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); in rt2800_set_rts_threshold()
7867 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); in rt2800_set_rts_threshold()
7868 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
7869 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); in rt2800_set_rts_threshold()
7883 u32 reg; in rt2800_conf_tx() local
7910 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_conf_tx()
7911 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
7912 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_conf_tx()
7918 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®); in rt2800_conf_tx()
7919 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
7920 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg); in rt2800_conf_tx()
7922 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®); in rt2800_conf_tx()
7923 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
7924 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg); in rt2800_conf_tx()
7926 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®); in rt2800_conf_tx()
7927 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
7928 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg); in rt2800_conf_tx()
7933 rt2800_register_read(rt2x00dev, offset, ®); in rt2800_conf_tx()
7934 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
7935 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
7936 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
7937 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()
7938 rt2800_register_write(rt2x00dev, offset, reg); in rt2800_conf_tx()
7948 u32 reg; in rt2800_get_tsf() local
7950 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®); in rt2800_get_tsf()
7951 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32; in rt2800_get_tsf()
7952 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®); in rt2800_get_tsf()
7953 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD); in rt2800_get_tsf()