Lines Matching refs:rt2x00mmio_register_read
164 rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR, ®); in rt61pci_mcu_request()
179 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_eepromregister_read()
208 .read = rt2x00mmio_register_read,
243 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_rfkill_poll()
294 rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14, ®); in rt61pci_blink_set()
339 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
372 rt2x00mmio_register_read(rt2x00dev, SEC_CSR1, ®); in rt61pci_config_shared_key()
379 rt2x00mmio_register_read(rt2x00dev, SEC_CSR5, ®); in rt61pci_config_shared_key()
404 rt2x00mmio_register_read(rt2x00dev, SEC_CSR0, ®); in rt61pci_config_shared_key()
433 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
436 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
470 rt2x00mmio_register_read(rt2x00dev, SEC_CSR4, ®); in rt61pci_config_pairwise_key()
495 rt2x00mmio_register_read(rt2x00dev, SEC_CSR2, ®); in rt61pci_config_pairwise_key()
504 rt2x00mmio_register_read(rt2x00dev, SEC_CSR3, ®); in rt61pci_config_pairwise_key()
526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_filter()
558 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_intf()
589 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_config_erp()
595 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_erp()
607 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_config_erp()
614 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_config_erp()
618 rt2x00mmio_register_read(rt2x00dev, MAC_CSR8, ®); in rt61pci_config_erp()
715 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_config_antenna_2529_rx()
822 rt2x00mmio_register_read(rt2x00dev, PHY_CSR0, ®); in rt61pci_config_ant()
929 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4, ®); in rt61pci_config_retry_limit()
949 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
970 rt2x00mmio_register_read(rt2x00dev, MAC_CSR11, ®); in rt61pci_config_ps()
1016 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_link_stats()
1022 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_link_stats()
1141 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_start_queue()
1146 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_start_queue()
1164 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1169 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1174 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1179 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_kick_queue()
1195 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1200 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1205 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1210 rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR, ®); in rt61pci_stop_queue()
1215 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_stop_queue()
1220 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_stop_queue()
1302 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_load_firmware()
1341 rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR, ®); in rt61pci_load_firmware()
1365 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1370 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_load_firmware()
1428 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0, ®); in rt61pci_init_queues()
1439 rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1, ®); in rt61pci_init_queues()
1445 rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR, ®); in rt61pci_init_queues()
1451 rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR, ®); in rt61pci_init_queues()
1457 rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR, ®); in rt61pci_init_queues()
1463 rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR, ®); in rt61pci_init_queues()
1468 rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR, ®); in rt61pci_init_queues()
1476 rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR, ®); in rt61pci_init_queues()
1481 rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR, ®); in rt61pci_init_queues()
1488 rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®); in rt61pci_init_queues()
1495 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_init_queues()
1506 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0, ®); in rt61pci_init_registers()
1512 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1, ®); in rt61pci_init_registers()
1526 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2, ®); in rt61pci_init_registers()
1540 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3, ®); in rt61pci_init_registers()
1549 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7, ®); in rt61pci_init_registers()
1556 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8, ®); in rt61pci_init_registers()
1563 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_init_registers()
1576 rt2x00mmio_register_read(rt2x00dev, MAC_CSR9, ®); in rt61pci_init_registers()
1622 rt2x00mmio_register_read(rt2x00dev, STA_CSR0, ®); in rt61pci_init_registers()
1623 rt2x00mmio_register_read(rt2x00dev, STA_CSR1, ®); in rt61pci_init_registers()
1624 rt2x00mmio_register_read(rt2x00dev, STA_CSR2, ®); in rt61pci_init_registers()
1629 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1634 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1639 rt2x00mmio_register_read(rt2x00dev, MAC_CSR1, ®); in rt61pci_init_registers()
1725 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1728 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®); in rt61pci_toggle_irq()
1738 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1746 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_toggle_irq()
1786 rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR, ®); in rt61pci_enable_radio()
1809 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®); in rt61pci_set_state()
1820 rt2x00mmio_register_read(rt2x00dev, MAC_CSR12, ®2); in rt61pci_set_state()
1979 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, ®); in rt61pci_write_beacon()
2040 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9, &orig_reg); in rt61pci_clear_beacon()
2176 rt2x00mmio_register_read(rt2x00dev, STA_CSR4, ®); in rt61pci_txdone()
2262 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_enable_interrupt()
2280 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_enable_mcu_interrupt()
2332 rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu); in rt61pci_interrupt()
2335 rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR, ®); in rt61pci_interrupt()
2373 rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR, ®); in rt61pci_interrupt()
2377 rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®); in rt61pci_interrupt()
2397 rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR, ®); in rt61pci_validate_eeprom()
2515 rt2x00mmio_register_read(rt2x00dev, MAC_CSR0, ®); in rt61pci_init_eeprom()
2858 rt2x00mmio_register_read(rt2x00dev, MAC_CSR13, ®); in rt61pci_probe_hw()
2930 rt2x00mmio_register_read(rt2x00dev, offset, ®); in rt61pci_conf_tx()
2938 rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR, ®); in rt61pci_conf_tx()
2942 rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR, ®); in rt61pci_conf_tx()
2946 rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR, ®); in rt61pci_conf_tx()
2959 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13, ®); in rt61pci_get_tsf()
2961 rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12, ®); in rt61pci_get_tsf()