Lines Matching refs:rt2x00mmio_register_write
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
110 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
138 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
162 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
167 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
201 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
209 .write = rt2x00mmio_register_write,
297 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
374 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); in rt61pci_config_shared_key()
381 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); in rt61pci_config_shared_key()
409 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); in rt61pci_config_shared_key()
472 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
500 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
509 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
544 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
560 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
592 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
599 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
603 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, in rt61pci_config_erp()
610 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
616 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
622 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
723 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
829 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
937 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
958 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
963 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
965 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); in rt61pci_config_ps()
966 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); in rt61pci_config_ps()
975 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
977 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
979 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); in rt61pci_config_ps()
980 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); in rt61pci_config_ps()
1143 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1150 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1166 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1171 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1176 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1181 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1197 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1202 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1207 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1212 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1217 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1224 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1318 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1319 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_load_firmware()
1320 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); in rt61pci_load_firmware()
1321 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); in rt61pci_load_firmware()
1329 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1335 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1363 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1368 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1372 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1437 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1442 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1448 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1454 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1460 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1466 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1473 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1479 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1486 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1493 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1497 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1510 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1521 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1535 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1554 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1561 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1570 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1572 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); in rt61pci_init_registers()
1574 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); in rt61pci_init_registers()
1578 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1580 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); in rt61pci_init_registers()
1585 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); in rt61pci_init_registers()
1591 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); in rt61pci_init_registers()
1592 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); in rt61pci_init_registers()
1593 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); in rt61pci_init_registers()
1595 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); in rt61pci_init_registers()
1596 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
1597 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); in rt61pci_init_registers()
1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); in rt61pci_init_registers()
1600 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); in rt61pci_init_registers()
1602 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); in rt61pci_init_registers()
1604 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_init_registers()
1612 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); in rt61pci_init_registers()
1613 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); in rt61pci_init_registers()
1614 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); in rt61pci_init_registers()
1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); in rt61pci_init_registers()
1632 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1637 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1641 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1726 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1729 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1744 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1756 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1788 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1798 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); in rt61pci_disable_radio()
1812 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1824 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1982 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2002 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_write_beacon()
2019 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); in rt61pci_write_beacon()
2022 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2043 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
2048 rt2x00mmio_register_write(rt2x00dev, in rt61pci_clear_beacon()
2054 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_clear_beacon()
2264 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2282 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2316 rt2x00mmio_register_write(rt2x00dev, in rt61pci_autowake_tasklet()
2333 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); in rt61pci_interrupt()
2336 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2375 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2379 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2841 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); in rt61pci_probe_hw()
2860 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2932 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2940 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2944 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2948 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()