Lines Matching refs:RF90_PATH_D

422 	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;  in _rtl92d_phy_init_bb_rf_register_definition()
431 	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;  in _rtl92d_phy_init_bb_rf_register_definition()
457 	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;  in _rtl92d_phy_init_bb_rf_register_definition()
467 	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;  in _rtl92d_phy_init_bb_rf_register_definition()
486 	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;  in _rtl92d_phy_init_bb_rf_register_definition()
492 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;  in _rtl92d_phy_init_bb_rf_register_definition()
498 	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;  in _rtl92d_phy_init_bb_rf_register_definition()
504 	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
510 	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
516 	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTxIQIMBALANCE;  in _rtl92d_phy_init_bb_rf_register_definition()
522 	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTxAFE;  in _rtl92d_phy_init_bb_rf_register_definition()
528 	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;  in _rtl92d_phy_init_bb_rf_register_definition()
842 	case RF90_PATH_D:  in rtl92d_phy_config_rf_with_headerfile()
1183 	case RF90_PATH_D:  in _rtl92d_phy_enable_rf_env()
1219 	case RF90_PATH_D:  in _rtl92d_phy_restore_rf_env()